[PATCH 1/2] devicetree: cadence_ttc: Document binding for timer width

[PATCH 1/2] devicetree: cadence_ttc: Document binding for timer width

[Michal Simek]

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From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Modern TTC implementations can extend the timer width to 32 bit. This
feature is not self identifying so the driver needs to be made aware
via device tree.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
index 993695c659e1..5439976eca6b 100644
--- a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
+++ b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
@@ -6,6 +6,9 @@ Required properties:
 - interrupts : A list of 3 interrupts; one per timer channel.
 - clocks: phandle to the source clock

+Optional properties:
+- timer-width: Bit width of the timer. Either 16 or 32 (default 16).
+
 Example:

 ttc0: ttc0@f8001000 {
@@ -14,4 +17,5 @@ ttc0: ttc0@f8001000 {
 	compatible = "cdns,ttc";
 	reg = <0xF8001000 0x1000>;
 	clocks = <&cpu_clk 3>;
+	timer-width = <32>;
 };
--
1.8.2.3


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[PATCH 2/2] clocksource: cadence_ttc: Add support for 32bit mode

[Michal Simek]

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New TTCs support 32bit mode. Older versions support
only 16bit modes. Keep 16bit mode as default
and 32bit optional.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 drivers/clocksource/cadence_ttc_timer.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
index 7a08811df9aa..510c8a1d37b3 100644
--- a/drivers/clocksource/cadence_ttc_timer.c
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -25,7 +25,7 @@
 #include <linux/sched_clock.h>

 /*
- * This driver configures the 2 16-bit count-up timers as follows:
+ * This driver configures the 2 16/32-bit count-up timers as follows:
  *
  * T1: Timer 1, clocksource for generic timekeeping
  * T2: Timer 2, clockevent source for hrtimers
@@ -321,7 +321,8 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
 	return NOTIFY_DONE;
 }

-static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
+static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
+					 u32 timer_width)
 {
 	struct ttc_timer_clocksource *ttccs;
 	int err;
@@ -351,7 +352,7 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
 	ttccs->cs.name = "ttc_clocksource";
 	ttccs->cs.rating = 200;
 	ttccs->cs.read = __ttc_clocksource_read;
-	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
+	ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
 	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;

 	/*
@@ -372,7 +373,8 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
 	}

 	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
-	sched_clock_register(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
+	sched_clock_register(ttc_sched_clock_read, timer_width,
+			     ttccs->ttc.freq / PRESCALE);
 }

 static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
@@ -467,6 +469,7 @@ static void __init ttc_timer_init(struct device_node *timer)
 	struct clk *clk_cs, *clk_ce;
 	static int initialized;
 	int clksel;
+	u32 timer_width = 16;

 	if (initialized)
 		return;
@@ -490,6 +493,8 @@ static void __init ttc_timer_init(struct device_node *timer)
 		BUG();
 	}

+	of_property_read_u32(timer, "timer-width", &timer_width);
+
 	clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
 	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
 	clk_cs = of_clk_get(timer, clksel);
@@ -506,7 +511,7 @@ static void __init ttc_timer_init(struct device_node *timer)
 		BUG();
 	}

-	ttc_setup_clocksource(clk_cs, timer_baseaddr);
+	ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
 	ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);

 	pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
--
1.8.2.3


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Re: [PATCH 1/2] devicetree: cadence_ttc: Document binding for timer width

[Mark Rutland]

On Wed, Sep 17, 2014 at 03:30:49PM +0100, Michal Simek wrote:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> 
> Modern TTC implementations can extend the timer width to 32 bit. This
> feature is not self identifying so the driver needs to be made aware
> via device tree.
> 
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> 
>  Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
> index 993695c659e1..5439976eca6b 100644
> --- a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
> @@ -6,6 +6,9 @@ Required properties:
>  - interrupts : A list of 3 interrupts; one per timer channel.
>  - clocks: phandle to the source clock
> 
> +Optional properties:
> +- timer-width: Bit width of the timer. Either 16 or 32 (default 16).

Are we expecting TTC implementations with widths other than 16 or 32?

This looks sane to me, but we might be able to just have a 32-bit-timer
property if we don't expect arbitrary widths.

Mark.

Re: [PATCH 1/2] devicetree: cadence_ttc: Document binding for timer width

[Michal Simek]

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On 09/17/2014 06:17 PM, Mark Rutland wrote:
> On Wed, Sep 17, 2014 at 03:30:49PM +0100, Michal Simek wrote:
>> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>
>> Modern TTC implementations can extend the timer width to 32 bit. This
>> feature is not self identifying so the driver needs to be made aware
>> via device tree.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>>  Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
>> index 993695c659e1..5439976eca6b 100644
>> --- a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
>> +++ b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
>> @@ -6,6 +6,9 @@ Required properties:
>>  - interrupts : A list of 3 interrupts; one per timer channel.
>>  - clocks: phandle to the source clock
>>
>> +Optional properties:
>> +- timer-width: Bit width of the timer. Either 16 or 32 (default 16).
> 
> Are we expecting TTC implementations with widths other than 16 or 32?

IRC if you use 32bit timer and setup for example 24bit width it should work
too and you are just ignoring that upper bits.

> 
> This looks sane to me, but we might be able to just have a 32-bit-timer
> property if we don't expect arbitrary widths.

Definitely model different timer width is easily possible to do in qemu
that's why I think having more generic property timer-width is just better than
having property used just for one case.

Thanks,
Michal



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Re: [PATCH 1/2] devicetree: cadence_ttc: Document binding for timer width

[Mark Rutland]

On Thu, Sep 18, 2014 at 06:07:40AM +0100, Michal Simek wrote:
> On 09/17/2014 06:17 PM, Mark Rutland wrote:
> > On Wed, Sep 17, 2014 at 03:30:49PM +0100, Michal Simek wrote:
> >> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> >>
> >> Modern TTC implementations can extend the timer width to 32 bit. This
> >> feature is not self identifying so the driver needs to be made aware
> >> via device tree.
> >>
> >> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> >> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> >> ---
> >>
> >>  Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt | 4 ++++
> >>  1 file changed, 4 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
> >> index 993695c659e1..5439976eca6b 100644
> >> --- a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
> >> +++ b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
> >> @@ -6,6 +6,9 @@ Required properties:
> >>  - interrupts : A list of 3 interrupts; one per timer channel.
> >>  - clocks: phandle to the source clock
> >>
> >> +Optional properties:
> >> +- timer-width: Bit width of the timer. Either 16 or 32 (default 16).
> > 
> > Are we expecting TTC implementations with widths other than 16 or 32?
> 
> IRC if you use 32bit timer and setup for example 24bit width it should work
> too and you are just ignoring that upper bits.

Sure, but what I'd like to know is whether we expect HW implementations
other than 16 or 32 bit rather than whether or not the driver will work
in that case. I'm not saying no to this patch; I'm just curious.

> > This looks sane to me, but we might be able to just have a 32-bit-timer
> > property if we don't expect arbitrary widths.
> 
> Definitely model different timer width is easily possible to do in qemu
> that's why I think having more generic property timer-width is just better than
> having property used just for one case.

Ok, so if you want to support that can we change the documentation
wording to be:

- timer-width: Bit width of the timer, necessary if not 16.

That implies support for other bit widths, and when the property needs
to be set (IMO 'default' sounds too much like a driver description than
a contract description).

Does this apply to one timer register, or are multiple registers
affected?

Mark.

Re: [PATCH 1/2] devicetree: cadence_ttc: Document binding for timer width

[Michal Simek]

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On 09/18/2014 08:36 PM, Mark Rutland wrote:
> On Thu, Sep 18, 2014 at 06:07:40AM +0100, Michal Simek wrote:
>> On 09/17/2014 06:17 PM, Mark Rutland wrote:
>>> On Wed, Sep 17, 2014 at 03:30:49PM +0100, Michal Simek wrote:
>>>> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>>>
>>>> Modern TTC implementations can extend the timer width to 32 bit. This
>>>> feature is not self identifying so the driver needs to be made aware
>>>> via device tree.
>>>>
>>>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>>>> ---
>>>>
>>>>  Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt | 4 ++++
>>>>  1 file changed, 4 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
>>>> index 993695c659e1..5439976eca6b 100644
>>>> --- a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
>>>> +++ b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
>>>> @@ -6,6 +6,9 @@ Required properties:
>>>>  - interrupts : A list of 3 interrupts; one per timer channel.
>>>>  - clocks: phandle to the source clock
>>>>
>>>> +Optional properties:
>>>> +- timer-width: Bit width of the timer. Either 16 or 32 (default 16).
>>>
>>> Are we expecting TTC implementations with widths other than 16 or 32?
>>
>> IRC if you use 32bit timer and setup for example 24bit width it should work
>> too and you are just ignoring that upper bits.
> 
> Sure, but what I'd like to know is whether we expect HW implementations
> other than 16 or 32 bit rather than whether or not the driver will work
> in that case. I'm not saying no to this patch; I'm just curious.

We are trying to find this information.


>>> This looks sane to me, but we might be able to just have a 32-bit-timer
>>> property if we don't expect arbitrary widths.
>>
>> Definitely model different timer width is easily possible to do in qemu
>> that's why I think having more generic property timer-width is just better than
>> having property used just for one case.
> 
> Ok, so if you want to support that can we change the documentation
> wording to be:
> 
> - timer-width: Bit width of the timer, necessary if not 16.
> 
> That implies support for other bit widths, and when the property needs
> to be set (IMO 'default' sounds too much like a driver description than
> a contract description).

Default one is just option which is used for origin configuration
and we should be backward compatible.
I am OK with this description. Will send v2.

> Does this apply to one timer register, or are multiple registers
> affected?

It applies for all 3 timers. All of them are 16 or 32.

Thanks,
Michal


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