From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Tom Lendacky <thomas.lendacky@amd.com>,
David Woodhouse <dwmw@amazon.co.uk>, <arjan@linux.intel.com>,
<tglx@linutronix.de>, <karahmed@amazon.de>, <x86@kernel.org>,
<linux-kernel@vger.kernel.org>, <tim.c.chen@linux.intel.com>,
<bp@alien8.de>, <peterz@infradead.org>, <pbonzini@redhat.com>,
<ak@linux.intel.com>, <torvalds@linux-foundation.org>,
<gregkh@linux-foundation.org>
Subject: Re: [PATCH v2 2/8] x86/cpufeatures: Add AMD feature bits for Prediction Command
Date: Sun, 21 Jan 2018 18:01:36 +0000 [thread overview]
Message-ID: <aed6fea6-01f0-823d-0c2e-3c9b401293f1@citrix.com> (raw)
In-Reply-To: <ce7ea88c-c5d4-154c-37fd-477d517914f3@amd.com>
On 21/01/18 17:50, Tom Lendacky wrote:
> On 1/21/2018 3:49 AM, David Woodhouse wrote:
>> AMD doesn't implement the Speculation Control MSR that Intel does, but
>> the Prediction Control MSR does exist and is advertised by a separate
>> CPUID bit. Add support for that.
>>
>> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
>> ---
>> arch/x86/include/asm/cpufeatures.h | 1 +
>> arch/x86/kernel/cpu/scattered.c | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index 2efb8d4..8c9e5c0 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -207,6 +207,7 @@
>> #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */
>> #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
>>
>> +#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR (AMD) */
>> #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
>> #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */
>>
>> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
>> index df11f5d..4eb90b2 100644
>> --- a/arch/x86/kernel/cpu/scattered.c
>> +++ b/arch/x86/kernel/cpu/scattered.c
>> @@ -28,6 +28,7 @@ static const struct cpuid_bit cpuid_bits[] = {
>> { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
>> { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
>> { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
>> + { X86_FEATURE_AMD_PRED_CMD, CPUID_EBX, 12, 0x80000008, 0 },
> I replied to the previous version, but I'll add it here, too.
>
> This should be moved to the existing 0x80000008/EBX entry rather than have
> it in scattered.
>
> Also, there will be a total of three bits:
> IBPB: 0x80000008 EBX[12]
> IBRS: 0x80000008 EBX[14]
> STIBP: 0x80000008 EBX[15]
>
> Since IBRS and STIBP share the same MSR, if a processor only supports
> STIBP (MSR bit 1), for ease of software implementation the processor
> does not GP fault attempts to write bit 0. In a similar manner, if a
> processor only suppors IBRS (MSR bit 0), the processor does not GP
> fault attempts to write bit 1.
Are you able to comment on the read behaviour after a write which is
ignored?
If the behaviour is "read as written" then virt cases are fine. If the
"ignore" causes a zero to be read back, then we're still going to need
to intercept and emulate all VM accesses.
Thanks,
~Andrew
next prev parent reply other threads:[~2018-01-21 18:01 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-21 9:49 [PATCH v2 0/8] Speculation Control feature support, IBPB David Woodhouse
2018-01-21 9:49 ` [PATCH v2 1/8] x86/cpufeatures: Add Intel feature bits for Speculation Control David Woodhouse
2018-01-21 10:17 ` Ingo Molnar
2018-01-21 9:49 ` [PATCH v2 2/8] x86/cpufeatures: Add AMD feature bits for Prediction Command David Woodhouse
2018-01-21 17:50 ` Tom Lendacky
2018-01-21 18:01 ` Andrew Cooper [this message]
2018-01-22 14:31 ` Tom Lendacky
2018-01-22 14:33 ` Andrew Cooper
2018-01-21 9:49 ` [PATCH v2 3/8] x86/msr: Add definitions for new speculation control MSRs David Woodhouse
2018-01-21 13:06 ` Jiri Slaby
2018-01-21 13:27 ` David Woodhouse
2018-01-21 9:49 ` [PATCH v2 4/8] x86/pti: Do not enable PTI on fixed Intel processors David Woodhouse
2018-01-21 13:38 ` Borislav Petkov
2018-01-21 9:49 ` [PATCH v2 5/8] x86/speculation: Add basic support for IBPB David Woodhouse
2018-01-21 10:26 ` Ingo Molnar
2018-01-21 18:06 ` Borislav Petkov
2018-01-21 18:29 ` KarimAllah Ahmed
2018-01-21 19:01 ` Borislav Petkov
2018-01-21 19:31 ` David Woodhouse
2018-01-21 19:37 ` Andrew Cooper
2018-01-21 20:04 ` David Woodhouse
2018-01-21 20:19 ` Andrew Cooper
2018-01-21 21:25 ` David Woodhouse
2018-01-21 19:53 ` Borislav Petkov
2018-01-21 18:54 ` David Woodhouse
2018-01-21 19:04 ` Borislav Petkov
2018-01-21 19:31 ` David Woodhouse
2018-01-21 19:54 ` Borislav Petkov
2018-01-21 20:07 ` David Woodhouse
2018-01-21 20:17 ` Borislav Petkov
2018-01-21 9:49 ` [PATCH v2 6/8] x86/kvm: Add IBPB support David Woodhouse
2018-01-21 18:06 ` Tom Lendacky
2018-01-21 9:49 ` [PATCH v2 7/8] x86/speculation: Use Indirect Branch Prediction Barrier in context switch David Woodhouse
2018-01-21 9:49 ` [PATCH v2 8/8] x86/mm: Only flush indirect branches when switching into non dumpable process David Woodhouse
2018-01-21 10:33 ` Ingo Molnar
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