From: atull <atull@opensource.altera.com>
To: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Frank Rowand <frowand.list@gmail.com>,
Mark Rutland <mark.rutland@arm.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Jon Masters <jcm@redhat.com>,
Walter Goossens <waltergoossens@home.nl>,
Michal Simek <michal.simek@xilinx.com>,
Cyril Chemparathy <cyril.chemparathy@xilinx.com>,
Matthew Gerlach <mgerlach@opensource.altera.com>,
Dinh Nguyen <dinguyen@opensource.altera.com>,
Devicetree List <devicetree@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Alan Tull <delicious.quinoa@gmail.com>, <julia@ni.com>
Subject: Re: [PATCH v19 12/12] fpga-manager: Add Socfpga Arria10 support
Date: Thu, 29 Sep 2016 16:35:39 -0500 [thread overview]
Message-ID: <alpine.DEB.2.02.1609291615050.30756@linuxheads99> (raw)
In-Reply-To: <CAAtXAHe927JSxaCs0LK8bm57mPRKvZ7ZaAvus_XDnzcQMmdAWw@mail.gmail.com>
On Thu, 29 Sep 2016, Moritz Fischer wrote:
> Hi Alan,
>
> On Wed, Sep 28, 2016 at 11:22 AM, Alan Tull <atull@opensource.altera.com> wrote:
>
> > +static void socfpga_a10_fpga_generate_dclks(struct a10_fpga_priv *priv,
> > + u32 count)
> > +{
> > + u32 val;
> > + unsigned int i;
> > +
> > + /* Clear any existing DONE status. */
> > + regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST,
> > + A10_FPGAMGR_DCLKSTAT_DCLKDONE);
> > +
> > + /* Issue the DCLK regmap. */
> > + regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count);
> > +
> > + /* wait till the dclkcnt done */
> > + for (i = 0; i < 100; i++) {
> > + regmap_read(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, &val);
> > + if (val)
> > + break;
> > + udelay(1);
> > + }
>
> It's quite new, but regmap_read_poll_timeout() might be a good fit here?
Yes
>
> > +static int socfpga_a10_fpga_encrypted(struct fpga_manager *mgr,
> > + u32 *buf32, size_t buf32_size)
> > +{
> > + int encrypt;
> > +
> > + if (buf32_size < 70)
> > + return -EINVAL;
> > +
> > + encrypt = ((buf32[69] >> 2) & 3) != 0;
> > +
> > + dev_dbg(&mgr->dev, "header word %d = %08x encrypt=%d\n",
> > + 69, buf32[69], encrypt);
> Maybe a named constants for magic 69 / 70 value :)
Sure
>
> > +static int socfpga_a10_fpga_compressed(struct fpga_manager *mgr,
> > + u32 *buf32, size_t buf32_size)
> > +{
> > + int compress;
> > +
> > + if (buf32_size < 230)
> > + return -EINVAL;
> > +
> > + compress = !((buf32[229] >> 1) & 1);
> > +
> > + dev_dbg(&mgr->dev, "header word %d = %08x compress=%d\n",
> > + 229, buf32[229], compress);
> > +
> > + return compress;
> > +}
> Same here, a comment on 229/230 would work too I guess.
>
> > +/* Start the FPGA programming by initialize the FPGA Manager */
> > +static int socfpga_a10_fpga_write_init(struct fpga_manager *mgr,
> > + struct fpga_image_info *info,
> > + const char *buf, size_t count)
> > +{
> > + struct a10_fpga_priv *priv = mgr->priv;
> > + unsigned int cfg_width;
> > + u32 msel, stat, mask;
> > + int ret;
> > +
> > + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG)
> > + cfg_width = CFGWDTH_16;
> > + else
> > + return -EINVAL;
>
> So we can *only* do partial reconfig? Am I missing something here?
Correct, only PR for now.
>
> > + /* Do some dclks, wait for pr_ready */
> > + socfpga_a10_fpga_generate_dclks(priv, 0x7ff);
>
> Maybe a named constant?
OK. Thanks for the review!
Alan
>
> Cheers,
> Moritz
>
prev parent reply other threads:[~2016-09-29 21:50 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-28 18:21 [PATCH v19 00/12] Device Tree support for FPGA Programming Alan Tull
2016-09-28 18:21 ` [PATCH v19 01/12] fpga: add bindings document for fpga region Alan Tull
2016-10-08 20:49 ` Rob Herring
2016-10-11 19:31 ` atull
2016-09-28 18:21 ` [PATCH v19 02/12] doc: fpga-mgr: add fpga image info to api Alan Tull
2016-09-28 18:21 ` [PATCH v19 03/12] add bindings document for altera freeze bridge Alan Tull
2016-10-08 20:49 ` Rob Herring
2016-10-10 18:45 ` atull
2016-09-28 18:21 ` [PATCH v19 04/12] add sysfs document for fpga bridge class Alan Tull
2016-09-29 21:54 ` Moritz Fischer
2016-09-28 18:21 ` [PATCH v19 05/12] fpga-mgr: add fpga image information struct Alan Tull
2016-09-28 23:41 ` Moritz Fischer
2016-09-29 4:34 ` Alan Tull
2016-09-29 17:43 ` Michal Simek
2016-09-28 18:21 ` [PATCH v19 06/12] fpga: add fpga image information struct for socfpga support Alan Tull
2016-09-28 18:21 ` [PATCH v19 07/12] fpga: add fpga image information struct for zynq support Alan Tull
2016-09-28 18:21 ` [PATCH v19 08/12] fpga: add fpga bridge framework Alan Tull
2016-09-28 18:21 ` [PATCH v19 09/12] fpga: fpga-region: device tree control for FPGA Alan Tull
2016-09-28 18:21 ` [PATCH v19 10/12] ARM: socfpga: fpga bridge driver support Alan Tull
2016-09-28 18:21 ` [PATCH v19 11/12] fpga: add altera freeze bridge support Alan Tull
2016-09-28 18:22 ` [PATCH v19 12/12] fpga-manager: Add Socfpga Arria10 support Alan Tull
2016-09-29 16:49 ` Moritz Fischer
2016-09-29 21:35 ` atull [this message]
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