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From: Thomas Gleixner <tglx@linutronix.de>
To: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Ludovic Desroches <ludovic.desroches@atmel.com>,
	jason@lakedaemon.net, marc.zyngier@arm.com,
	linux-kernel@vger.kernel.org, sasha.levin@oracle.com,
	linux-arm-kernel@lists.infradead.org, nicolas.ferre@atmel.com,
	alexandre.belloni@free-electrons.com, Wenyou.Yang@atmel.com
Subject: Re: [PATCH 1/3] irqchip: atmel-aic5: fix bug with mask/unmask
Date: Tue, 22 Sep 2015 15:50:30 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.11.1509221549420.5606@nanos> (raw)
In-Reply-To: <20150922135558.7be8ac1c@bbrezillon>

On Tue, 22 Sep 2015, Boris Brezillon wrote:
> On Tue, 22 Sep 2015 12:27:08 +0200 (CEST)
> Thomas Gleixner <tglx@linutronix.de> wrote:
> > Why is this locking dgc->gc[0] and fiddling with some other generic
> > chip?
> 
> Actually, we always access the same set of registers for all irqs of the
> domain, and thus need to take the same lock (I chose the one contained
> in the first generic irqchip, but I guess it could work with the others
> too, as long as we always take the same one) before accessing them
> because the configuration is done in two steps:
> 
> 1/ specify the irq line you want to configure
> 2/ set the new configuration
> 
> Regarding register accesses, all generic chips are configured to
> point to the same registers, so accessing them from the 'base' generic
> chip or from the generic chip attached to the irq_data struct is the
> same, though I agree that using bgc would add some consistency to the
> implementation.

Fair enough. It just deserves a comment for the casual reader.

Thanks,

	tglx

  reply	other threads:[~2015-09-22 13:51 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-21 13:46 [PATCH 1/3] irqchip: atmel-aic5: fix bug with mask/unmask Ludovic Desroches
2015-09-21 13:46 ` [PATCH 2/3] irqchip: atmel-aic5: fix variable naming Ludovic Desroches
2015-09-22  8:27   ` Nicolas Ferre
2015-09-22 14:09   ` [tip:irq/core] irqchip/atmel-aic5: Use explicit variable name for the base chip tip-bot for Ludovic Desroches
2015-09-21 13:46 ` [PATCH 3/3] irqchip: atmel-aic5: simplify base chip selection Ludovic Desroches
2015-09-22  8:27   ` Nicolas Ferre
2015-09-22 14:09   ` [tip:irq/core] irqchip/atmel-aic5: Simplify " tip-bot for Ludovic Desroches
2015-09-22  7:45 ` [PATCH 1/3] irqchip: atmel-aic5: fix bug with mask/unmask Boris Brezillon
2015-09-22  8:27 ` Nicolas Ferre
2015-09-22 10:27 ` Thomas Gleixner
2015-09-22 11:55   ` Boris Brezillon
2015-09-22 13:50     ` Thomas Gleixner [this message]
2015-09-22 14:07       ` Ludovic Desroches
2015-09-22 10:30 ` [tip:irq/urgent] irqchip/atmel-aic5: Use proper mask cache in mask/unmask() tip-bot for Ludovic Desroches
2015-09-22 10:37   ` Thomas Gleixner
2015-09-22 14:00 ` [tip:irq/urgent] irqchip/atmel-aic5: Use per chip mask caches " tip-bot for Ludovic Desroches

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