* [PATCH 0/2] serial: sifive: Correct/improve baud base handling
@ 2022-04-29 20:40 Maciej W. Rozycki
2022-04-29 20:40 ` [PATCH 1/2] serial: sifive: Report actual baud base rather than fixed 115200 Maciej W. Rozycki
2022-04-29 20:40 ` [PATCH 2/2] serial: sifive: Remove duplicate `clkin_rate' setting Maciej W. Rozycki
0 siblings, 2 replies; 3+ messages in thread
From: Maciej W. Rozycki @ 2022-04-29 20:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Palmer Dabbelt, Paul Walmsley
Cc: Damien Le Moal, linux-serial, linux-riscv, linux-kernel
Hi,
While fiddling with other serial port devices with the use of my HiFive
Unmatched board I have noticed we do not correctly report the baud base
value for the SiFive FU740-C000 SOC's on-chip UARTs. This small patch
set fixes the initialisation of the baud base value and then simplifies
handling by removing now redundant duplicate port parameter.
See individual change descriptions for details. This patch set has been
verified with the HiFive Unmatched board. Please apply.
Maciej
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/2] serial: sifive: Report actual baud base rather than fixed 115200
2022-04-29 20:40 [PATCH 0/2] serial: sifive: Correct/improve baud base handling Maciej W. Rozycki
@ 2022-04-29 20:40 ` Maciej W. Rozycki
2022-04-29 20:40 ` [PATCH 2/2] serial: sifive: Remove duplicate `clkin_rate' setting Maciej W. Rozycki
1 sibling, 0 replies; 3+ messages in thread
From: Maciej W. Rozycki @ 2022-04-29 20:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Palmer Dabbelt, Paul Walmsley
Cc: Damien Le Moal, linux-serial, linux-riscv, linux-kernel
The base baud value reported is supposed to be the highest baud rate
that can be set for a serial port. The SiFive FU740-C000 SOC's on-chip
UART supports baud rates of up to 1/16 of the input clock rate, which is
the bus clock `tlclk'[1], often at 130MHz in the case of the HiFive
Unmatched board.
However the sifive UART driver reports a fixed value of 115200 instead:
10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 1, base_baud = 115200) is a SiFive UART v0
10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 2, base_baud = 115200) is a SiFive UART v0
even though we already support setting higher baud rates, e.g.:
$ tty
/dev/ttySIF1
$ stty speed
230400
The baud base value is computed by the serial core by dividing the UART
clock recorded in `struct uart_port' by 16, which is also the minimum
value of the clock divider supported, so correct the baud base value
reported by setting the UART clock recorded to the input clock rate
rather than 115200:
10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 1, base_baud = 8125000) is a SiFive UART v0
10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 2, base_baud = 8125000) is a SiFive UART v0
References:
[1] "SiFive FU740-C000 Manual", v1p3, SiFive, Inc., August 13, 2021,
Section 16.9 "Baud Rate Divisor Register (div)", pp.143-144
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Fixes: 1f1496a923b6 ("riscv: Fix sifive serial driver")
---
drivers/tty/serial/sifive.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
linux-serial-sifive-base-baud.diff
Index: linux-macro/drivers/tty/serial/sifive.c
===================================================================
--- linux-macro.orig/drivers/tty/serial/sifive.c
+++ linux-macro/drivers/tty/serial/sifive.c
@@ -998,7 +998,7 @@ static int sifive_serial_probe(struct pl
/* Set up clock divider */
ssp->clkin_rate = clk_get_rate(ssp->clk);
ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
- ssp->port.uartclk = ssp->baud_rate * 16;
+ ssp->port.uartclk = ssp->clkin_rate;
__ssp_update_div(ssp);
platform_set_drvdata(pdev, ssp);
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 2/2] serial: sifive: Remove duplicate `clkin_rate' setting
2022-04-29 20:40 [PATCH 0/2] serial: sifive: Correct/improve baud base handling Maciej W. Rozycki
2022-04-29 20:40 ` [PATCH 1/2] serial: sifive: Report actual baud base rather than fixed 115200 Maciej W. Rozycki
@ 2022-04-29 20:40 ` Maciej W. Rozycki
1 sibling, 0 replies; 3+ messages in thread
From: Maciej W. Rozycki @ 2022-04-29 20:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Palmer Dabbelt, Paul Walmsley
Cc: Damien Le Moal, linux-serial, linux-riscv, linux-kernel
The `clkin_rate' member of `struct sifive_serial_port' now duplicates
`uartclk' from nested `struct uart_port', so use `uartclk' throughout
and remove `clkin_rate'.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
---
drivers/tty/serial/sifive.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
linux-serial-sifive-uartclk.diff
Index: linux-macro/drivers/tty/serial/sifive.c
===================================================================
--- linux-macro.orig/drivers/tty/serial/sifive.c
+++ linux-macro/drivers/tty/serial/sifive.c
@@ -148,7 +148,6 @@
* @port: struct uart_port embedded in this struct
* @dev: struct device *
* @ier: shadowed copy of the interrupt enable register
- * @clkin_rate: input clock to the UART IP block.
* @baud_rate: UART serial line rate (e.g., 115200 baud)
* @clk: reference to this device's clock
* @clk_notifier: clock rate change notifier for upstream clock changes
@@ -159,7 +158,6 @@ struct sifive_serial_port {
struct uart_port port;
struct device *dev;
unsigned char ier;
- unsigned long clkin_rate;
unsigned long baud_rate;
struct clk *clk;
struct notifier_block clk_notifier;
@@ -463,7 +461,7 @@ static void __ssp_update_div(struct sifi
{
u16 div;
- div = DIV_ROUND_UP(ssp->clkin_rate, ssp->baud_rate) - 1;
+ div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1;
__ssp_writel(div, SIFIVE_SERIAL_DIV_OFFS, ssp);
}
@@ -648,8 +646,8 @@ static int sifive_serial_clk_notifier(st
udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));
}
- if (event == POST_RATE_CHANGE && ssp->clkin_rate != cnd->new_rate) {
- ssp->clkin_rate = cnd->new_rate;
+ if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) {
+ ssp->port.uartclk = cnd->new_rate;
__ssp_update_div(ssp);
}
@@ -678,7 +676,8 @@ static void sifive_serial_set_termios(st
__ssp_set_stop_bits(ssp, nstop);
/* Set line rate */
- rate = uart_get_baud_rate(port, termios, old, 0, ssp->clkin_rate / 16);
+ rate = uart_get_baud_rate(port, termios, old, 0,
+ ssp->port.uartclk / 16);
__ssp_update_baud_rate(ssp, rate);
spin_lock_irqsave(&ssp->port.lock, flags);
@@ -996,9 +995,8 @@ static int sifive_serial_probe(struct pl
}
/* Set up clock divider */
- ssp->clkin_rate = clk_get_rate(ssp->clk);
+ ssp->port.uartclk = clk_get_rate(ssp->clk);
ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
- ssp->port.uartclk = ssp->clkin_rate;
__ssp_update_div(ssp);
platform_set_drvdata(pdev, ssp);
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-04-29 20:40 UTC | newest]
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2022-04-29 20:40 [PATCH 0/2] serial: sifive: Correct/improve baud base handling Maciej W. Rozycki
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2022-04-29 20:40 ` [PATCH 2/2] serial: sifive: Remove duplicate `clkin_rate' setting Maciej W. Rozycki
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