* x86/events/intel/ds: Fix bts_interrupt_threshold alignment
@ 2018-07-13 22:48 Hugh Dickins
2018-07-14 19:58 ` [PATCH] " Hugh Dickins
0 siblings, 1 reply; 3+ messages in thread
From: Hugh Dickins @ 2018-07-13 22:48 UTC (permalink / raw)
To: Ingo Molnar
Cc: Thomas Gleixner, Metzger, Markus T, Peter Zijlstra,
Arnaldo Carvalho de Melo, Shishkin, Alexander, Kleen, Andi,
Hansen, Dave, Stephane Eranian, linux-kernel
Markus reported that BTS is sporadically missing the tail of the trace
in the perf_event data buffer: [decode error (1): instruction overflow]
shown in GDB; and bisected it to the conversion of debug_store to PTI.
A little "optimization" crept into alloc_bts_buffer(), which mistakenly
placed bts_interrupt_threshold away from the 24-byte record boundary.
Intel SDM Vol 3B 17.4.9 says "This address must point to an offset from
the BTS buffer base that is a multiple of the BTS record size."
Revert "max" from a byte count to a record count, to calculate the
bts_interrupt_threshold correctly: which turns out to fix problem seen.
Fixes: c1961a4631da ("x86/events/intel/ds: Map debug buffers in cpu_entry_area")
Signed-off-by: Hugh Dickins <hughd@google.com>
Reported-and-tested-by: Markus T Metzger <markus.t.metzger@intel.com>
Cc: <stable@vger.kernel.org> # v4.14+
---
arch/x86/events/intel/ds.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
--- 4.18-rc4/arch/x86/events/intel/ds.c 2018-06-03 14:15:21.000000000 -0700
+++ linux/arch/x86/events/intel/ds.c 2018-07-12 17:38:28.471378616 -0700
@@ -408,9 +408,11 @@ static int alloc_bts_buffer(int cpu)
ds->bts_buffer_base = (unsigned long) cea;
ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
ds->bts_index = ds->bts_buffer_base;
- max = BTS_RECORD_SIZE * (BTS_BUFFER_SIZE / BTS_RECORD_SIZE);
- ds->bts_absolute_maximum = ds->bts_buffer_base + max;
- ds->bts_interrupt_threshold = ds->bts_absolute_maximum - (max / 16);
+ max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
+ ds->bts_absolute_maximum = ds->bts_buffer_base +
+ max * BTS_RECORD_SIZE;
+ ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
+ (max / 16) * BTS_RECORD_SIZE;
return 0;
}
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] x86/events/intel/ds: Fix bts_interrupt_threshold alignment
2018-07-13 22:48 x86/events/intel/ds: Fix bts_interrupt_threshold alignment Hugh Dickins
@ 2018-07-14 19:58 ` Hugh Dickins
2018-07-15 9:42 ` [tip:x86/pti] " tip-bot for Hugh Dickins
0 siblings, 1 reply; 3+ messages in thread
From: Hugh Dickins @ 2018-07-14 19:58 UTC (permalink / raw)
To: Ingo Molnar
Cc: Thomas Gleixner, Metzger, Markus T, Peter Zijlstra,
Arnaldo Carvalho de Melo, Shishkin, Alexander, Kleen, Andi,
Hansen, Dave, Stephane Eranian, linux-kernel, x86
Markus reported that BTS is sporadically missing the tail of the trace
in the perf_event data buffer: [decode error (1): instruction overflow]
shown in GDB; and bisected it to the conversion of debug_store to PTI.
A little "optimization" crept into alloc_bts_buffer(), which mistakenly
placed bts_interrupt_threshold away from the 24-byte record boundary.
Intel SDM Vol 3B 17.4.9 says "This address must point to an offset from
the BTS buffer base that is a multiple of the BTS record size."
Revert "max" from a byte count to a record count, to calculate the
bts_interrupt_threshold correctly: which turns out to fix problem seen.
Fixes: c1961a4631da ("x86/events/intel/ds: Map debug buffers in cpu_entry_area")
Signed-off-by: Hugh Dickins <hughd@google.com>
Reported-and-tested-by: Markus T Metzger <markus.t.metzger@intel.com>
Cc: <stable@vger.kernel.org> # v4.14+
---
Sorry for the spam: I missed out [PATCH] and x86@kernel.org yesterday.
arch/x86/events/intel/ds.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
--- 4.18-rc4/arch/x86/events/intel/ds.c 2018-06-03 14:15:21.000000000 -0700
+++ linux/arch/x86/events/intel/ds.c 2018-07-12 17:38:28.471378616 -0700
@@ -408,9 +408,11 @@ static int alloc_bts_buffer(int cpu)
ds->bts_buffer_base = (unsigned long) cea;
ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
ds->bts_index = ds->bts_buffer_base;
- max = BTS_RECORD_SIZE * (BTS_BUFFER_SIZE / BTS_RECORD_SIZE);
- ds->bts_absolute_maximum = ds->bts_buffer_base + max;
- ds->bts_interrupt_threshold = ds->bts_absolute_maximum - (max / 16);
+ max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
+ ds->bts_absolute_maximum = ds->bts_buffer_base +
+ max * BTS_RECORD_SIZE;
+ ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
+ (max / 16) * BTS_RECORD_SIZE;
return 0;
}
^ permalink raw reply [flat|nested] 3+ messages in thread
* [tip:x86/pti] x86/events/intel/ds: Fix bts_interrupt_threshold alignment
2018-07-14 19:58 ` [PATCH] " Hugh Dickins
@ 2018-07-15 9:42 ` tip-bot for Hugh Dickins
0 siblings, 0 replies; 3+ messages in thread
From: tip-bot for Hugh Dickins @ 2018-07-15 9:42 UTC (permalink / raw)
To: linux-tip-commits
Cc: mingo, hpa, markus.t.metzger, dave.hansen, linux-kernel, acme,
eranian, alexander.shishkin, andi.kleen, hughd, tglx, peterz
Commit-ID: 2c991e408df6a407476dbc453d725e1e975479e7
Gitweb: https://git.kernel.org/tip/2c991e408df6a407476dbc453d725e1e975479e7
Author: Hugh Dickins <hughd@google.com>
AuthorDate: Sat, 14 Jul 2018 12:58:07 -0700
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Sun, 15 Jul 2018 11:38:44 +0200
x86/events/intel/ds: Fix bts_interrupt_threshold alignment
Markus reported that BTS is sporadically missing the tail of the trace
in the perf_event data buffer: [decode error (1): instruction overflow]
shown in GDB; and bisected it to the conversion of debug_store to PTI.
A little "optimization" crept into alloc_bts_buffer(), which mistakenly
placed bts_interrupt_threshold away from the 24-byte record boundary.
Intel SDM Vol 3B 17.4.9 says "This address must point to an offset from
the BTS buffer base that is a multiple of the BTS record size."
Revert "max" from a byte count to a record count, to calculate the
bts_interrupt_threshold correctly: which turns out to fix problem seen.
Fixes: c1961a4631da ("x86/events/intel/ds: Map debug buffers in cpu_entry_area")
Reported-and-tested-by: Markus T Metzger <markus.t.metzger@intel.com>
Signed-off-by: Hugh Dickins <hughd@google.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <andi.kleen@intel.com>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: stable@vger.kernel.org # v4.14+
Link: https://lkml.kernel.org/r/alpine.LSU.2.11.1807141248290.1614@eggly.anvils
---
arch/x86/events/intel/ds.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 8a10a045b57b..8cf03f101938 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -408,9 +408,11 @@ static int alloc_bts_buffer(int cpu)
ds->bts_buffer_base = (unsigned long) cea;
ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
ds->bts_index = ds->bts_buffer_base;
- max = BTS_RECORD_SIZE * (BTS_BUFFER_SIZE / BTS_RECORD_SIZE);
- ds->bts_absolute_maximum = ds->bts_buffer_base + max;
- ds->bts_interrupt_threshold = ds->bts_absolute_maximum - (max / 16);
+ max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
+ ds->bts_absolute_maximum = ds->bts_buffer_base +
+ max * BTS_RECORD_SIZE;
+ ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
+ (max / 16) * BTS_RECORD_SIZE;
return 0;
}
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-07-15 9:43 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-13 22:48 x86/events/intel/ds: Fix bts_interrupt_threshold alignment Hugh Dickins
2018-07-14 19:58 ` [PATCH] " Hugh Dickins
2018-07-15 9:42 ` [tip:x86/pti] " tip-bot for Hugh Dickins
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).