[PATCH 0/2] reset: reset-zynqmp: Added Versal platform support

[PATCH 0/2] reset: reset-zynqmp: Added Versal platform support

[Sai Krishna Potthuri]

Extended the ZynqMP reset driver to support Versal platform, accordingly
updated the dt-binding with the Versal platform specific information
like compatible string and reset indices.

Sai Krishna Potthuri (2):
  dt-bindings: reset: Updated binding for Versal reset driver
  reset: reset-zynqmp: Added support for Versal platform

 .../bindings/reset/xlnx,zynqmp-reset.txt      |  11 +-
 drivers/reset/reset-zynqmp.c                  |  24 +++-
 .../dt-bindings/reset/xlnx-versal-resets.h    | 105 ++++++++++++++++++
 3 files changed, 132 insertions(+), 8 deletions(-)
 create mode 100644 include/dt-bindings/reset/xlnx-versal-resets.h

-- 
2.17.1

[PATCH 1/2] dt-bindings: reset: Updated binding for Versal reset driver

[Sai Krishna Potthuri]

Added documentation and Versal reset indices to describe
about Versal reset driver bindings.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
---
 .../bindings/reset/xlnx,zynqmp-reset.txt      |  11 +-
 .../dt-bindings/reset/xlnx-versal-resets.h    | 105 ++++++++++++++++++
 2 files changed, 112 insertions(+), 4 deletions(-)
 create mode 100644 include/dt-bindings/reset/xlnx-versal-resets.h

diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
index 27a45fe5ecf1..ed836868dbf1 100644
--- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
+++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
@@ -1,7 +1,7 @@
 --------------------------------------------------------------------------
- =  Zynq UltraScale+ MPSoC reset driver binding =
+ =  Zynq UltraScale+ MPSoC and Versal reset driver binding =
 --------------------------------------------------------------------------
-The Zynq UltraScale+ MPSoC has several different resets.
+The Zynq UltraScale+ MPSoC and Versal has several different resets.
 
 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
 about zynqmp resets.
@@ -10,7 +10,8 @@ Please also refer to reset.txt in this directory for common reset
 controller binding usage.
 
 Required Properties:
-- compatible:	"xlnx,zynqmp-reset"
+- compatible:	"xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
+		"xlnx,versal-reset" for Versal platform
 - #reset-cells:	Specifies the number of cells needed to encode reset
 		line, should be 1
 
@@ -37,8 +38,10 @@ Device nodes that need access to reset lines should
 specify them as a reset phandle in their corresponding node as
 specified in reset.txt.
 
-For list of all valid reset indicies see
+For list of all valid reset indices for Zynq UltraScale+ MPSoC see
 <dt-bindings/reset/xlnx-zynqmp-resets.h>
+For list of all valid reset indices for Versal see
+<dt-bindings/reset/xlnx-versal-resets.h>
 
 Example:
 
diff --git a/include/dt-bindings/reset/xlnx-versal-resets.h b/include/dt-bindings/reset/xlnx-versal-resets.h
new file mode 100644
index 000000000000..895424e9b0e5
--- /dev/null
+++ b/include/dt-bindings/reset/xlnx-versal-resets.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_VERSAL_RESETS_H
+#define _DT_BINDINGS_VERSAL_RESETS_H
+
+#define VERSAL_RST_PMC_POR			(0xc30c001U)
+#define VERSAL_RST_PMC				(0xc410002U)
+#define VERSAL_RST_PS_POR			(0xc30c003U)
+#define VERSAL_RST_PL_POR			(0xc30c004U)
+#define VERSAL_RST_NOC_POR			(0xc30c005U)
+#define VERSAL_RST_FPD_POR			(0xc30c006U)
+#define VERSAL_RST_ACPU_0_POR			(0xc30c007U)
+#define VERSAL_RST_ACPU_1_POR			(0xc30c008U)
+#define VERSAL_RST_OCM2_POR			(0xc30c009U)
+#define VERSAL_RST_PS_SRST			(0xc41000aU)
+#define VERSAL_RST_PL_SRST			(0xc41000bU)
+#define VERSAL_RST_NOC				(0xc41000cU)
+#define VERSAL_RST_NPI				(0xc41000dU)
+#define VERSAL_RST_SYS_RST_1			(0xc41000eU)
+#define VERSAL_RST_SYS_RST_2			(0xc41000fU)
+#define VERSAL_RST_SYS_RST_3			(0xc410010U)
+#define VERSAL_RST_FPD				(0xc410011U)
+#define VERSAL_RST_PL0				(0xc410012U)
+#define VERSAL_RST_PL1				(0xc410013U)
+#define VERSAL_RST_PL2				(0xc410014U)
+#define VERSAL_RST_PL3				(0xc410015U)
+#define VERSAL_RST_APU				(0xc410016U)
+#define VERSAL_RST_ACPU_0			(0xc410017U)
+#define VERSAL_RST_ACPU_1			(0xc410018U)
+#define VERSAL_RST_ACPU_L2			(0xc410019U)
+#define VERSAL_RST_ACPU_GIC			(0xc41001aU)
+#define VERSAL_RST_RPU_ISLAND			(0xc41001bU)
+#define VERSAL_RST_RPU_AMBA			(0xc41001cU)
+#define VERSAL_RST_R5_0				(0xc41001dU)
+#define VERSAL_RST_R5_1				(0xc41001eU)
+#define VERSAL_RST_SYSMON_PMC_SEQ_RST		(0xc41001fU)
+#define VERSAL_RST_SYSMON_PMC_CFG_RST		(0xc410020U)
+#define VERSAL_RST_SYSMON_FPD_CFG_RST		(0xc410021U)
+#define VERSAL_RST_SYSMON_FPD_SEQ_RST		(0xc410022U)
+#define VERSAL_RST_SYSMON_LPD			(0xc410023U)
+#define VERSAL_RST_PDMA_RST1			(0xc410024U)
+#define VERSAL_RST_PDMA_RST0			(0xc410025U)
+#define VERSAL_RST_ADMA				(0xc410026U)
+#define VERSAL_RST_TIMESTAMP			(0xc410027U)
+#define VERSAL_RST_OCM				(0xc410028U)
+#define VERSAL_RST_OCM2_RST			(0xc410029U)
+#define VERSAL_RST_IPI				(0xc41002aU)
+#define VERSAL_RST_SBI				(0xc41002bU)
+#define VERSAL_RST_LPD				(0xc41002cU)
+#define VERSAL_RST_QSPI				(0xc10402dU)
+#define VERSAL_RST_OSPI				(0xc10402eU)
+#define VERSAL_RST_SDIO_0			(0xc10402fU)
+#define VERSAL_RST_SDIO_1			(0xc104030U)
+#define VERSAL_RST_I2C_PMC			(0xc104031U)
+#define VERSAL_RST_GPIO_PMC			(0xc104032U)
+#define VERSAL_RST_GEM_0			(0xc104033U)
+#define VERSAL_RST_GEM_1			(0xc104034U)
+#define VERSAL_RST_SPARE			(0xc104035U)
+#define VERSAL_RST_USB_0			(0xc104036U)
+#define VERSAL_RST_UART_0			(0xc104037U)
+#define VERSAL_RST_UART_1			(0xc104038U)
+#define VERSAL_RST_SPI_0			(0xc104039U)
+#define VERSAL_RST_SPI_1			(0xc10403aU)
+#define VERSAL_RST_CAN_FD_0			(0xc10403bU)
+#define VERSAL_RST_CAN_FD_1			(0xc10403cU)
+#define VERSAL_RST_I2C_0			(0xc10403dU)
+#define VERSAL_RST_I2C_1			(0xc10403eU)
+#define VERSAL_RST_GPIO_LPD			(0xc10403fU)
+#define VERSAL_RST_TTC_0			(0xc104040U)
+#define VERSAL_RST_TTC_1			(0xc104041U)
+#define VERSAL_RST_TTC_2			(0xc104042U)
+#define VERSAL_RST_TTC_3			(0xc104043U)
+#define VERSAL_RST_SWDT_FPD			(0xc104044U)
+#define VERSAL_RST_SWDT_LPD			(0xc104045U)
+#define VERSAL_RST_USB				(0xc104046U)
+#define VERSAL_RST_DPC				(0xc208047U)
+#define VERSAL_RST_PMCDBG			(0xc208048U)
+#define VERSAL_RST_DBG_TRACE			(0xc208049U)
+#define VERSAL_RST_DBG_FPD			(0xc20804aU)
+#define VERSAL_RST_DBG_TSTMP			(0xc20804bU)
+#define VERSAL_RST_RPU0_DBG			(0xc20804cU)
+#define VERSAL_RST_RPU1_DBG			(0xc20804dU)
+#define VERSAL_RST_HSDP				(0xc20804eU)
+#define VERSAL_RST_DBG_LPD			(0xc20804fU)
+#define VERSAL_RST_CPM_POR			(0xc30c050U)
+#define VERSAL_RST_CPM				(0xc410051U)
+#define VERSAL_RST_CPMDBG			(0xc208052U)
+#define VERSAL_RST_PCIE_CFG			(0xc410053U)
+#define VERSAL_RST_PCIE_CORE0			(0xc410054U)
+#define VERSAL_RST_PCIE_CORE1			(0xc410055U)
+#define VERSAL_RST_PCIE_DMA			(0xc410056U)
+#define VERSAL_RST_CMN				(0xc410057U)
+#define VERSAL_RST_L2_0				(0xc410058U)
+#define VERSAL_RST_L2_1				(0xc410059U)
+#define VERSAL_RST_ADDR_REMAP			(0xc41005aU)
+#define VERSAL_RST_CPI0				(0xc41005bU)
+#define VERSAL_RST_CPI1				(0xc41005cU)
+#define VERSAL_RST_XRAM				(0xc30c05dU)
+#define VERSAL_RST_AIE_ARRAY			(0xc10405eU)
+#define VERSAL_RST_AIE_SHIM			(0xc10405fU)
+
+#endif
-- 
2.17.1

[PATCH 2/2] reset: reset-zynqmp: Added support for Versal platform

[Sai Krishna Potthuri]

Updated the reset driver to support Versal platform.
As part of adding Versal support
- Added Versal specific compatible string.
- Reset Id and number of resets are different for Versal and ZynqMP,
hence taken care of these two based on compatible string.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
---
 drivers/reset/reset-zynqmp.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c
index 373ea8d4f7a1..17aa4532ec5e 100644
--- a/drivers/reset/reset-zynqmp.c
+++ b/drivers/reset/reset-zynqmp.c
@@ -12,9 +12,11 @@
 
 #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
 #define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
+#define VERSAL_NR_RESETS	95
 
 struct zynqmp_reset_data {
 	struct reset_controller_dev rcdev;
+	u32 reset_id;
 };
 
 static inline struct zynqmp_reset_data *
@@ -26,23 +28,28 @@ to_zynqmp_reset_data(struct reset_controller_dev *rcdev)
 static int zynqmp_reset_assert(struct reset_controller_dev *rcdev,
 			       unsigned long id)
 {
-	return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
+	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
+
+	return zynqmp_pm_reset_assert(priv->reset_id + id,
 				      PM_RESET_ACTION_ASSERT);
 }
 
 static int zynqmp_reset_deassert(struct reset_controller_dev *rcdev,
 				 unsigned long id)
 {
-	return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
+	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
+
+	return zynqmp_pm_reset_assert(priv->reset_id + id,
 				      PM_RESET_ACTION_RELEASE);
 }
 
 static int zynqmp_reset_status(struct reset_controller_dev *rcdev,
 			       unsigned long id)
 {
+	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
 	int val, err;
 
-	err = zynqmp_pm_reset_get_status(ZYNQMP_RESET_ID + id, &val);
+	err = zynqmp_pm_reset_get_status(priv->reset_id + id, &val);
 	if (err)
 		return err;
 
@@ -52,7 +59,9 @@ static int zynqmp_reset_status(struct reset_controller_dev *rcdev,
 static int zynqmp_reset_reset(struct reset_controller_dev *rcdev,
 			      unsigned long id)
 {
-	return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
+	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
+
+	return zynqmp_pm_reset_assert(priv->reset_id + id,
 				      PM_RESET_ACTION_PULSE);
 }
 
@@ -76,13 +85,20 @@ static int zynqmp_reset_probe(struct platform_device *pdev)
 	priv->rcdev.ops = &zynqmp_reset_ops;
 	priv->rcdev.owner = THIS_MODULE;
 	priv->rcdev.of_node = pdev->dev.of_node;
+	priv->reset_id = ZYNQMP_RESET_ID;
 	priv->rcdev.nr_resets = ZYNQMP_NR_RESETS;
+	if (of_device_is_compatible(pdev->dev.of_node,
+				    "xlnx,versal-reset")) {
+		priv->reset_id = 0;
+		priv->rcdev.nr_resets = VERSAL_NR_RESETS;
+	}
 
 	return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
 }
 
 static const struct of_device_id zynqmp_reset_dt_ids[] = {
 	{ .compatible = "xlnx,zynqmp-reset", },
+	{ .compatible = "xlnx,versal-reset", },
 	{ /* sentinel */ },
 };
 
-- 
2.17.1

Re: [PATCH 2/2] reset: reset-zynqmp: Added support for Versal platform

[Philipp Zabel]

On Tue, 2020-07-14 at 11:59 +0530, Sai Krishna Potthuri wrote:
> Updated the reset driver to support Versal platform.
> As part of adding Versal support
> - Added Versal specific compatible string.
> - Reset Id and number of resets are different for Versal and ZynqMP,
> hence taken care of these two based on compatible string.
> 
> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
> ---
>  drivers/reset/reset-zynqmp.c | 24 ++++++++++++++++++++----
>  1 file changed, 20 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c
> index 373ea8d4f7a1..17aa4532ec5e 100644
> --- a/drivers/reset/reset-zynqmp.c
> +++ b/drivers/reset/reset-zynqmp.c
> @@ -12,9 +12,11 @@
>  
>  #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
>  #define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
> +#define VERSAL_NR_RESETS	95
>  
>  struct zynqmp_reset_data {
>  	struct reset_controller_dev rcdev;
> +	u32 reset_id;
>  };
>  
>  static inline struct zynqmp_reset_data *
> @@ -26,23 +28,28 @@ to_zynqmp_reset_data(struct reset_controller_dev *rcdev)
>  static int zynqmp_reset_assert(struct reset_controller_dev *rcdev,
>  			       unsigned long id)
>  {
> -	return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
> +	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
> +
> +	return zynqmp_pm_reset_assert(priv->reset_id + id,
>  				      PM_RESET_ACTION_ASSERT);
>  }
>  
>  static int zynqmp_reset_deassert(struct reset_controller_dev *rcdev,
>  				 unsigned long id)
>  {
> -	return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
> +	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
> +
> +	return zynqmp_pm_reset_assert(priv->reset_id + id,
>  				      PM_RESET_ACTION_RELEASE);
>  }
>  
>  static int zynqmp_reset_status(struct reset_controller_dev *rcdev,
>  			       unsigned long id)
>  {
> +	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
>  	int val, err;
>  
> -	err = zynqmp_pm_reset_get_status(ZYNQMP_RESET_ID + id, &val);
> +	err = zynqmp_pm_reset_get_status(priv->reset_id + id, &val);
>  	if (err)
>  		return err;
>  
> @@ -52,7 +59,9 @@ static int zynqmp_reset_status(struct reset_controller_dev *rcdev,
>  static int zynqmp_reset_reset(struct reset_controller_dev *rcdev,
>  			      unsigned long id)
>  {
> -	return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
> +	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
> +
> +	return zynqmp_pm_reset_assert(priv->reset_id + id,
>  				      PM_RESET_ACTION_PULSE);
>  }
>  
> @@ -76,13 +85,20 @@ static int zynqmp_reset_probe(struct platform_device *pdev)
>  	priv->rcdev.ops = &zynqmp_reset_ops;
>  	priv->rcdev.owner = THIS_MODULE;
>  	priv->rcdev.of_node = pdev->dev.of_node;
> +	priv->reset_id = ZYNQMP_RESET_ID;
>  	priv->rcdev.nr_resets = ZYNQMP_NR_RESETS;
> +	if (of_device_is_compatible(pdev->dev.of_node,
> +				    "xlnx,versal-reset")) {

It would be better to use of_match_device and static const initalization
data for this.

> +		priv->reset_id = 0;
> +		priv->rcdev.nr_resets = VERSAL_NR_RESETS;

This won't work. All your reset ids are greater than 95, and this driver
is using the default of_xlate callback, so of_reset_simple_xlate will
fail all reset control requests with -EINVAL.

regards
Philipp

RE: [PATCH 2/2] reset: reset-zynqmp: Added support for Versal platform

[Sai Krishna Potthuri]

Hi Philipp,

Thanks for the review.

> -----Original Message-----
> From: Philipp Zabel <p.zabel@pengutronix.de>
> Sent: Monday, July 20, 2020 3:18 PM
> To: Sai Krishna Potthuri <lakshmis@xilinx.com>; Rob Herring
> <robh+dt@kernel.org>; Michal Simek <michals@xilinx.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; git <git@xilinx.com>; saikrishna12468@gmail.com
> Subject: Re: [PATCH 2/2] reset: reset-zynqmp: Added support for Versal
> platform
> 
> On Tue, 2020-07-14 at 11:59 +0530, Sai Krishna Potthuri wrote:
> > Updated the reset driver to support Versal platform.
> > As part of adding Versal support
> > - Added Versal specific compatible string.
> > - Reset Id and number of resets are different for Versal and ZynqMP,
> > hence taken care of these two based on compatible string.
> >
> > Signed-off-by: Sai Krishna Potthuri
> > <lakshmi.sai.krishna.potthuri@xilinx.com>
> > ---
> >  drivers/reset/reset-zynqmp.c | 24 ++++++++++++++++++++----
> >  1 file changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/reset/reset-zynqmp.c
> > b/drivers/reset/reset-zynqmp.c index 373ea8d4f7a1..17aa4532ec5e
> 100644
> > --- a/drivers/reset/reset-zynqmp.c
> > +++ b/drivers/reset/reset-zynqmp.c
> > @@ -12,9 +12,11 @@
> >
> >  #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END -
> > ZYNQMP_PM_RESET_START)  #define ZYNQMP_RESET_ID
> ZYNQMP_PM_RESET_START
> > +#define VERSAL_NR_RESETS	95
> >
> >  struct zynqmp_reset_data {
> >  	struct reset_controller_dev rcdev;
> > +	u32 reset_id;
> >  };
> >
> >  static inline struct zynqmp_reset_data * @@ -26,23 +28,28 @@
> > to_zynqmp_reset_data(struct reset_controller_dev *rcdev)  static int
> > zynqmp_reset_assert(struct reset_controller_dev *rcdev,
> >  			       unsigned long id)
> >  {
> > -	return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
> > +	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
> > +
> > +	return zynqmp_pm_reset_assert(priv->reset_id + id,
> >  				      PM_RESET_ACTION_ASSERT);
> >  }
> >
> >  static int zynqmp_reset_deassert(struct reset_controller_dev *rcdev,
> >  				 unsigned long id)
> >  {
> > -	return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
> > +	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
> > +
> > +	return zynqmp_pm_reset_assert(priv->reset_id + id,
> >  				      PM_RESET_ACTION_RELEASE);
> >  }
> >
> >  static int zynqmp_reset_status(struct reset_controller_dev *rcdev,
> >  			       unsigned long id)
> >  {
> > +	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
> >  	int val, err;
> >
> > -	err = zynqmp_pm_reset_get_status(ZYNQMP_RESET_ID + id, &val);
> > +	err = zynqmp_pm_reset_get_status(priv->reset_id + id, &val);
> >  	if (err)
> >  		return err;
> >
> > @@ -52,7 +59,9 @@ static int zynqmp_reset_status(struct
> > reset_controller_dev *rcdev,  static int zynqmp_reset_reset(struct
> reset_controller_dev *rcdev,
> >  			      unsigned long id)
> >  {
> > -	return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
> > +	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
> > +
> > +	return zynqmp_pm_reset_assert(priv->reset_id + id,
> >  				      PM_RESET_ACTION_PULSE);
> >  }
> >
> > @@ -76,13 +85,20 @@ static int zynqmp_reset_probe(struct
> platform_device *pdev)
> >  	priv->rcdev.ops = &zynqmp_reset_ops;
> >  	priv->rcdev.owner = THIS_MODULE;
> >  	priv->rcdev.of_node = pdev->dev.of_node;
> > +	priv->reset_id = ZYNQMP_RESET_ID;
> >  	priv->rcdev.nr_resets = ZYNQMP_NR_RESETS;
> > +	if (of_device_is_compatible(pdev->dev.of_node,
> > +				    "xlnx,versal-reset")) {
> 
> It would be better to use of_match_device and static const initalization data
> for this.
Will create soc specific initialization data structure and assign based on
of_device_get_match_data().

> 
> > +		priv->reset_id = 0;
> > +		priv->rcdev.nr_resets = VERSAL_NR_RESETS;
> 
> This won't work. All your reset ids are greater than 95, and this driver is using
> the default of_xlate callback, so of_reset_simple_xlate will fail all reset
> control requests with -EINVAL.
Will create of_xlate callback that will simply return the reset line number
without any checks. We have underlying secure library which will validate
the reset line number.

Regards
Sai Krishna
> 
> regards
> Philipp

Re: [PATCH 1/2] dt-bindings: reset: Updated binding for Versal reset driver

[Rob Herring]

On Tue, Jul 14, 2020 at 11:59:08AM +0530, Sai Krishna Potthuri wrote:
> Added documentation and Versal reset indices to describe
> about Versal reset driver bindings.
> 
> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
> ---
>  .../bindings/reset/xlnx,zynqmp-reset.txt      |  11 +-
>  .../dt-bindings/reset/xlnx-versal-resets.h    | 105 ++++++++++++++++++
>  2 files changed, 112 insertions(+), 4 deletions(-)
>  create mode 100644 include/dt-bindings/reset/xlnx-versal-resets.h
> 
> diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
> index 27a45fe5ecf1..ed836868dbf1 100644
> --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
> +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
> @@ -1,7 +1,7 @@
>  --------------------------------------------------------------------------
> - =  Zynq UltraScale+ MPSoC reset driver binding =
> + =  Zynq UltraScale+ MPSoC and Versal reset driver binding =
>  --------------------------------------------------------------------------
> -The Zynq UltraScale+ MPSoC has several different resets.
> +The Zynq UltraScale+ MPSoC and Versal has several different resets.
>  
>  See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
>  about zynqmp resets.
> @@ -10,7 +10,8 @@ Please also refer to reset.txt in this directory for common reset
>  controller binding usage.
>  
>  Required Properties:
> -- compatible:	"xlnx,zynqmp-reset"
> +- compatible:	"xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
> +		"xlnx,versal-reset" for Versal platform
>  - #reset-cells:	Specifies the number of cells needed to encode reset
>  		line, should be 1
>  
> @@ -37,8 +38,10 @@ Device nodes that need access to reset lines should
>  specify them as a reset phandle in their corresponding node as
>  specified in reset.txt.
>  
> -For list of all valid reset indicies see
> +For list of all valid reset indices for Zynq UltraScale+ MPSoC see
>  <dt-bindings/reset/xlnx-zynqmp-resets.h>
> +For list of all valid reset indices for Versal see
> +<dt-bindings/reset/xlnx-versal-resets.h>
>  
>  Example:
>  
> diff --git a/include/dt-bindings/reset/xlnx-versal-resets.h b/include/dt-bindings/reset/xlnx-versal-resets.h
> new file mode 100644
> index 000000000000..895424e9b0e5
> --- /dev/null
> +++ b/include/dt-bindings/reset/xlnx-versal-resets.h
> @@ -0,0 +1,105 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + *  Copyright (C) 2020 Xilinx, Inc.
> + */
> +
> +#ifndef _DT_BINDINGS_VERSAL_RESETS_H
> +#define _DT_BINDINGS_VERSAL_RESETS_H
> +
> +#define VERSAL_RST_PMC_POR			(0xc30c001U)

Perhaps some explanation on the numbering as ZynqMP seems to be just an 
index.

> +#define VERSAL_RST_PMC				(0xc410002U)
> +#define VERSAL_RST_PS_POR			(0xc30c003U)
> +#define VERSAL_RST_PL_POR			(0xc30c004U)
> +#define VERSAL_RST_NOC_POR			(0xc30c005U)
> +#define VERSAL_RST_FPD_POR			(0xc30c006U)
> +#define VERSAL_RST_ACPU_0_POR			(0xc30c007U)
> +#define VERSAL_RST_ACPU_1_POR			(0xc30c008U)
> +#define VERSAL_RST_OCM2_POR			(0xc30c009U)
> +#define VERSAL_RST_PS_SRST			(0xc41000aU)
> +#define VERSAL_RST_PL_SRST			(0xc41000bU)
> +#define VERSAL_RST_NOC				(0xc41000cU)
> +#define VERSAL_RST_NPI				(0xc41000dU)
> +#define VERSAL_RST_SYS_RST_1			(0xc41000eU)
> +#define VERSAL_RST_SYS_RST_2			(0xc41000fU)
> +#define VERSAL_RST_SYS_RST_3			(0xc410010U)
> +#define VERSAL_RST_FPD				(0xc410011U)
> +#define VERSAL_RST_PL0				(0xc410012U)
> +#define VERSAL_RST_PL1				(0xc410013U)
> +#define VERSAL_RST_PL2				(0xc410014U)
> +#define VERSAL_RST_PL3				(0xc410015U)
> +#define VERSAL_RST_APU				(0xc410016U)
> +#define VERSAL_RST_ACPU_0			(0xc410017U)
> +#define VERSAL_RST_ACPU_1			(0xc410018U)
> +#define VERSAL_RST_ACPU_L2			(0xc410019U)
> +#define VERSAL_RST_ACPU_GIC			(0xc41001aU)
> +#define VERSAL_RST_RPU_ISLAND			(0xc41001bU)
> +#define VERSAL_RST_RPU_AMBA			(0xc41001cU)
> +#define VERSAL_RST_R5_0				(0xc41001dU)
> +#define VERSAL_RST_R5_1				(0xc41001eU)
> +#define VERSAL_RST_SYSMON_PMC_SEQ_RST		(0xc41001fU)
> +#define VERSAL_RST_SYSMON_PMC_CFG_RST		(0xc410020U)
> +#define VERSAL_RST_SYSMON_FPD_CFG_RST		(0xc410021U)
> +#define VERSAL_RST_SYSMON_FPD_SEQ_RST		(0xc410022U)
> +#define VERSAL_RST_SYSMON_LPD			(0xc410023U)
> +#define VERSAL_RST_PDMA_RST1			(0xc410024U)
> +#define VERSAL_RST_PDMA_RST0			(0xc410025U)
> +#define VERSAL_RST_ADMA				(0xc410026U)
> +#define VERSAL_RST_TIMESTAMP			(0xc410027U)
> +#define VERSAL_RST_OCM				(0xc410028U)
> +#define VERSAL_RST_OCM2_RST			(0xc410029U)
> +#define VERSAL_RST_IPI				(0xc41002aU)
> +#define VERSAL_RST_SBI				(0xc41002bU)
> +#define VERSAL_RST_LPD				(0xc41002cU)
> +#define VERSAL_RST_QSPI				(0xc10402dU)
> +#define VERSAL_RST_OSPI				(0xc10402eU)
> +#define VERSAL_RST_SDIO_0			(0xc10402fU)
> +#define VERSAL_RST_SDIO_1			(0xc104030U)
> +#define VERSAL_RST_I2C_PMC			(0xc104031U)
> +#define VERSAL_RST_GPIO_PMC			(0xc104032U)
> +#define VERSAL_RST_GEM_0			(0xc104033U)
> +#define VERSAL_RST_GEM_1			(0xc104034U)
> +#define VERSAL_RST_SPARE			(0xc104035U)
> +#define VERSAL_RST_USB_0			(0xc104036U)
> +#define VERSAL_RST_UART_0			(0xc104037U)
> +#define VERSAL_RST_UART_1			(0xc104038U)
> +#define VERSAL_RST_SPI_0			(0xc104039U)
> +#define VERSAL_RST_SPI_1			(0xc10403aU)
> +#define VERSAL_RST_CAN_FD_0			(0xc10403bU)
> +#define VERSAL_RST_CAN_FD_1			(0xc10403cU)
> +#define VERSAL_RST_I2C_0			(0xc10403dU)
> +#define VERSAL_RST_I2C_1			(0xc10403eU)
> +#define VERSAL_RST_GPIO_LPD			(0xc10403fU)
> +#define VERSAL_RST_TTC_0			(0xc104040U)
> +#define VERSAL_RST_TTC_1			(0xc104041U)
> +#define VERSAL_RST_TTC_2			(0xc104042U)
> +#define VERSAL_RST_TTC_3			(0xc104043U)
> +#define VERSAL_RST_SWDT_FPD			(0xc104044U)
> +#define VERSAL_RST_SWDT_LPD			(0xc104045U)
> +#define VERSAL_RST_USB				(0xc104046U)
> +#define VERSAL_RST_DPC				(0xc208047U)
> +#define VERSAL_RST_PMCDBG			(0xc208048U)
> +#define VERSAL_RST_DBG_TRACE			(0xc208049U)
> +#define VERSAL_RST_DBG_FPD			(0xc20804aU)
> +#define VERSAL_RST_DBG_TSTMP			(0xc20804bU)
> +#define VERSAL_RST_RPU0_DBG			(0xc20804cU)
> +#define VERSAL_RST_RPU1_DBG			(0xc20804dU)
> +#define VERSAL_RST_HSDP				(0xc20804eU)
> +#define VERSAL_RST_DBG_LPD			(0xc20804fU)
> +#define VERSAL_RST_CPM_POR			(0xc30c050U)
> +#define VERSAL_RST_CPM				(0xc410051U)
> +#define VERSAL_RST_CPMDBG			(0xc208052U)
> +#define VERSAL_RST_PCIE_CFG			(0xc410053U)
> +#define VERSAL_RST_PCIE_CORE0			(0xc410054U)
> +#define VERSAL_RST_PCIE_CORE1			(0xc410055U)
> +#define VERSAL_RST_PCIE_DMA			(0xc410056U)
> +#define VERSAL_RST_CMN				(0xc410057U)
> +#define VERSAL_RST_L2_0				(0xc410058U)
> +#define VERSAL_RST_L2_1				(0xc410059U)
> +#define VERSAL_RST_ADDR_REMAP			(0xc41005aU)
> +#define VERSAL_RST_CPI0				(0xc41005bU)
> +#define VERSAL_RST_CPI1				(0xc41005cU)
> +#define VERSAL_RST_XRAM				(0xc30c05dU)
> +#define VERSAL_RST_AIE_ARRAY			(0xc10405eU)
> +#define VERSAL_RST_AIE_SHIM			(0xc10405fU)
> +
> +#endif
> -- 
> 2.17.1
> 

RE: [PATCH 1/2] dt-bindings: reset: Updated binding for Versal reset driver

[Sai Krishna Potthuri]

Hi Rob,

Thanks for the review

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Tuesday, July 21, 2020 7:38 AM
> To: Sai Krishna Potthuri <lakshmis@xilinx.com>
> Cc: Philipp Zabel <p.zabel@pengutronix.de>; Michal Simek
> <michals@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; git
> <git@xilinx.com>; saikrishna12468@gmail.com
> Subject: Re: [PATCH 1/2] dt-bindings: reset: Updated binding for Versal reset
> driver
> 
> On Tue, Jul 14, 2020 at 11:59:08AM +0530, Sai Krishna Potthuri wrote:
> > Added documentation and Versal reset indices to describe about Versal
> > reset driver bindings.
> >
> > Signed-off-by: Sai Krishna Potthuri
> > <lakshmi.sai.krishna.potthuri@xilinx.com>
> > ---
> >  .../bindings/reset/xlnx,zynqmp-reset.txt      |  11 +-
> >  .../dt-bindings/reset/xlnx-versal-resets.h    | 105 ++++++++++++++++++
> >  2 files changed, 112 insertions(+), 4 deletions(-)  create mode
> > 100644 include/dt-bindings/reset/xlnx-versal-resets.h
> >
> > diff --git
> > a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
> > b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
> > index 27a45fe5ecf1..ed836868dbf1 100644
> > --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
> > +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
> > @@ -1,7 +1,7 @@
> >
> > ----------------------------------------------------------------------
> > ----
> > - =  Zynq UltraScale+ MPSoC reset driver binding =
> > + =  Zynq UltraScale+ MPSoC and Versal reset driver binding =
> >
> > ----------------------------------------------------------------------
> > ---- -The Zynq UltraScale+ MPSoC has several different resets.
> > +The Zynq UltraScale+ MPSoC and Versal has several different resets.
> >
> >  See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more
> > information  about zynqmp resets.
> > @@ -10,7 +10,8 @@ Please also refer to reset.txt in this directory for
> > common reset  controller binding usage.
> >
> >  Required Properties:
> > -- compatible:	"xlnx,zynqmp-reset"
> > +- compatible:	"xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC
> platform
> > +		"xlnx,versal-reset" for Versal platform
> >  - #reset-cells:	Specifies the number of cells needed to encode reset
> >  		line, should be 1
> >
> > @@ -37,8 +38,10 @@ Device nodes that need access to reset lines should
> > specify them as a reset phandle in their corresponding node as
> > specified in reset.txt.
> >
> > -For list of all valid reset indicies see
> > +For list of all valid reset indices for Zynq UltraScale+ MPSoC see
> >  <dt-bindings/reset/xlnx-zynqmp-resets.h>
> > +For list of all valid reset indices for Versal see
> > +<dt-bindings/reset/xlnx-versal-resets.h>
> >
> >  Example:
> >
> > diff --git a/include/dt-bindings/reset/xlnx-versal-resets.h
> > b/include/dt-bindings/reset/xlnx-versal-resets.h
> > new file mode 100644
> > index 000000000000..895424e9b0e5
> > --- /dev/null
> > +++ b/include/dt-bindings/reset/xlnx-versal-resets.h
> > @@ -0,0 +1,105 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + *  Copyright (C) 2020 Xilinx, Inc.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_VERSAL_RESETS_H
> > +#define _DT_BINDINGS_VERSAL_RESETS_H
> > +
> > +#define VERSAL_RST_PMC_POR			(0xc30c001U)
> 
> Perhaps some explanation on the numbering as ZynqMP seems to be just an
> index.
In versal, all ID's includes Class, SubClass, Type, Index information whereas class
refers to clock, reset, power etc., Underlying firmware in Versal have such
classification and expects the ID to be this way.
[13:0] - Index bits
[19:14] - Type bits
[25:20] - SubClass bits
[31:26] - Class bits
I will add this information in this file in v2.

Regards
Sai Krishna
> 
> > +#define VERSAL_RST_PMC				(0xc410002U)
> > +#define VERSAL_RST_PS_POR			(0xc30c003U)
> > +#define VERSAL_RST_PL_POR			(0xc30c004U)
> > +#define VERSAL_RST_NOC_POR			(0xc30c005U)
> > +#define VERSAL_RST_FPD_POR			(0xc30c006U)
> > +#define VERSAL_RST_ACPU_0_POR			(0xc30c007U)
> > +#define VERSAL_RST_ACPU_1_POR			(0xc30c008U)
> > +#define VERSAL_RST_OCM2_POR			(0xc30c009U)
> > +#define VERSAL_RST_PS_SRST			(0xc41000aU)
> > +#define VERSAL_RST_PL_SRST			(0xc41000bU)
> > +#define VERSAL_RST_NOC				(0xc41000cU)
> > +#define VERSAL_RST_NPI				(0xc41000dU)
> > +#define VERSAL_RST_SYS_RST_1			(0xc41000eU)
> > +#define VERSAL_RST_SYS_RST_2			(0xc41000fU)
> > +#define VERSAL_RST_SYS_RST_3			(0xc410010U)
> > +#define VERSAL_RST_FPD				(0xc410011U)
> > +#define VERSAL_RST_PL0				(0xc410012U)
> > +#define VERSAL_RST_PL1				(0xc410013U)
> > +#define VERSAL_RST_PL2				(0xc410014U)
> > +#define VERSAL_RST_PL3				(0xc410015U)
> > +#define VERSAL_RST_APU				(0xc410016U)
> > +#define VERSAL_RST_ACPU_0			(0xc410017U)
> > +#define VERSAL_RST_ACPU_1			(0xc410018U)
> > +#define VERSAL_RST_ACPU_L2			(0xc410019U)
> > +#define VERSAL_RST_ACPU_GIC			(0xc41001aU)
> > +#define VERSAL_RST_RPU_ISLAND			(0xc41001bU)
> > +#define VERSAL_RST_RPU_AMBA			(0xc41001cU)
> > +#define VERSAL_RST_R5_0				(0xc41001dU)
> > +#define VERSAL_RST_R5_1				(0xc41001eU)
> > +#define VERSAL_RST_SYSMON_PMC_SEQ_RST		(0xc41001fU)
> > +#define VERSAL_RST_SYSMON_PMC_CFG_RST		(0xc410020U)
> > +#define VERSAL_RST_SYSMON_FPD_CFG_RST		(0xc410021U)
> > +#define VERSAL_RST_SYSMON_FPD_SEQ_RST		(0xc410022U)
> > +#define VERSAL_RST_SYSMON_LPD			(0xc410023U)
> > +#define VERSAL_RST_PDMA_RST1			(0xc410024U)
> > +#define VERSAL_RST_PDMA_RST0			(0xc410025U)
> > +#define VERSAL_RST_ADMA				(0xc410026U)
> > +#define VERSAL_RST_TIMESTAMP			(0xc410027U)
> > +#define VERSAL_RST_OCM				(0xc410028U)
> > +#define VERSAL_RST_OCM2_RST			(0xc410029U)
> > +#define VERSAL_RST_IPI				(0xc41002aU)
> > +#define VERSAL_RST_SBI				(0xc41002bU)
> > +#define VERSAL_RST_LPD				(0xc41002cU)
> > +#define VERSAL_RST_QSPI				(0xc10402dU)
> > +#define VERSAL_RST_OSPI				(0xc10402eU)
> > +#define VERSAL_RST_SDIO_0			(0xc10402fU)
> > +#define VERSAL_RST_SDIO_1			(0xc104030U)
> > +#define VERSAL_RST_I2C_PMC			(0xc104031U)
> > +#define VERSAL_RST_GPIO_PMC			(0xc104032U)
> > +#define VERSAL_RST_GEM_0			(0xc104033U)
> > +#define VERSAL_RST_GEM_1			(0xc104034U)
> > +#define VERSAL_RST_SPARE			(0xc104035U)
> > +#define VERSAL_RST_USB_0			(0xc104036U)
> > +#define VERSAL_RST_UART_0			(0xc104037U)
> > +#define VERSAL_RST_UART_1			(0xc104038U)
> > +#define VERSAL_RST_SPI_0			(0xc104039U)
> > +#define VERSAL_RST_SPI_1			(0xc10403aU)
> > +#define VERSAL_RST_CAN_FD_0			(0xc10403bU)
> > +#define VERSAL_RST_CAN_FD_1			(0xc10403cU)
> > +#define VERSAL_RST_I2C_0			(0xc10403dU)
> > +#define VERSAL_RST_I2C_1			(0xc10403eU)
> > +#define VERSAL_RST_GPIO_LPD			(0xc10403fU)
> > +#define VERSAL_RST_TTC_0			(0xc104040U)
> > +#define VERSAL_RST_TTC_1			(0xc104041U)
> > +#define VERSAL_RST_TTC_2			(0xc104042U)
> > +#define VERSAL_RST_TTC_3			(0xc104043U)
> > +#define VERSAL_RST_SWDT_FPD			(0xc104044U)
> > +#define VERSAL_RST_SWDT_LPD			(0xc104045U)
> > +#define VERSAL_RST_USB				(0xc104046U)
> > +#define VERSAL_RST_DPC				(0xc208047U)
> > +#define VERSAL_RST_PMCDBG			(0xc208048U)
> > +#define VERSAL_RST_DBG_TRACE			(0xc208049U)
> > +#define VERSAL_RST_DBG_FPD			(0xc20804aU)
> > +#define VERSAL_RST_DBG_TSTMP			(0xc20804bU)
> > +#define VERSAL_RST_RPU0_DBG			(0xc20804cU)
> > +#define VERSAL_RST_RPU1_DBG			(0xc20804dU)
> > +#define VERSAL_RST_HSDP				(0xc20804eU)
> > +#define VERSAL_RST_DBG_LPD			(0xc20804fU)
> > +#define VERSAL_RST_CPM_POR			(0xc30c050U)
> > +#define VERSAL_RST_CPM				(0xc410051U)
> > +#define VERSAL_RST_CPMDBG			(0xc208052U)
> > +#define VERSAL_RST_PCIE_CFG			(0xc410053U)
> > +#define VERSAL_RST_PCIE_CORE0			(0xc410054U)
> > +#define VERSAL_RST_PCIE_CORE1			(0xc410055U)
> > +#define VERSAL_RST_PCIE_DMA			(0xc410056U)
> > +#define VERSAL_RST_CMN				(0xc410057U)
> > +#define VERSAL_RST_L2_0				(0xc410058U)
> > +#define VERSAL_RST_L2_1				(0xc410059U)
> > +#define VERSAL_RST_ADDR_REMAP			(0xc41005aU)
> > +#define VERSAL_RST_CPI0				(0xc41005bU)
> > +#define VERSAL_RST_CPI1				(0xc41005cU)
> > +#define VERSAL_RST_XRAM				(0xc30c05dU)
> > +#define VERSAL_RST_AIE_ARRAY			(0xc10405eU)
> > +#define VERSAL_RST_AIE_SHIM			(0xc10405fU)
> > +
> > +#endif
> > --
> > 2.17.1
> >