From: "David Woodhouse" <dwmw2@infradead.org>
To: "Tom Lendacky" <thomas.lendacky@amd.com>
Cc: "Thomas Gleixner" <tglx@linutronix.de>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
bp@alien8.de, dwmw@amazon.co.uk, gregkh@linux-foundation.org,
pjt@google.com, mingo@kernel.org, linux-kernel@vger.kernel.org,
hpa@zytor.com, tim.c.chen@linux.intel.com,
torvalds@linux-foundation.org, peterz@infradead.org,
dave.hansen@intel.com, linux-tip-commits@vger.kernel.org
Subject: Re: [tip:x86/pti] x86/cpu/AMD: Use LFENCE_RDTSC instead of MFENCE_RDTSC
Date: Mon, 8 Jan 2018 15:02:25 -0000 [thread overview]
Message-ID: <b2009674ce338fd1ad0aaaa55d176a9d.squirrel@twosheds.infradead.org> (raw)
In-Reply-To: <4d9a1f0d-a401-3f0f-9ee2-dd42f4b4716a@amd.com>
> Ok, I can add the read-back check before setting the feature flag(s).
>
> But... what about the case where the guest is a different family than
> hypervisor? If we're on, say, a Fam15h hypervisor but the guest is started
> as a Fam0fh guest where the MSR doesn't exist and LFENCE is supposed to be
> serialized? I'll have to do a rdmsr_safe() and only set the flag(s) if I
> can successfully read the MSR back and validate the bit.
At some point, if the hypervisor is lying to you about what the CPU is,
and you can't check empirically, you have to admit defeat :)
--
dwmw2
next prev parent reply other threads:[~2018-01-08 15:03 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-05 16:07 [PATCH v1 0/3] x86/cpu/AMD: Make LFENCE a serializing instruction on AMD Tom Lendacky
2018-01-05 16:07 ` [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction Tom Lendacky
2018-01-05 16:35 ` Brian Gerst
2018-01-05 16:36 ` Tom Lendacky
2018-01-06 21:05 ` [tip:x86/pti] " tip-bot for Tom Lendacky
2018-01-05 16:07 ` [PATCH v1 2/3] x86/cpu/AMD: Use LFENCE_RDTSC instead of MFENCE_RDTSC Tom Lendacky
2018-01-06 21:06 ` [tip:x86/pti] " tip-bot for Tom Lendacky
2018-01-08 10:08 ` Thomas Gleixner
2018-01-08 10:23 ` Woodhouse, David
2018-01-08 10:25 ` Thomas Gleixner
2018-01-08 10:40 ` Andrew Cooper
2018-01-08 11:10 ` Thomas Gleixner
2018-01-08 14:47 ` Tom Lendacky
2018-01-08 14:54 ` Andrew Cooper
2018-01-08 16:48 ` Dr. David Alan Gilbert
2018-01-08 17:01 ` Paolo Bonzini
2018-01-08 17:39 ` Tom Lendacky
2018-01-08 17:42 ` Paolo Bonzini
2018-01-17 17:21 ` Tom Lendacky
2018-01-17 17:53 ` Paolo Bonzini
2018-01-08 15:02 ` David Woodhouse [this message]
2018-01-08 15:15 ` Thomas Gleixner
2018-01-08 17:31 ` Tom Lendacky
2018-01-08 20:57 ` Thomas Gleixner
2018-01-05 16:08 ` [PATCH v1 3/3] x86/msr: Remove now unused definition of MFENCE_RDTSC feature Tom Lendacky
2018-01-06 21:06 ` [tip:x86/pti] " tip-bot for Tom Lendacky
2018-01-05 16:56 ` [PATCH v1 0/3] x86/cpu/AMD: Make LFENCE a serializing instruction on AMD Borislav Petkov
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