From: tip-bot for Tom Lendacky <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: thomas.lendacky@amd.com, pjt@google.com, mingo@kernel.org,
bp@alien8.de, torvalds@linux-foundation.org,
peterz@infradead.org, gregkh@linux-foundation.org,
linux-kernel@vger.kernel.org, hpa@zytor.com,
dave.hansen@intel.com, dwmw@amazon.co.uk,
tim.c.chen@linux.intel.com, tglx@linutronix.de
Subject: [tip:x86/pti] x86/cpu/AMD: Make LFENCE a serializing instruction
Date: Sat, 6 Jan 2018 13:05:35 -0800 [thread overview]
Message-ID: <tip-0592b0bce1694957fed178fc52f4b11576714b07@git.kernel.org> (raw)
In-Reply-To: <20180105160746.23786.11850.stgit@tlendack-t1.amdoffice.net>
Commit-ID: 0592b0bce1694957fed178fc52f4b11576714b07
Gitweb: https://git.kernel.org/tip/0592b0bce1694957fed178fc52f4b11576714b07
Author: Tom Lendacky <thomas.lendacky@amd.com>
AuthorDate: Fri, 5 Jan 2018 10:07:46 -0600
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Sat, 6 Jan 2018 21:57:40 +0100
x86/cpu/AMD: Make LFENCE a serializing instruction
To aid in speculation control, make LFENCE a serializing instruction.
This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG). Some families
that support LFENCE do not have this MSR. For these families, the LFENCE
instruction is already serializing.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@alien8.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Tim Chen <tim.c.chen@linux.intel.com>
Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Cc: Paul Turner <pjt@google.com>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20180105160746.23786.11850.stgit@tlendack-t1.amdoffice.net
---
arch/x86/include/asm/msr-index.h | 2 ++
arch/x86/kernel/cpu/amd.c | 9 +++++++++
2 files changed, 11 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index ab02261..1e7d710 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -352,6 +352,8 @@
#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
#define FAM10H_MMIO_CONF_BASE_SHIFT 20
#define MSR_FAM10H_NODE_ID 0xc001100c
+#define MSR_F10H_DECFG 0xc0011029
+#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
/* K8 MSRs */
#define MSR_K8_TOP_MEM1 0xc001001a
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index bcb75dc..fbd439e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -829,6 +829,15 @@ static void init_amd(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_K8);
if (cpu_has(c, X86_FEATURE_XMM2)) {
+ /*
+ * Use LFENCE for execution serialization. On families which
+ * don't have that MSR, LFENCE is already serializing.
+ * msr_set_bit() uses the safe accessors, too, even if the MSR
+ * is not present.
+ */
+ msr_set_bit(MSR_F10H_DECFG,
+ MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
+
/* MFENCE stops RDTSC speculation */
set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
}
next prev parent reply other threads:[~2018-01-06 21:11 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-05 16:07 [PATCH v1 0/3] x86/cpu/AMD: Make LFENCE a serializing instruction on AMD Tom Lendacky
2018-01-05 16:07 ` [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction Tom Lendacky
2018-01-05 16:35 ` Brian Gerst
2018-01-05 16:36 ` Tom Lendacky
2018-01-06 21:05 ` tip-bot for Tom Lendacky [this message]
2018-01-05 16:07 ` [PATCH v1 2/3] x86/cpu/AMD: Use LFENCE_RDTSC instead of MFENCE_RDTSC Tom Lendacky
2018-01-06 21:06 ` [tip:x86/pti] " tip-bot for Tom Lendacky
2018-01-08 10:08 ` Thomas Gleixner
2018-01-08 10:23 ` Woodhouse, David
2018-01-08 10:25 ` Thomas Gleixner
2018-01-08 10:40 ` Andrew Cooper
2018-01-08 11:10 ` Thomas Gleixner
2018-01-08 14:47 ` Tom Lendacky
2018-01-08 14:54 ` Andrew Cooper
2018-01-08 16:48 ` Dr. David Alan Gilbert
2018-01-08 17:01 ` Paolo Bonzini
2018-01-08 17:39 ` Tom Lendacky
2018-01-08 17:42 ` Paolo Bonzini
2018-01-17 17:21 ` Tom Lendacky
2018-01-17 17:53 ` Paolo Bonzini
2018-01-08 15:02 ` David Woodhouse
2018-01-08 15:15 ` Thomas Gleixner
2018-01-08 17:31 ` Tom Lendacky
2018-01-08 20:57 ` Thomas Gleixner
2018-01-05 16:08 ` [PATCH v1 3/3] x86/msr: Remove now unused definition of MFENCE_RDTSC feature Tom Lendacky
2018-01-06 21:06 ` [tip:x86/pti] " tip-bot for Tom Lendacky
2018-01-05 16:56 ` [PATCH v1 0/3] x86/cpu/AMD: Make LFENCE a serializing instruction on AMD Borislav Petkov
2018-01-08 22:09 [PATCH v2 1/2] x86/cpu/AMD: Make LFENCE a serializing instruction Tom Lendacky
2018-01-09 0:48 ` [tip:x86/pti] " tip-bot for Tom Lendacky
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