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From: "Zhang, Rui" <rui.zhang@intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: "mingo@redhat.com" <mingo@redhat.com>,
	"acme@kernel.org" <acme@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"alexander.shishkin@linux.intel.com" 
	<alexander.shishkin@linux.intel.com>,
	"jolsa@redhat.com" <jolsa@redhat.com>,
	"namhyung@kernel.org" <namhyung@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"x86@kernel.org" <x86@kernel.org>,
	"kan.liang@linux.intel.com" <kan.liang@linux.intel.com>,
	"ak@linux.intel.com" <ak@linux.intel.com>
Subject: RE: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection
Date: Sun, 17 Jan 2021 14:44:04 +0000	[thread overview]
Message-ID: <b27f97d12329452bb95c1345a0bbdd3f@intel.com> (raw)
In-Reply-To: <YALgm2b0YNkO7Qtd@hirez.programming.kicks-ass.net>



> -----Original Message-----
> From: Peter Zijlstra <peterz@infradead.org>
> Sent: Saturday, January 16, 2021 8:48 PM
> To: Zhang, Rui <rui.zhang@intel.com>
> Cc: mingo@redhat.com; acme@kernel.org; mark.rutland@arm.com;
> alexander.shishkin@linux.intel.com; jolsa@redhat.com;
> namhyung@kernel.org; linux-kernel@vger.kernel.org; x86@kernel.org;
> kan.liang@linux.intel.com; ak@linux.intel.com
> Subject: Re: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection
> Importance: High
> 
> On Sat, Jan 16, 2021 at 08:19:35AM +0000, Zhang, Rui wrote:
> >
> >
> > > -----Original Message-----
> > > From: Peter Zijlstra <peterz@infradead.org>
> > > Sent: Saturday, January 16, 2021 4:03 AM
> > > To: Zhang, Rui <rui.zhang@intel.com>
> > > Cc: mingo@redhat.com; acme@kernel.org; mark.rutland@arm.com;
> > > alexander.shishkin@linux.intel.com; jolsa@redhat.com;
> > > namhyung@kernel.org; linux-kernel@vger.kernel.org; x86@kernel.org;
> > > kan.liang@linux.intel.com; ak@linux.intel.com
> > > Subject: Re: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection
> > > Importance: High
> > >
> > > On Fri, Jan 15, 2021 at 05:22:07PM +0800, Zhang Rui wrote:
> > > > In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent
> > > > the energy counter, and the higher 32bits are reserved.
> > > >
> > > > Add the MSR mask for these MSRs to fix a problem that the RAPL PMU
> > > > events are added erroneously when higher 32bits contain non-zero
> value.
> > >
> > > Why would these high bits be non-zero?
> >
> > On SPR platform, the high bits of Psys energy counter are reused for other
> purpose.
> > High bits for other RAPL domains energy counters still return 0.
> >
> > I didn't mention this because I thought this patch should be okay as a
> generic fix.
> 
> But it doesn't fix anything.. there's not anything broken, except on that daft
> SPR thing.

Well, yes.
Before SPR, this is just a potential issue. But things on SPR suggests that this potential issue may become a real one.
So are you suggesting me to also include the SPR information as the justification of this patch?

Thanks,
rui

  reply	other threads:[~2021-01-17 14:45 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-15  9:22 [PATCH 1/3] perf/x86/rapl: Add msr mask support Zhang Rui
2021-01-15  9:22 ` [PATCH 2/3] perf/x86/rapl: Fix energy counter detection Zhang Rui
2021-01-15 20:03   ` Peter Zijlstra
2021-01-16  8:19     ` Zhang, Rui
2021-01-16 12:48       ` Peter Zijlstra
2021-01-17 14:44         ` Zhang, Rui [this message]
2021-02-03 14:21           ` Peter Zijlstra
2021-01-15  9:22 ` [PATCH 3/3] perf/x86/rapl: Fix psys-energy event on Intel SPR platform Zhang Rui
2021-01-16 12:50   ` Peter Zijlstra
2021-01-17 14:33     ` Zhang, Rui
2021-01-25  6:11       ` Zhang, Rui
2021-02-03 14:17         ` Zhang, Rui
2021-02-03 14:47         ` Peter Zijlstra
2021-02-04 16:04           ` Zhang Rui

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