[PATCH v10 00/11] Add multiport support for DWC3 controllers

[PATCH v10 00/11] Add multiport support for DWC3 controllers

[Krishna Kurapati]

Currently the DWC3 driver supports only single port controller which
requires at most two PHYs ie HS and SS PHYs. There are SoCs that has
DWC3 controller with multiple ports that can operate in host mode.
Some of the port supports both SS+HS and other port supports only HS
mode.

This change primarily refactors the Phy logic in core driver to allow
multiport support with Generic Phy's.

Changes have been tested on  QCOM SoC SA8295P which has 4 ports (2
are HS+SS capable and 2 are HS only capable).

Changes in v10:
Refactored phy init/exit/power-on/off functions in dwc3 core
Refactored dwc3-qcom irq registration and handling
Implemented wakeup for multiport irq's
Moved few macros from xhci.h to xhci-ext-caps.h
Fixed nits pointed out in v9
Fixed Co-developed by and SOB tags in patches 5 and 11

Changes in v9:
Added IRQ support for DP/DM/SS MP Irq's of SC8280
Refactored code to read port count by accessing xhci registers

Changes in v8:
Reorganised code in patch-5
Fixed nitpicks in code according to comments received on v7
Fixed indentation in DT patches
Added drive strength for pinctrl nodes in SA8295 DT

Changes in v7:
Added power event irq's for Multiport controller.
Udpated commit text for patch-9 (adding DT changes for enabling first
port of multiport controller on sa8540-ride).
Fixed check-patch warnings for driver code.
Fixed DT binding errors for changes in snps,dwc3.yaml
Reabsed code on top of usb-next

Changes in v6:
Updated comments in code after.
Updated variables names appropriately as per review comments.
Updated commit text in patch-2 and added additional info as per review
comments.
The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected
it in this version.

Changes in v5:
Added DT support for first port of Teritiary USB controller on SA8540-Ride
Added support for reading port info from XHCI Extended Params registers.

Changes in RFC v4:
Added DT support for SA8295p.

Changes in RFC v3:
Incase any PHY init fails, then clear/exit the PHYs that
are already initialized.

Changes in RFC v2:
Changed dwc3_count_phys to return the number of PHY Phandles in the node.
This will be used now in dwc3_extract_num_phys to increment num_usb2_phy 
and num_usb3_phy.

Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its
structure such that the first half is for HS-PHY and second half is for
SS-PHY.

In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is
present, pass proper SS_IDX else pass -1.

Tests done on v10:
Enumeration:
/ # lsusb
Bus 003 Device 001: ID 1d6b:0002
Bus 001 Device 001: ID 1d6b:0002
Bus 001 Device 002: ID 045e:0040
Bus 004 Device 001: ID 1d6b:0003
Bus 002 Device 001: ID 1d6b:0003
Bus 001 Device 003: ID 17ef:60d1

Interrupt registration:
/ # cat /proc/interrupts  | grep dwc
184:  0 0 0 0 0 0 0 0       PDC 127 Level     qcom_dwc3 DP_HS1
185:  0 0 0 0 0 0 0 0       PDC 126 Level     qcom_dwc3 DM_HS1
186:  0 0 0 0 0 0 0 0       PDC  16 Level     qcom_dwc3 SS1
187:  0 0 0 0 0 0 0 0       PDC 129 Level     qcom_dwc3 DP_HS2
188:  0 0 0 0 0 0 0 0       PDC 128 Level     qcom_dwc3 DM_HS2
189:  0 0 0 0 0 0 0 0       PDC  17 Level     qcom_dwc3 SS2
190:  0 0 0 0 0 0 0 0       PDC 131 Level     qcom_dwc3 DP_HS3
191:  0 0 0 0 0 0 0 0       PDC 130 Level     qcom_dwc3 DM_HS3
192:  0 0 0 0 0 0 0 0       PDC 133 Level     qcom_dwc3 DP_HS4
193:  0 0 0 0 0 0 0 0       PDC 132 Level     qcom_dwc3 DM_HS4
195:  0 0 0 0 0 0 0 0       PDC  14 Level     qcom_dwc3 DP_HS
196:  0 0 0 0 0 0 0 0       PDC  15 Level     qcom_dwc3 DM_HS
197:  0 0 0 0 0 0 0 0       PDC 138 Level     qcom_dwc3 SS
198: 32 0 0 0 0 0 0 0     GICv3 835 Leel     dwc3
199:  0 0 0 0 0 0 0 0       PDC  12 Level     qcom_dwc3 DP_HS
200:  0 0 0 0 0 0 0 0       PDC  13 Level     qcom_dwc3 DM_HS
201:  0 0 0 0 0 0 0 0       PDC 136 Level     qcom_dwc3 SS

Interrupt connfiguration during suspend entry and suspend exit upon device
connect. Speed here in the following log indicates enum usb_device_speed
in dwc3-qcom.

[  151.625326] K: dwc3_qcom_enable_interrupts index: 0 speed: 0
[  151.680985] K: dwc3_qcom_enable_interrupts index: 0 speed: 2
[  151.686841] K: dwc3_qcom_enable_interrupts index: 1 speed: 2
[  151.692665] K: dwc3_qcom_enable_interrupts index: 2 speed: 0
[  151.692678] K: dwc3_qcom_enable_interrupts index: 3 speed: 0

[  151.724912] K: dwc3_qcom_disable_interrupts index: 0 speed: 2
[  151.730832] K: dwc3_qcom_disable_interrupts index: 1 speed: 2
[  151.736740] K: dwc3_qcom_disable_interrupts index: 2 speed: 0
[  151.742646] K: dwc3_qcom_disable_interrupts index: 3 speed: 0
[  152.010699] K: dwc3_qcom_disable_interrupts index: 0 speed: 0

[  152.107836] OOM killer enabled.
[  152.111070] Restarting tasks ... done.
[  152.115742] random: crng reseeded on system resumption
[  152.121298] PM: suspend exit
/ # [  152.240015] usb 1-3: new low-speed USB device number 8 using xhci-hcd

On SC7280 CRD Herobrine variant, enumeration and wakeup was tested and it
works fine:

Enumeration:
localhost ~ # lsusb
Bus 002 Device 004: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN
Bus 002 Device 003: ID 05e3:0626 Genesys Logic, Inc. USB3.1 Hub
Bus 002 Device 002: ID 0bda:0411 Realtek Semiconductor Corp. 4-Port USB 3.1 Hub
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 024: ID 046d:c06a Logitech, Inc. USB Optical Mouse
Bus 001 Device 007: ID 05e3:0610 Genesys Logic, Inc. 4-port hub
Bus 001 Device 002: ID 0bda:5411 Realtek Semiconductor Corp. 4-Port USB 2.1 Hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

localhost ~ # dmesg | grep hub
[    3.713331] hub 1-0:1.0: USB hub found
[    3.717222] hub 1-0:1.0: 1 port detected
[    3.764330] hub 2-0:1.0: USB hub found
[    3.768216] hub 2-0:1.0: 1 port detected
[    4.159720] hub 1-1:1.0: USB hub found
[    4.165010] hub 1-1:1.0: 4 ports detected
[    4.322363] hub 2-1:1.0: USB hub found
[    4.327220] hub 2-1:1.0: 4 ports detected
[    5.504227] hub 2-1.4:1.0: USB hub found
[    5.508724] hub 2-1.4:1.0: 4 ports detected
[    7.263756] hub 1-1.4:1.0: USB hub found
[    7.268273] hub 1-1.4:1.0: 4 ports detected
[   10.030906] hub 1-1.4:1.0: USB hub found
[   10.035352] hub 1-1.4:1.0: 4 ports detected


Interrupt registration on SC7280-CRD:
localhost ~ # cat /proc/interrupts   | grep dwc
 82:   0   0   0    0    0    0    0    0     GICv3 163 Level     qcom_dwc3 HS
 211:  0   0   0    0    0    0    0    0       PDC  14 Level     qcom_dwc3 DP_HS
 212:  0   0   0    0    0    0    0    0       PDC  15 Level     qcom_dwc3 DM_HS
 213:  0   0   0    0    0    0    0    0       PDC  17 Level     qcom_dwc3 SS


Wakeup from system suspend upon mouse click:
 [ 1159.589739] K: dwc3_qcom_enable_interrupts port: 0 speed: 3
 [ 1160.025300] K: qcom_dwc3_resume_irq irq: 211
 [ 1160.149660] K: dwc3_qcom_disable_interrupts port: 0 speed: 3
 [ 1161.649610] Resume caused by IRQ 211, qcom_dwc3 DP_HS

Also DT Binding checks were done on both modified yaml files.

Links to previous versions:
Link to v9: https://lore.kernel.org/all/20230621043628.21485-1-quic_kriskura@quicinc.com/
Link to v8: https://lore.kernel.org/all/20230514054917.21318-1-quic_kriskura@quicinc.com/
Link to v7: https://lore.kernel.org/all/20230501143445.3851-1-quic_kriskura@quicinc.com/
Link to v6: https://lore.kernel.org/all/20230405125759.4201-1-quic_kriskura@quicinc.com/
Link to v5: https://lore.kernel.org/all/20230310163420.7582-1-quic_kriskura@quicinc.com/
Link to RFC v4: https://lore.kernel.org/all/20230115114146.12628-1-quic_kriskura@quicinc.com/
Link to RFC v3: https://lore.kernel.org/all/1654709787-23686-1-git-send-email-quic_harshq@quicinc.com/#r
Link to RFC v2: https://lore.kernel.org/all/1653560029-6937-1-git-send-email-quic_harshq@quicinc.com/#r

Andrew Halaney (1):
  arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
    controller

Harsh Agarwal (1):
  usb: dwc3: core: Refactor PHY logic to support Multiport Controller

Krishna Kurapati (9):
  dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport
  dt-bindings: usb: Add bindings for multiport properties on DWC3
    controller
  usb: dwc3: core: Access XHCI address space temporarily to read port
    info
  usb: dwc3: core: Skip setting event buffers for host only controllers
  usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver
  usb: dwc3: qcom: Enable wakeup for applicable ports of multiport
  usb: dwc3: qcom: Add multiport suspend/resume support for wrapper
  arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
  arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
    ports

 .../devicetree/bindings/usb/qcom,dwc3.yaml    |  29 ++
 .../devicetree/bindings/usb/snps,dwc3.yaml    |  13 +-
 arch/arm64/boot/dts/qcom/sa8295p-adp.dts      |  53 +++
 arch/arm64/boot/dts/qcom/sa8540p-ride.dts     |  22 ++
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi        |  77 ++++
 drivers/usb/dwc3/core.c                       | 326 ++++++++++++----
 drivers/usb/dwc3/core.h                       |  16 +-
 drivers/usb/dwc3/drd.c                        |  15 +-
 drivers/usb/dwc3/dwc3-qcom.c                  | 358 ++++++++++++------
 drivers/usb/host/xhci-ext-caps.h              |   5 +
 drivers/usb/host/xhci.h                       |   3 -
 11 files changed, 714 insertions(+), 203 deletions(-)

-- 
2.40.0

[PATCH v10 01/11] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport

[Krishna Kurapati]

Add the compatible string for SC8280 Multiport USB controller from
Qualcomm.

There are 4 power event irq interrupts supported by this controller
(one for each port of multiport). Added all the 4 as non-optional
interrupts for SC8280XP-MP

Also each port of multiport has one DP and oen DM IRQ. Add all DP/DM
IRQ's related to 4 ports of SC8280XP Teritiary controller.

Also added ss phy irq for both SS Ports.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 .../devicetree/bindings/usb/qcom,dwc3.yaml    | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index ae24dac78d9a..80a0a7be18e3 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -28,6 +28,7 @@ properties:
           - qcom,sc7180-dwc3
           - qcom,sc7280-dwc3
           - qcom,sc8280xp-dwc3
+          - qcom,sc8280xp-dwc3-mp
           - qcom,sdm660-dwc3
           - qcom,sdm670-dwc3
           - qcom,sdm845-dwc3
@@ -265,6 +266,7 @@ allOf:
           contains:
             enum:
               - qcom,sc8280xp-dwc3
+              - qcom,sc8280xp-dwc3-mp
     then:
       properties:
         clocks:
@@ -477,6 +479,33 @@ allOf:
             - const: dm_hs_phy_irq
             - const: ss_phy_irq
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sc8280xp-dwc3-mp
+    then:
+      properties:
+        interrupts:
+          maxItems: 14
+        interrupt-names:
+          items:
+            - const: pwr_event_1
+            - const: pwr_event_2
+            - const: pwr_event_3
+            - const: pwr_event_4
+            - const: dp_hs_phy_1
+            - const: dm_hs_phy_1
+            - const: dp_hs_phy_2
+            - const: dm_hs_phy_2
+            - const: dp_hs_phy_3
+            - const: dm_hs_phy_3
+            - const: dp_hs_phy_4
+            - const: dm_hs_phy_4
+            - const: ss_phy_1
+            - const: ss_phy_2
+
 additionalProperties: false
 
 examples:
-- 
2.40.0

[PATCH v10 02/11] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller

[Krishna Kurapati]

Add bindings to indicate properties required to support multiport
on Synopsys DWC3 controller.

Suggested-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/usb/snps,dwc3.yaml          | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
index a696f23730d3..5bc941355b43 100644
--- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
@@ -85,15 +85,16 @@ properties:
 
   phys:
     minItems: 1
-    maxItems: 2
+    maxItems: 8
 
   phy-names:
     minItems: 1
-    maxItems: 2
-    items:
-      enum:
-        - usb2-phy
-        - usb3-phy
+    maxItems: 8
+    oneOf:
+      - items:
+          enum: [ usb2-phy, usb3-phy ]
+      - items:
+          pattern: "^usb[23]-port[0-3]$"
 
   power-domains:
     description:
-- 
2.40.0

[PATCH v10 03/11] usb: dwc3: core: Access XHCI address space temporarily to read port info

[Krishna Kurapati]

Currently host-only capable DWC3 controllers support Multiport.
Temporarily map XHCI address space for host-only controllers and parse
XHCI Extended Capabilities registers to read number of usb2 ports and
usb3 ports present on multiport controller. Each USB Port is at least HS
capable.

Since the extcaps header is only being used, move port_count related
macros and structure from xhci.h to xhci-ext-caps.h.

The port info for usb2 and usb3 phy are identified as num_usb2_ports
and num_usb3_ports. The intention is as follows:

Wherever we need to perform phy operations like:

LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
{
	phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
	phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
}

If number of usb2 ports is 3, loop can go from index 0-2 for
usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
if the first 2 ports are SS capable or some other ports like (2 and 3)
are SS capable. So instead, num_usb2_ports is used to loop around all
phy's (both hs and ss) for performing phy operations. If any
usb3_generic_phy turns out to be NULL, phy operation just bails out.

num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
phy's as we need to know how many SS capable ports are there for this.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 drivers/usb/dwc3/core.c          | 61 ++++++++++++++++++++++++++++++++
 drivers/usb/dwc3/core.h          |  5 +++
 drivers/usb/host/xhci-ext-caps.h | 27 ++++++++++++++
 drivers/usb/host/xhci.h          | 27 --------------
 4 files changed, 93 insertions(+), 27 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index f6689b731718..edc79ce70588 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -39,6 +39,7 @@
 #include "io.h"
 
 #include "debug.h"
+#include "../host/xhci-ext-caps.h"
 
 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY	5000 /* ms */
 
@@ -1767,6 +1768,51 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
 	return 0;
 }
 
+static int dwc3_read_port_info(struct dwc3 *dwc)
+{
+	void __iomem *base;
+	u8 major_revision;
+	u32 offset = 0;
+	u32 val;
+
+	/*
+	 * Remap xHCI address space to access XHCI ext cap regs,
+	 * since it is needed to get port info.
+	 */
+	base = ioremap(dwc->xhci_resources[0].start,
+				resource_size(&dwc->xhci_resources[0]));
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	do {
+		offset = xhci_find_next_ext_cap(base, offset,
+				XHCI_EXT_CAPS_PROTOCOL);
+		if (!offset)
+			break;
+
+		val = readl(base + offset);
+		major_revision = XHCI_EXT_PORT_MAJOR(val);
+
+		val = readl(base + offset + 0x08);
+		if (major_revision == 0x03) {
+			dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
+		} else if (major_revision <= 0x02) {
+			dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
+		} else {
+			dev_err(dwc->dev,
+				"Unrecognized port major revision %d\n",
+							major_revision);
+		}
+	} while (1);
+
+	dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
+			dwc->num_usb2_ports, dwc->num_usb3_ports);
+
+	iounmap(base);
+
+	return 0;
+}
+
 static int dwc3_probe(struct platform_device *pdev)
 {
 	struct device		*dev = &pdev->dev;
@@ -1774,6 +1820,7 @@ static int dwc3_probe(struct platform_device *pdev)
 	void __iomem		*regs;
 	struct dwc3		*dwc;
 	int			ret;
+	unsigned int		hw_mode;
 
 	dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
 	if (!dwc)
@@ -1854,6 +1901,20 @@ static int dwc3_probe(struct platform_device *pdev)
 			goto err_disable_clks;
 	}
 
+	/*
+	 * Currently only DWC3 controllers that are host-only capable
+	 * support Multiport.
+	 */
+	hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+	if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
+		ret = dwc3_read_port_info(dwc);
+		if (ret)
+			goto err_disable_clks;
+	} else {
+		dwc->num_usb2_ports = 1;
+		dwc->num_usb3_ports = 1;
+	}
+
 	spin_lock_init(&dwc->lock);
 	mutex_init(&dwc->mutex);
 
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 8b1295e4dcdd..0840808e8a40 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1029,6 +1029,8 @@ struct dwc3_scratchpad_array {
  * @usb3_phy: pointer to USB3 PHY
  * @usb2_generic_phy: pointer to USB2 PHY
  * @usb3_generic_phy: pointer to USB3 PHY
+ * @num_usb2_ports: number of USB2 ports
+ * @num_usb3_ports: number of USB3 ports
  * @phys_ready: flag to indicate that PHYs are ready
  * @ulpi: pointer to ulpi interface
  * @ulpi_ready: flag to indicate that ULPI is initialized
@@ -1168,6 +1170,9 @@ struct dwc3 {
 	struct phy		*usb2_generic_phy;
 	struct phy		*usb3_generic_phy;
 
+	u8			num_usb2_ports;
+	u8			num_usb3_ports;
+
 	bool			phys_ready;
 
 	struct ulpi		*ulpi;
diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
index e8af0a125f84..96eb36a58738 100644
--- a/drivers/usb/host/xhci-ext-caps.h
+++ b/drivers/usb/host/xhci-ext-caps.h
@@ -79,6 +79,33 @@
 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
 #define XHCI_STS_CNR		(1 << 11)
 
+/**
+ * struct xhci_protocol_caps
+ * @revision:		major revision, minor revision, capability ID,
+ *			and next capability pointer.
+ * @name_string:	Four ASCII characters to say which spec this xHC
+ *			follows, typically "USB ".
+ * @port_info:		Port offset, count, and protocol-defined information.
+ */
+struct xhci_protocol_caps {
+	u32	revision;
+	u32	name_string;
+	u32	port_info;
+};
+
+#define	XHCI_EXT_PORT_MAJOR(x)	(((x) >> 24) & 0xff)
+#define	XHCI_EXT_PORT_MINOR(x)	(((x) >> 16) & 0xff)
+#define	XHCI_EXT_PORT_PSIC(x)	(((x) >> 28) & 0x0f)
+#define	XHCI_EXT_PORT_OFF(x)	((x) & 0xff)
+#define	XHCI_EXT_PORT_COUNT(x)	(((x) >> 8) & 0xff)
+
+#define	XHCI_EXT_PORT_PSIV(x)	(((x) >> 0) & 0x0f)
+#define	XHCI_EXT_PORT_PSIE(x)	(((x) >> 4) & 0x03)
+#define	XHCI_EXT_PORT_PLT(x)	(((x) >> 6) & 0x03)
+#define	XHCI_EXT_PORT_PFD(x)	(((x) >> 8) & 0x01)
+#define	XHCI_EXT_PORT_LP(x)	(((x) >> 14) & 0x03)
+#define	XHCI_EXT_PORT_PSIM(x)	(((x) >> 16) & 0xffff)
+
 #include <linux/io.h>
 
 /**
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 7e282b4522c0..77016338bee1 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -558,33 +558,6 @@ struct xhci_doorbell_array {
 #define DB_VALUE(ep, stream)	((((ep) + 1) & 0xff) | ((stream) << 16))
 #define DB_VALUE_HOST		0x00000000
 
-/**
- * struct xhci_protocol_caps
- * @revision:		major revision, minor revision, capability ID,
- *			and next capability pointer.
- * @name_string:	Four ASCII characters to say which spec this xHC
- *			follows, typically "USB ".
- * @port_info:		Port offset, count, and protocol-defined information.
- */
-struct xhci_protocol_caps {
-	u32	revision;
-	u32	name_string;
-	u32	port_info;
-};
-
-#define	XHCI_EXT_PORT_MAJOR(x)	(((x) >> 24) & 0xff)
-#define	XHCI_EXT_PORT_MINOR(x)	(((x) >> 16) & 0xff)
-#define	XHCI_EXT_PORT_PSIC(x)	(((x) >> 28) & 0x0f)
-#define	XHCI_EXT_PORT_OFF(x)	((x) & 0xff)
-#define	XHCI_EXT_PORT_COUNT(x)	(((x) >> 8) & 0xff)
-
-#define	XHCI_EXT_PORT_PSIV(x)	(((x) >> 0) & 0x0f)
-#define	XHCI_EXT_PORT_PSIE(x)	(((x) >> 4) & 0x03)
-#define	XHCI_EXT_PORT_PLT(x)	(((x) >> 6) & 0x03)
-#define	XHCI_EXT_PORT_PFD(x)	(((x) >> 8) & 0x01)
-#define	XHCI_EXT_PORT_LP(x)	(((x) >> 14) & 0x03)
-#define	XHCI_EXT_PORT_PSIM(x)	(((x) >> 16) & 0xffff)
-
 #define PLT_MASK        (0x03 << 6)
 #define PLT_SYM         (0x00 << 6)
 #define PLT_ASYM_RX     (0x02 << 6)
-- 
2.40.0

[PATCH v10 04/11] usb: dwc3: core: Skip setting event buffers for host only controllers

[Krishna Kurapati]

On some SoC's like SA8295P where the tertiary controller is host-only
capable, GEVTADDRHI/LO, GEVTSIZ, GEVTCOUNT registers are not accessible.
Trying to access them leads to a crash.

For DRD/Peripheral supported controllers, event buffer setup is done
again in gadget_pullup. Skip setup or cleanup of event buffers if
controller is host-only capable.

Suggested-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 drivers/usb/dwc3/core.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index edc79ce70588..0aa58600a566 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -486,6 +486,13 @@ static void dwc3_free_event_buffers(struct dwc3 *dwc)
 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
 {
 	struct dwc3_event_buffer *evt;
+	unsigned int hw_mode;
+
+	hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+	if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
+		dwc->ev_buf = NULL;
+		return 0;
+	}
 
 	evt = dwc3_alloc_one_event_buffer(dwc, length);
 	if (IS_ERR(evt)) {
@@ -507,6 +514,9 @@ int dwc3_event_buffers_setup(struct dwc3 *dwc)
 {
 	struct dwc3_event_buffer	*evt;
 
+	if (!dwc->ev_buf)
+		return 0;
+
 	evt = dwc->ev_buf;
 	evt->lpos = 0;
 	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
@@ -524,6 +534,9 @@ void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 {
 	struct dwc3_event_buffer	*evt;
 
+	if (!dwc->ev_buf)
+		return;
+
 	evt = dwc->ev_buf;
 
 	evt->lpos = 0;
-- 
2.40.0

[PATCH v10 05/11] usb: dwc3: core: Refactor PHY logic to support Multiport Controller

[Krishna Kurapati]

From: Harsh Agarwal <quic_harshq@quicinc.com>

Currently the DWC3 driver supports only single port controller
which requires at most one HS and one SS PHY.

But the DWC3 USB controller can be connected to multiple ports and
each port can have their own PHYs. Each port of the multiport
controller can either be HS+SS capable or HS only capable
Proper quantification of them is required to modify GUSB2PHYCFG
and GUSB3PIPECTL registers appropriately.

Add support for detecting, obtaining and configuring phy's supported
by a multiport controller and. Limit the max number of ports
supported to 4 as only SC8280 which is a quad port controller supports
Multiport currently.

Co-developed-by: Harsh Agarwal <quic_harshq@quicinc.com>
Signed-off-by: Harsh Agarwal <quic_harshq@quicinc.com>
Co-developed-by:Krishna Kurapati <quic_kriskura@quicinc.com>
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 drivers/usb/dwc3/core.c | 252 +++++++++++++++++++++++++++-------------
 drivers/usb/dwc3/core.h |  11 +-
 drivers/usb/dwc3/drd.c  |  15 ++-
 3 files changed, 190 insertions(+), 88 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 0aa58600a566..c887c325d3c0 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -124,6 +124,7 @@ static void __dwc3_set_mode(struct work_struct *work)
 	int ret;
 	u32 reg;
 	u32 desired_dr_role;
+	int i;
 
 	mutex_lock(&dwc->mutex);
 	spin_lock_irqsave(&dwc->lock, flags);
@@ -201,8 +202,10 @@ static void __dwc3_set_mode(struct work_struct *work)
 		} else {
 			if (dwc->usb2_phy)
 				otg_set_vbus(dwc->usb2_phy->otg, true);
-			phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
-			phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+			for (i = 0; i < dwc->num_usb2_ports; i++) {
+				phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
+				phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
+			}
 			if (dwc->dis_split_quirk) {
 				reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
 				reg |= DWC3_GUCTL3_SPLITDISABLE;
@@ -217,8 +220,8 @@ static void __dwc3_set_mode(struct work_struct *work)
 
 		if (dwc->usb2_phy)
 			otg_set_vbus(dwc->usb2_phy->otg, false);
-		phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
-		phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
+		phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
+		phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
 
 		ret = dwc3_gadget_init(dwc);
 		if (ret)
@@ -589,22 +592,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 	return ret;
 }
 
-/**
- * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
- * @dwc: Pointer to our controller context structure
- *
- * Returns 0 on success. The USB PHY interfaces are configured but not
- * initialized. The PHY interfaces and the PHYs get initialized together with
- * the core in dwc3_core_init.
- */
-static int dwc3_phy_setup(struct dwc3 *dwc)
+static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
 {
 	unsigned int hw_mode;
 	u32 reg;
 
 	hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 
-	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
+	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
 
 	/*
 	 * Make sure UX_EXIT_PX is cleared as that causes issues with some
@@ -659,9 +654,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_del_phy_power_chg_quirk)
 		reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 
-	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
 
-	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+	return 0;
+}
+
+static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
+{
+	unsigned int hw_mode;
+	u32 reg;
+
+	hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+
+	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
 
 	/* Select the HS PHY interface */
 	switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
@@ -673,7 +678,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 		} else if (dwc->hsphy_interface &&
 				!strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 			reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
-			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
 		} else {
 			/* Relying on default value. */
 			if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
@@ -740,7 +745,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->ulpi_ext_vbus_drv)
 		reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
 
-	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
+
+	return 0;
+}
+
+/**
+ * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
+ * @dwc: Pointer to our controller context structure
+ *
+ * Returns 0 on success. The USB PHY interfaces are configured but not
+ * initialized. The PHY interfaces and the PHYs get initialized together with
+ * the core in dwc3_core_init.
+ */
+static int dwc3_phy_setup(struct dwc3 *dwc)
+{
+	int i;
+	int ret;
+
+	for (i = 0; i < dwc->num_usb3_ports; i++) {
+		ret = dwc3_ss_phy_setup(dwc, i);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < dwc->num_usb2_ports; i++) {
+		ret = dwc3_hs_phy_setup(dwc, i);
+		if (ret)
+			return ret;
+	}
 
 	return 0;
 }
@@ -748,23 +781,32 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 static int dwc3_phy_init(struct dwc3 *dwc)
 {
 	int ret;
+	int i;
+	int j;
 
 	usb_phy_init(dwc->usb2_phy);
 	usb_phy_init(dwc->usb3_phy);
 
-	ret = phy_init(dwc->usb2_generic_phy);
-	if (ret < 0)
-		goto err_shutdown_usb3_phy;
+	for (i = 0; i < dwc->num_usb2_ports; i++) {
+		ret = phy_init(dwc->usb2_generic_phy[i]);
+		if (ret < 0)
+			goto err_exit_phy;
 
-	ret = phy_init(dwc->usb3_generic_phy);
-	if (ret < 0)
-		goto err_exit_usb2_phy;
+		ret = phy_init(dwc->usb3_generic_phy[i]);
+		if (ret < 0) {
+			phy_exit(dwc->usb2_generic_phy[i]);
+			goto err_exit_phy;
+		}
+	}
 
 	return 0;
 
-err_exit_usb2_phy:
-	phy_exit(dwc->usb2_generic_phy);
-err_shutdown_usb3_phy:
+err_exit_phy:
+	for (j = i - 1; j >= 0; j--) {
+		phy_exit(dwc->usb2_generic_phy[j]);
+		phy_exit(dwc->usb3_generic_phy[j]);
+	}
+
 	usb_phy_shutdown(dwc->usb3_phy);
 	usb_phy_shutdown(dwc->usb2_phy);
 
@@ -773,8 +815,12 @@ static int dwc3_phy_init(struct dwc3 *dwc)
 
 static void dwc3_phy_exit(struct dwc3 *dwc)
 {
-	phy_exit(dwc->usb3_generic_phy);
-	phy_exit(dwc->usb2_generic_phy);
+	int i;
+
+	for (i = 0; i < dwc->num_usb2_ports; i++) {
+		phy_exit(dwc->usb3_generic_phy[i]);
+		phy_exit(dwc->usb2_generic_phy[i]);
+	}
 
 	usb_phy_shutdown(dwc->usb3_phy);
 	usb_phy_shutdown(dwc->usb2_phy);
@@ -783,23 +829,32 @@ static void dwc3_phy_exit(struct dwc3 *dwc)
 static int dwc3_phy_power_on(struct dwc3 *dwc)
 {
 	int ret;
+	int i;
+	int j;
 
 	usb_phy_set_suspend(dwc->usb2_phy, 0);
 	usb_phy_set_suspend(dwc->usb3_phy, 0);
 
-	ret = phy_power_on(dwc->usb2_generic_phy);
-	if (ret < 0)
-		goto err_suspend_usb3_phy;
+	for (i = 0; i < dwc->num_usb2_ports; i++) {
+		ret = phy_power_on(dwc->usb2_generic_phy[i]);
+		if (ret < 0)
+			goto err_power_off_phy;
 
-	ret = phy_power_on(dwc->usb3_generic_phy);
-	if (ret < 0)
-		goto err_power_off_usb2_phy;
+		ret = phy_power_on(dwc->usb3_generic_phy[i]);
+		if (ret < 0) {
+			phy_power_off(dwc->usb2_generic_phy[i]);
+			goto err_power_off_phy;
+		}
+	}
 
 	return 0;
 
-err_power_off_usb2_phy:
-	phy_power_off(dwc->usb2_generic_phy);
-err_suspend_usb3_phy:
+err_power_off_phy:
+	for (j = i - 1; j >= 0; j--) {
+		phy_power_off(dwc->usb2_generic_phy[j]);
+		phy_power_off(dwc->usb3_generic_phy[j]);
+	}
+
 	usb_phy_set_suspend(dwc->usb3_phy, 1);
 	usb_phy_set_suspend(dwc->usb2_phy, 1);
 
@@ -808,8 +863,12 @@ static int dwc3_phy_power_on(struct dwc3 *dwc)
 
 static void dwc3_phy_power_off(struct dwc3 *dwc)
 {
-	phy_power_off(dwc->usb3_generic_phy);
-	phy_power_off(dwc->usb2_generic_phy);
+	int i;
+
+	for (i = 0; i < dwc->num_usb2_ports; i++) {
+		phy_power_off(dwc->usb3_generic_phy[i]);
+		phy_power_off(dwc->usb2_generic_phy[i]);
+	}
 
 	usb_phy_set_suspend(dwc->usb3_phy, 1);
 	usb_phy_set_suspend(dwc->usb2_phy, 1);
@@ -1082,6 +1141,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
 	unsigned int		hw_mode;
 	u32			reg;
 	int			ret;
+	int			i;
 
 	hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 
@@ -1125,15 +1185,19 @@ static int dwc3_core_init(struct dwc3 *dwc)
 	if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
 	    !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
 		if (!dwc->dis_u3_susphy_quirk) {
-			reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
-			reg |= DWC3_GUSB3PIPECTL_SUSPHY;
-			dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+			for (i = 0; i < dwc->num_usb3_ports; i++) {
+				reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
+				reg |= DWC3_GUSB3PIPECTL_SUSPHY;
+				dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
+			}
 		}
 
 		if (!dwc->dis_u2_susphy_quirk) {
-			reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
-			reg |= DWC3_GUSB2PHYCFG_SUSPHY;
-			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+			for (i = 0; i < dwc->num_usb2_ports; i++) {
+				reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+				reg |= DWC3_GUSB2PHYCFG_SUSPHY;
+				dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+			}
 		}
 	}
 
@@ -1292,7 +1356,9 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
 {
 	struct device		*dev = dwc->dev;
 	struct device_node	*node = dev->of_node;
+	char phy_name[11];
 	int ret;
+	int i;
 
 	if (node) {
 		dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
@@ -1318,22 +1384,36 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
 			return dev_err_probe(dev, ret, "no usb3 phy configured\n");
 	}
 
-	dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
-	if (IS_ERR(dwc->usb2_generic_phy)) {
-		ret = PTR_ERR(dwc->usb2_generic_phy);
-		if (ret == -ENOSYS || ret == -ENODEV)
-			dwc->usb2_generic_phy = NULL;
+	for (i = 0; i < dwc->num_usb2_ports; i++) {
+		if (dwc->num_usb2_ports == 1)
+			sprintf(phy_name, "usb2-phy");
 		else
-			return dev_err_probe(dev, ret, "no usb2 phy configured\n");
-	}
+			sprintf(phy_name, "usb2-port%d", i);
 
-	dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
-	if (IS_ERR(dwc->usb3_generic_phy)) {
-		ret = PTR_ERR(dwc->usb3_generic_phy);
-		if (ret == -ENOSYS || ret == -ENODEV)
-			dwc->usb3_generic_phy = NULL;
+		dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
+		if (IS_ERR(dwc->usb2_generic_phy[i])) {
+			ret = PTR_ERR(dwc->usb2_generic_phy[i]);
+			if (ret == -ENOSYS || ret == -ENODEV)
+				dwc->usb2_generic_phy[i] = NULL;
+			else
+				return dev_err_probe(dev, ret,
+					"failed to lookup phy %s\n", phy_name);
+		}
+
+		if (dwc->num_usb2_ports == 1)
+			sprintf(phy_name, "usb3-phy");
 		else
-			return dev_err_probe(dev, ret, "no usb3 phy configured\n");
+			sprintf(phy_name, "usb3-port%d", i);
+
+		dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
+		if (IS_ERR(dwc->usb3_generic_phy[i])) {
+			ret = PTR_ERR(dwc->usb3_generic_phy[i]);
+			if (ret == -ENOSYS || ret == -ENODEV)
+				dwc->usb3_generic_phy[i] = NULL;
+			else
+				return dev_err_probe(dev, ret,
+					"failed to lookup phy %s\n", phy_name);
+		}
 	}
 
 	return 0;
@@ -1343,6 +1423,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
 {
 	struct device *dev = dwc->dev;
 	int ret;
+	int i;
 
 	switch (dwc->dr_mode) {
 	case USB_DR_MODE_PERIPHERAL:
@@ -1350,8 +1431,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
 
 		if (dwc->usb2_phy)
 			otg_set_vbus(dwc->usb2_phy->otg, false);
-		phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
-		phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
+		phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
+		phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
 
 		ret = dwc3_gadget_init(dwc);
 		if (ret)
@@ -1362,8 +1443,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
 
 		if (dwc->usb2_phy)
 			otg_set_vbus(dwc->usb2_phy->otg, true);
-		phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
-		phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+		for (i = 0; i < dwc->num_usb2_ports; i++) {
+			phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
+			phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
+		}
 
 		ret = dwc3_host_init(dwc);
 		if (ret)
@@ -1820,9 +1903,12 @@ static int dwc3_read_port_info(struct dwc3 *dwc)
 
 	dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
 			dwc->num_usb2_ports, dwc->num_usb3_ports);
-
 	iounmap(base);
 
+	if ((dwc->num_usb2_ports > DWC3_MAX_PORTS) ||
+		(dwc->num_usb3_ports > DWC3_MAX_PORTS))
+		return -ENOMEM;
+
 	return 0;
 }
 
@@ -2058,6 +2144,7 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
 {
 	unsigned long	flags;
 	u32 reg;
+	int i;
 
 	switch (dwc->current_dr_role) {
 	case DWC3_GCTL_PRTCAP_DEVICE:
@@ -2076,17 +2163,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
 		/* Let controller to suspend HSPHY before PHY driver suspends */
 		if (dwc->dis_u2_susphy_quirk ||
 		    dwc->dis_enblslpm_quirk) {
-			reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
-			reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
-				DWC3_GUSB2PHYCFG_SUSPHY;
-			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+			for (i = 0; i < dwc->num_usb2_ports; i++) {
+				reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+				reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
+					DWC3_GUSB2PHYCFG_SUSPHY;
+				dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+			}
 
 			/* Give some time for USB2 PHY to suspend */
 			usleep_range(5000, 6000);
 		}
 
-		phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
-		phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
+		for (i = 0; i < dwc->num_usb2_ports; i++) {
+			phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
+			phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
+		}
 		break;
 	case DWC3_GCTL_PRTCAP_OTG:
 		/* do nothing during runtime_suspend */
@@ -2116,6 +2207,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
 	unsigned long	flags;
 	int		ret;
 	u32		reg;
+	int		i;
 
 	switch (dwc->current_dr_role) {
 	case DWC3_GCTL_PRTCAP_DEVICE:
@@ -2135,17 +2227,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
 			break;
 		}
 		/* Restore GUSB2PHYCFG bits that were modified in suspend */
-		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
-		if (dwc->dis_u2_susphy_quirk)
-			reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
+		 for (i = 0; i < dwc->num_usb2_ports; i++) {
+			reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+			if (dwc->dis_u2_susphy_quirk)
+				reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 
-		if (dwc->dis_enblslpm_quirk)
-			reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
+			if (dwc->dis_enblslpm_quirk)
+				reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 
-		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+		}
 
-		phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
-		phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
+		for (i = 0; i < dwc->num_usb2_ports; i++) {
+			phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
+			phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
+		}
 		break;
 	case DWC3_GCTL_PRTCAP_OTG:
 		/* nothing to do on runtime_resume */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 0840808e8a40..058a747d8a32 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -33,6 +33,9 @@
 
 #include <linux/power_supply.h>
 
+/* Number of ports supported by a multiport controller */
+#define DWC3_MAX_PORTS 4
+
 #define DWC3_MSG_MAX	500
 
 /* Global constants */
@@ -1027,8 +1030,8 @@ struct dwc3_scratchpad_array {
  * @usb_psy: pointer to power supply interface.
  * @usb2_phy: pointer to USB2 PHY
  * @usb3_phy: pointer to USB3 PHY
- * @usb2_generic_phy: pointer to USB2 PHY
- * @usb3_generic_phy: pointer to USB3 PHY
+ * @usb2_generic_phy: pointer to array of USB2 PHY
+ * @usb3_generic_phy: pointer to array of USB3 PHY
  * @num_usb2_ports: number of USB2 ports
  * @num_usb3_ports: number of USB3 ports
  * @phys_ready: flag to indicate that PHYs are ready
@@ -1167,8 +1170,8 @@ struct dwc3 {
 	struct usb_phy		*usb2_phy;
 	struct usb_phy		*usb3_phy;
 
-	struct phy		*usb2_generic_phy;
-	struct phy		*usb3_generic_phy;
+	struct phy		*usb2_generic_phy[DWC3_MAX_PORTS];
+	struct phy		*usb3_generic_phy[DWC3_MAX_PORTS];
 
 	u8			num_usb2_ports;
 	u8			num_usb3_ports;
diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
index 039bf241769a..9aec41f1ad43 100644
--- a/drivers/usb/dwc3/drd.c
+++ b/drivers/usb/dwc3/drd.c
@@ -331,6 +331,7 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
 	u32 reg;
 	int id;
 	unsigned long flags;
+	int i;
 
 	if (dwc->dr_mode != USB_DR_MODE_OTG)
 		return;
@@ -386,9 +387,12 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
 		} else {
 			if (dwc->usb2_phy)
 				otg_set_vbus(dwc->usb2_phy->otg, true);
-			if (dwc->usb2_generic_phy)
-				phy_set_mode(dwc->usb2_generic_phy,
-					     PHY_MODE_USB_HOST);
+			for (i = 0; i < dwc->num_usb2_ports; i++) {
+				if (dwc->usb2_generic_phy[i]) {
+					phy_set_mode(dwc->usb2_generic_phy[i],
+						     PHY_MODE_USB_HOST);
+				}
+			}
 		}
 		break;
 	case DWC3_OTG_ROLE_DEVICE:
@@ -400,9 +404,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
 
 		if (dwc->usb2_phy)
 			otg_set_vbus(dwc->usb2_phy->otg, false);
-		if (dwc->usb2_generic_phy)
-			phy_set_mode(dwc->usb2_generic_phy,
-				     PHY_MODE_USB_DEVICE);
+		if (dwc->usb2_generic_phy[0])
+			phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
 		ret = dwc3_gadget_init(dwc);
 		if (ret)
 			dev_err(dwc->dev, "failed to initialize peripheral\n");
-- 
2.40.0

[PATCH v10 06/11] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver

[Krishna Kurapati]

Refactor setup_irq call to facilitate reading multiport IRQ's along
with non mulitport ones. For SA8295, there are 4-DP/4-DM and 2-SS
IRQ's. Check whether device is multiport capable or not and read all
interrupts for DP/DM/SS on each port accordingly.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 drivers/usb/dwc3/dwc3-qcom.c | 277 ++++++++++++++++++++++++-----------
 1 file changed, 190 insertions(+), 87 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 3de43df6bbe8..ad89ded116d3 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -64,33 +64,61 @@ struct dwc3_acpi_pdata {
 	bool			is_urs;
 };
 
+struct dwc3_qcom_of_match_data {
+	u8	num_ports;
+};
+
 struct dwc3_qcom {
-	struct device		*dev;
-	void __iomem		*qscratch_base;
-	struct platform_device	*dwc3;
-	struct platform_device	*urs_usb;
-	struct clk		**clks;
-	int			num_clocks;
-	struct reset_control	*resets;
-
-	int			hs_phy_irq;
-	int			dp_hs_phy_irq;
-	int			dm_hs_phy_irq;
-	int			ss_phy_irq;
-	enum usb_device_speed	usb2_speed;
-
-	struct extcon_dev	*edev;
-	struct extcon_dev	*host_edev;
-	struct notifier_block	vbus_nb;
-	struct notifier_block	host_nb;
+	struct device				*dev;
+	void __iomem				*qscratch_base;
+	struct platform_device			*dwc3;
+	struct platform_device			*urs_usb;
+	struct clk				**clks;
+	int					num_clocks;
+	struct reset_control			*resets;
+
+	int					hs_phy_irq;
+	int					dp_hs_phy_irq[DWC3_MAX_PORTS];
+	int					dm_hs_phy_irq[DWC3_MAX_PORTS];
+	int					ss_phy_irq[DWC3_MAX_PORTS];
+	enum usb_device_speed			usb2_speed;
+
+	struct extcon_dev			*edev;
+	struct extcon_dev			*host_edev;
+	struct notifier_block			vbus_nb;
+	struct notifier_block			host_nb;
+
+	const struct dwc3_acpi_pdata		*acpi_pdata;
+
+	enum usb_dr_mode			mode;
+	bool					is_suspended;
+	bool					pm_suspended;
+	struct icc_path				*icc_path_ddr;
+	struct icc_path				*icc_path_apps;
+	const struct dwc3_qcom_of_match_data	*data;
+};
+
+static const struct dwc3_qcom_of_match_data qcom_dwc3  = {
+	.num_ports = 1,
+};
 
-	const struct dwc3_acpi_pdata *acpi_pdata;
+static const struct dwc3_qcom_of_match_data sx8280xp_qcom_dwc3 = {
+	.num_ports = 4,
+};
 
-	enum usb_dr_mode	mode;
-	bool			is_suspended;
-	bool			pm_suspended;
-	struct icc_path		*icc_path_ddr;
-	struct icc_path		*icc_path_apps;
+/*
+ * Driver needs to read HS/DP_HS/DM_HS/SS IRQ's. Currently, for
+ * SA8295 which supports mutliport, thre are 4 DP/ 4 DM/ 2 SS IRQ's
+ * and 1 HS IRQ present. So avoid trying to read HS_PHY_IRQ for 4
+ * ports of SA8295.
+ */
+#define MAX_PHY_IRQ	4
+
+enum dwc3_qcom_phy_irq_identifier {
+	HS_PHY_IRQ = 0,
+	DP_HS_PHY_IRQ,
+	DM_HS_PHY_IRQ,
+	SS_PHY_IRQ,
 };
 
 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
@@ -375,16 +403,16 @@ static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
 	dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
 
 	if (qcom->usb2_speed == USB_SPEED_LOW) {
-		dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
+		dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[0]);
 	} else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
 			(qcom->usb2_speed == USB_SPEED_FULL)) {
-		dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
+		dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[0]);
 	} else {
-		dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
-		dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
+		dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[0]);
+		dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[0]);
 	}
 
-	dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
+	dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq[0]);
 }
 
 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
@@ -401,20 +429,20 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
 	 */
 
 	if (qcom->usb2_speed == USB_SPEED_LOW) {
-		dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
+		dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[0],
 						IRQ_TYPE_EDGE_FALLING);
 	} else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
 			(qcom->usb2_speed == USB_SPEED_FULL)) {
-		dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
+		dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[0],
 						IRQ_TYPE_EDGE_FALLING);
 	} else {
-		dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
+		dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[0],
 						IRQ_TYPE_EDGE_RISING);
-		dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
+		dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[0],
 						IRQ_TYPE_EDGE_RISING);
 	}
 
-	dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
+	dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq[0], 0);
 }
 
 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
@@ -535,72 +563,138 @@ static int dwc3_qcom_get_irq(struct platform_device *pdev,
 	return ret;
 }
 
-static int dwc3_qcom_setup_irq(struct platform_device *pdev)
+static int dwc3_qcom_prep_irq(struct dwc3_qcom *qcom, char *irq_name,
+				char *disp_name, int irq)
 {
-	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
-	const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
-	int irq;
 	int ret;
 
-	irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
-				pdata ? pdata->hs_phy_irq_index : -1);
-	if (irq > 0) {
-		/* Keep wakeup interrupts disabled until suspend */
-		irq_set_status_flags(irq, IRQ_NOAUTOEN);
-		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
+	/* Keep wakeup interrupts disabled until suspend */
+	irq_set_status_flags(irq, IRQ_NOAUTOEN);
+	ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 					qcom_dwc3_resume_irq,
 					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
-					"qcom_dwc3 HS", qcom);
-		if (ret) {
-			dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
-			return ret;
+					disp_name, qcom);
+	if (ret)
+		dev_err(qcom->dev, "%s failed: %d\n", irq_name, ret);
+
+	return ret;
+}
+
+static int dwc3_get_acpi_index(const struct dwc3_acpi_pdata *pdata, int irq_index)
+{
+	int acpi_index = -1;
+
+	if (!pdata)
+		return -1;
+
+	if (irq_index == DP_HS_PHY_IRQ)
+		acpi_index = pdata->dp_hs_phy_irq_index;
+	else if (irq_index == DM_HS_PHY_IRQ)
+		acpi_index = pdata->dm_hs_phy_irq_index;
+	else if (irq_index == SS_PHY_IRQ)
+		acpi_index = pdata->ss_phy_irq_index;
+
+	return acpi_index;
+}
+
+static int dwc3_get_port_irq(struct platform_device *pdev, u8 port_index)
+{
+	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
+	bool is_mp_supported = (qcom->data->num_ports > 1) ? true : false;
+	const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
+	char *disp_name;
+	int acpi_index;
+	char *dt_name;
+	int ret;
+	int irq;
+	int i;
+
+	/*
+	 * We need to read only DP/DM/SS IRQ's here.
+	 * So loop over from 1->3 and accordingly modify respective phy_irq[].
+	 */
+	for (i = 1; i < MAX_PHY_IRQ; i++) {
+
+		if (!is_mp_supported && (port_index == 0)) {
+			if (i == DP_HS_PHY_IRQ) {
+				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"dp_hs_phy_irq");
+				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"qcom_dwc3 DP_HS");
+			} else if (i == DM_HS_PHY_IRQ) {
+				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"dm_hs_phy_irq");
+				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"qcom_dwc3 DM_HS");
+			} else if (i == SS_PHY_IRQ) {
+				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"ss_phy_irq");
+				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"qcom_dwc3 SS");
+			}
+		} else {
+			if (i == DP_HS_PHY_IRQ) {
+				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"dp_hs_phy_%d", port_index + 1);
+				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"qcom_dwc3 DP_HS%d", port_index + 1);
+			} else if (i == DM_HS_PHY_IRQ) {
+				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"dm_hs_phy_%d", port_index + 1);
+				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"qcom_dwc3 DM_HS%d", port_index + 1);
+			} else if (i == SS_PHY_IRQ) {
+				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"ss_phy_%d", port_index + 1);
+				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					"qcom_dwc3 SS%d", port_index + 1);
+			}
 		}
-		qcom->hs_phy_irq = irq;
-	}
 
-	irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
-				pdata ? pdata->dp_hs_phy_irq_index : -1);
-	if (irq > 0) {
-		irq_set_status_flags(irq, IRQ_NOAUTOEN);
-		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
-					qcom_dwc3_resume_irq,
-					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
-					"qcom_dwc3 DP_HS", qcom);
-		if (ret) {
-			dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
-			return ret;
+		if (!dt_name || !disp_name)
+			return -ENOMEM;
+
+		acpi_index = !is_mp_supported ? dwc3_get_acpi_index(pdata, i) : -1;
+
+		irq = dwc3_qcom_get_irq(pdev, dt_name, acpi_index);
+		if (irq > 0) {
+			ret = dwc3_qcom_prep_irq(qcom, dt_name, disp_name, irq);
+			if (ret)
+				return ret;
+
+			if (i == DP_HS_PHY_IRQ)
+				qcom->dp_hs_phy_irq[port_index] = irq;
+			else if (i == DM_HS_PHY_IRQ)
+				qcom->dm_hs_phy_irq[port_index] = irq;
+			else if (i == SS_PHY_IRQ)
+				qcom->ss_phy_irq[port_index] = irq;
 		}
-		qcom->dp_hs_phy_irq = irq;
 	}
 
-	irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
-				pdata ? pdata->dm_hs_phy_irq_index : -1);
+	return 0;
+}
+
+static int dwc3_qcom_setup_irq(struct platform_device *pdev)
+{
+	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
+	const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
+	int irq;
+	int ret;
+	int i;
+
+	irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
+				pdata ? pdata->hs_phy_irq_index : -1);
 	if (irq > 0) {
-		irq_set_status_flags(irq, IRQ_NOAUTOEN);
-		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
-					qcom_dwc3_resume_irq,
-					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
-					"qcom_dwc3 DM_HS", qcom);
-		if (ret) {
-			dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
+		ret = dwc3_qcom_prep_irq(qcom, "hs_phy_irq", "qcom_dwc3 HS",irq);
+		if (ret)
 			return ret;
-		}
-		qcom->dm_hs_phy_irq = irq;
+		qcom->hs_phy_irq = irq;
 	}
 
-	irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
-				pdata ? pdata->ss_phy_irq_index : -1);
-	if (irq > 0) {
-		irq_set_status_flags(irq, IRQ_NOAUTOEN);
-		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
-					qcom_dwc3_resume_irq,
-					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
-					"qcom_dwc3 SS", qcom);
-		if (ret) {
-			dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
+	for (i = 0; i < qcom->data->num_ports; i++) {
+		ret = dwc3_get_port_irq(pdev, i);
+		if (ret)
 			return ret;
-		}
-		qcom->ss_phy_irq = irq;
 	}
 
 	return 0;
@@ -811,6 +905,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, qcom);
 	qcom->dev = &pdev->dev;
 
+	qcom->data = of_device_get_match_data(qcom->dev);
+
 	if (has_acpi_companion(dev)) {
 		qcom->acpi_pdata = acpi_device_get_match_data(dev);
 		if (!qcom->acpi_pdata) {
@@ -1023,8 +1119,15 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
 };
 
 static const struct of_device_id dwc3_qcom_of_match[] = {
-	{ .compatible = "qcom,dwc3" },
-	{ }
+	{
+		.compatible = "qcom,dwc3",
+		.data = &qcom_dwc3,
+	},
+	{
+		.compatible = "qcom,sc8280xp-dwc3-mp",
+		.data = &sx8280xp_qcom_dwc3,
+	},
+	{ },
 };
 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
 
-- 
2.40.0

[PATCH v10 07/11] usb: dwc3: qcom: Enable wakeup for applicable ports of multiport

[Krishna Kurapati]

Currently wakeup is supported by only single port controllers. Read speed
of each port and accordingly enable IRQ's for those ports.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 drivers/usb/dwc3/dwc3-qcom.c | 64 ++++++++++++++++++++----------------
 1 file changed, 35 insertions(+), 29 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index ad89ded116d3..a98223291306 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -81,7 +81,7 @@ struct dwc3_qcom {
 	int					dp_hs_phy_irq[DWC3_MAX_PORTS];
 	int					dm_hs_phy_irq[DWC3_MAX_PORTS];
 	int					ss_phy_irq[DWC3_MAX_PORTS];
-	enum usb_device_speed			usb2_speed;
+	enum usb_device_speed			usb2_speed[DWC3_MAX_PORTS];
 
 	struct extcon_dev			*edev;
 	struct extcon_dev			*host_edev;
@@ -349,7 +349,8 @@ static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
 	return dwc->xhci;
 }
 
-static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
+static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom,
+							int port_index)
 {
 	struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
 	struct usb_device *udev;
@@ -362,12 +363,10 @@ static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
 
 	/*
 	 * It is possible to query the speed of all children of
-	 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code
-	 * currently supports only 1 port per controller. So
-	 * this is sufficient.
+	 * USB2.0 root hub via usb_hub_for_each_child().
 	 */
 #ifdef CONFIG_USB
-	udev = usb_hub_find_child(hcd->self.root_hub, 1);
+	udev = usb_hub_find_child(hcd->self.root_hub, port_index + 1);
 #else
 	udev = NULL;
 #endif
@@ -400,23 +399,29 @@ static void dwc3_qcom_disable_wakeup_irq(int irq)
 
 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
 {
+	int i;
+
 	dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
 
-	if (qcom->usb2_speed == USB_SPEED_LOW) {
-		dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[0]);
-	} else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
-			(qcom->usb2_speed == USB_SPEED_FULL)) {
-		dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[0]);
-	} else {
-		dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[0]);
-		dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[0]);
-	}
+	for (i = 0; i < qcom->data->num_ports; i++) {
+		if (qcom->usb2_speed[i] == USB_SPEED_LOW) {
+			dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[i]);
+		} else if ((qcom->usb2_speed[i] == USB_SPEED_HIGH) ||
+				(qcom->usb2_speed[i] == USB_SPEED_FULL)) {
+			dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[i]);
+		} else {
+			dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[i]);
+			dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[i]);
+		}
 
-	dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq[0]);
+		dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq[i]);
+	}
 }
 
 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
 {
+	int i;
+
 	dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0);
 
 	/*
@@ -427,22 +432,25 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
 	 * disconnect and remote wakeup. When no device is connected, configure both
 	 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario.
 	 */
+	for (i = 0; i < qcom->data->num_ports; i++) {
+		qcom->usb2_speed[i] = dwc3_qcom_read_usb2_speed(qcom, i);
 
-	if (qcom->usb2_speed == USB_SPEED_LOW) {
-		dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[0],
+		if (qcom->usb2_speed[i] == USB_SPEED_LOW) {
+			dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[i],
 						IRQ_TYPE_EDGE_FALLING);
-	} else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
-			(qcom->usb2_speed == USB_SPEED_FULL)) {
-		dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[0],
+		} else if ((qcom->usb2_speed[i] == USB_SPEED_HIGH) ||
+			(qcom->usb2_speed[i] == USB_SPEED_FULL)) {
+			dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[i],
 						IRQ_TYPE_EDGE_FALLING);
-	} else {
-		dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[0],
+		} else {
+			dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[i],
 						IRQ_TYPE_EDGE_RISING);
-		dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[0],
+			dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[i],
 						IRQ_TYPE_EDGE_RISING);
-	}
+		}
 
-	dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq[0], 0);
+		dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq[i], 0);
+	}
 }
 
 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
@@ -468,10 +476,8 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
 	 * The role is stable during suspend as role switching is done from a
 	 * freezable workqueue.
 	 */
-	if (dwc3_qcom_is_host(qcom) && wakeup) {
-		qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom);
+	if (dwc3_qcom_is_host(qcom) && wakeup)
 		dwc3_qcom_enable_interrupts(qcom);
-	}
 
 	qcom->is_suspended = true;
 
-- 
2.40.0

[PATCH v10 08/11] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper

[Krishna Kurapati]

QCOM SoC SA8295P's tertiary quad port controller supports 2 HS+SS
ports and 2 HS only ports. Add support for configuring PWR_EVENT_IRQ's
for all the ports during suspend/resume.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 drivers/usb/dwc3/dwc3-qcom.c | 38 ++++++++++++++++++++++++++++++------
 1 file changed, 32 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index a98223291306..2db1472eed21 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -37,7 +37,11 @@
 #define PIPE3_PHYSTATUS_SW			BIT(3)
 #define PIPE_UTMI_CLK_DIS			BIT(8)
 
-#define PWR_EVNT_IRQ_STAT_REG			0x58
+#define PWR_EVNT_IRQ1_STAT_REG			0x58
+#define PWR_EVNT_IRQ2_STAT_REG			0x1dc
+#define PWR_EVNT_IRQ3_STAT_REG			0x228
+#define PWR_EVNT_IRQ4_STAT_REG			0x238
+
 #define PWR_EVNT_LPM_IN_L2_MASK			BIT(4)
 #define PWR_EVNT_LPM_OUT_L2_MASK		BIT(5)
 
@@ -121,6 +125,19 @@ enum dwc3_qcom_phy_irq_identifier {
 	SS_PHY_IRQ,
 };
 
+/*
+ * SA8295 has 4 power event IRQ STAT registers to be checked
+ * during suspend resume.
+ */
+#define NUM_PWR_EVENT_STAT_REGS	4
+
+static u32 pwr_evnt_irq_stat_reg_offset[NUM_PWR_EVENT_STAT_REGS] = {
+	PWR_EVNT_IRQ1_STAT_REG,
+	PWR_EVNT_IRQ2_STAT_REG,
+	PWR_EVNT_IRQ3_STAT_REG,
+	PWR_EVNT_IRQ4_STAT_REG,
+};
+
 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
 {
 	u32 reg;
@@ -455,15 +472,19 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
 
 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
 {
+	u8 num_ports;
 	u32 val;
 	int i, ret;
 
 	if (qcom->is_suspended)
 		return 0;
 
-	val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
-	if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
-		dev_err(qcom->dev, "HS-PHY not in L2\n");
+	num_ports = qcom->data->num_ports;
+	for (i = 0; i < num_ports; i++) {
+		val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg_offset[i]);
+		if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
+			dev_err(qcom->dev, "HS-PHY not in L2\n");
+	}
 
 	for (i = qcom->num_clocks - 1; i >= 0; i--)
 		clk_disable_unprepare(qcom->clks[i]);
@@ -486,6 +507,7 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
 
 static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
 {
+	u8 num_ports;
 	int ret;
 	int i;
 
@@ -509,8 +531,12 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
 		dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
 
 	/* Clear existing events from PHY related to L2 in/out */
-	dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
-			  PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
+	num_ports = qcom->data->num_ports;
+	for (i = 0; i < num_ports; i++) {
+		dwc3_qcom_setbits(qcom->qscratch_base,
+			pwr_evnt_irq_stat_reg_offset[i],
+			PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
+	}
 
 	qcom->is_suspended = false;
 
-- 
2.40.0

[PATCH v10 09/11] arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280

[Krishna Kurapati]

Add USB and DWC3 node for tertiary port of SC8280 along with multiport
IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
platforms.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 77 ++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index ac0596dfdbc4..a9401351d49c 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3329,6 +3329,83 @@ system-cache-controller@9200000 {
 			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		usb_2: usb@a4f8800 {
+			compatible = "qcom,sc8280xp-dwc3-mp";
+			reg = <0 0x0a4f8800 0 0x400>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
+				 <&gcc GCC_USB30_MP_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
+				 <&gcc GCC_USB30_MP_SLEEP_CLK>,
+				 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
+				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
+				      "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
+
+			assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_MP_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
+					      <&pdc 126 IRQ_TYPE_EDGE_RISING>,
+					      <&pdc 129 IRQ_TYPE_EDGE_RISING>,
+					      <&pdc 128 IRQ_TYPE_EDGE_RISING>,
+					      <&pdc 131 IRQ_TYPE_EDGE_RISING>,
+					      <&pdc 130 IRQ_TYPE_EDGE_RISING>,
+					      <&pdc 133 IRQ_TYPE_EDGE_RISING>,
+					      <&pdc 132 IRQ_TYPE_EDGE_RISING>,
+					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
+
+			interrupt-names = "dp_hs_phy_1", "dm_hs_phy_1",
+					  "dp_hs_phy_2", "dm_hs_phy_2",
+					  "dp_hs_phy_3", "dm_hs_phy_3",
+					  "dp_hs_phy_4", "dm_hs_phy_4",
+					  "ss_phy_1", "ss_phy_2",
+					  "pwr_event_1",
+					  "pwr_event_2",
+					  "pwr_event_3",
+					  "pwr_event_4";
+
+			power-domains = <&gcc USB30_MP_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB30_MP_BCR>;
+
+			interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>,
+					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			wakeup-source;
+
+			status = "disabled";
+
+			usb_2_dwc3: usb@a400000 {
+				compatible = "snps,dwc3";
+				reg = <0 0x0a400000 0 0xcd00>;
+				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0x800 0x0>;
+				phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
+				       <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
+				       <&usb_2_hsphy2>,
+				       <&usb_2_hsphy3>;
+				phy-names = "usb2-port0", "usb3-port0",
+					    "usb2-port1", "usb3-port1",
+					    "usb2-port2",
+					    "usb2-port3";
+			};
+		};
+
 		usb_0: usb@a6f8800 {
 			compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
 			reg = <0 0x0a6f8800 0 0x400>;
-- 
2.40.0

[PATCH v10 10/11] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports

[Krishna Kurapati]

Enable tertiary controller for SA8295P (based on SC8280XP).
Add pinctrl support for usb ports to provide VBUS to connected peripherals.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 53 ++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index fd253942e5e5..473fe858fbed 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 
 #include "sa8540p.dtsi"
 #include "sa8540p-pmics.dtsi"
@@ -584,6 +585,20 @@ &usb_1_qmpphy {
 	status = "okay";
 };
 
+&usb_2 {
+	pinctrl-0 = <&usb2_en_state>,
+		    <&usb3_en_state>,
+		    <&usb4_en_state>,
+		    <&usb5_en_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	dr_mode = "host";
+};
+
 &usb_2_hsphy0 {
 	vdda-pll-supply = <&vreg_l5a>;
 	vdda18-supply = <&vreg_l7g>;
@@ -729,3 +744,41 @@ wake-n-pins {
 		};
 	};
 };
+
+&pmm8540c_gpios {
+	usb2_en_state: usb2-en-state {
+		pins = "gpio9";
+		function = "normal";
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+		output-high;
+		power-source = <0>;
+	};
+};
+
+&pmm8540e_gpios {
+	usb3_en_state: usb3-en-state {
+		pins = "gpio5";
+		function = "normal";
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+		output-high;
+		power-source = <0>;
+	};
+};
+
+&pmm8540g_gpios {
+	usb4_en_state: usb4-en-state {
+		pins = "gpio5";
+		function = "normal";
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+		output-high;
+		power-source = <0>;
+	};
+
+	usb5_en_state: usb5-en-state {
+		pins = "gpio9";
+		function = "normal";
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+		output-high;
+		power-source = <0>;
+	};
+};
-- 
2.40.0

[PATCH v10 11/11] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller

[Krishna Kurapati]

From: Andrew Halaney <ahalaney@redhat.com>

There is now support for the multiport USB controller this uses so
enable it.

The board only has a single port hooked up (despite it being wired up to
the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
which by default on boot is selected to mux properly. Grab the gpio
controlling that and ensure it stays in the right position so USB 2.0
continues to be routed from the external port to the SoC.

Co-developed-by: Andrew Halaney <ahalaney@redhat.com>
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
[Krishna: Rebased on top of usb-next]
Co-developed-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 5a26974dcf8f..69f6b13e6197 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -488,6 +488,19 @@ &usb_2_qmpphy0 {
 	status = "okay";
 };
 
+&usb_2 {
+	pinctrl-0 = <&usb2_en_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	dr_mode = "host";
+	phy-names = "usb2-port0", "usb3-port0";
+	phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>;
+};
+
 &xo_board_clk {
 	clock-frequency = <38400000>;
 };
@@ -640,4 +653,13 @@ wake-pins {
 			bias-pull-up;
 		};
 	};
+
+	usb2_en_state: usb2-en-state {
+		/* TS3USB221A USB2.0 mux select */
+		pins = "gpio24";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
 };
-- 
2.40.0

Re: [PATCH v10 01/11] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport

[Krzysztof Kozlowski]

On 28/07/2023 00:32, Krishna Kurapati wrote:
> Add the compatible string for SC8280 Multiport USB controller from
> Qualcomm.
> 
> There are 4 power event irq interrupts supported by this controller
> (one for each port of multiport). Added all the 4 as non-optional
> interrupts for SC8280XP-MP
> 
> Also each port of multiport has one DP and oen DM IRQ. Add all DP/DM
> IRQ's related to 4 ports of SC8280XP Teritiary controller.
> 
> Also added ss phy irq for both SS Ports.
> 
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
>  .../devicetree/bindings/usb/qcom,dwc3.yaml    | 29 +++++++++++++++++++
>  1 file changed, 29 insertions(+)


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v10 03/11] usb: dwc3: core: Access XHCI address space temporarily to read port info

[Thinh Nguyen]

On Fri, Jul 28, 2023, Krishna Kurapati wrote:
> Currently host-only capable DWC3 controllers support Multiport.
> Temporarily map XHCI address space for host-only controllers and parse
> XHCI Extended Capabilities registers to read number of usb2 ports and
> usb3 ports present on multiport controller. Each USB Port is at least HS
> capable.
> 
> Since the extcaps header is only being used, move port_count related
> macros and structure from xhci.h to xhci-ext-caps.h.
> 
> The port info for usb2 and usb3 phy are identified as num_usb2_ports
> and num_usb3_ports. The intention is as follows:
> 
> Wherever we need to perform phy operations like:
> 
> LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> {
> 	phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> 	phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> }
> 
> If number of usb2 ports is 3, loop can go from index 0-2 for
> usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
> if the first 2 ports are SS capable or some other ports like (2 and 3)
> are SS capable. So instead, num_usb2_ports is used to loop around all
> phy's (both hs and ss) for performing phy operations. If any
> usb3_generic_phy turns out to be NULL, phy operation just bails out.
> 
> num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> phy's as we need to know how many SS capable ports are there for this.
> 
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
>  drivers/usb/dwc3/core.c          | 61 ++++++++++++++++++++++++++++++++
>  drivers/usb/dwc3/core.h          |  5 +++
>  drivers/usb/host/xhci-ext-caps.h | 27 ++++++++++++++
>  drivers/usb/host/xhci.h          | 27 --------------
>  4 files changed, 93 insertions(+), 27 deletions(-)

Please split the moving of code for xhci in a separate commit.

Thanks,
Thinh

Re: [PATCH v10 04/11] usb: dwc3: core: Skip setting event buffers for host only controllers

[Thinh Nguyen]

On Fri, Jul 28, 2023, Krishna Kurapati wrote:
> On some SoC's like SA8295P where the tertiary controller is host-only
> capable, GEVTADDRHI/LO, GEVTSIZ, GEVTCOUNT registers are not accessible.
> Trying to access them leads to a crash.
> 
> For DRD/Peripheral supported controllers, event buffer setup is done
> again in gadget_pullup. Skip setup or cleanup of event buffers if
> controller is host-only capable.
> 
> Suggested-by: Johan Hovold <johan@kernel.org>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
>  drivers/usb/dwc3/core.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index edc79ce70588..0aa58600a566 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -486,6 +486,13 @@ static void dwc3_free_event_buffers(struct dwc3 *dwc)
>  static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
>  {
>  	struct dwc3_event_buffer *evt;
> +	unsigned int hw_mode;
> +
> +	hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> +	if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
> +		dwc->ev_buf = NULL;
> +		return 0;
> +	}
>  
>  	evt = dwc3_alloc_one_event_buffer(dwc, length);
>  	if (IS_ERR(evt)) {
> @@ -507,6 +514,9 @@ int dwc3_event_buffers_setup(struct dwc3 *dwc)
>  {
>  	struct dwc3_event_buffer	*evt;
>  
> +	if (!dwc->ev_buf)
> +		return 0;
> +
>  	evt = dwc->ev_buf;
>  	evt->lpos = 0;
>  	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
> @@ -524,6 +534,9 @@ void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
>  {
>  	struct dwc3_event_buffer	*evt;
>  
> +	if (!dwc->ev_buf)
> +		return;
> +
>  	evt = dwc->ev_buf;
>  
>  	evt->lpos = 0;
> -- 
> 2.40.0
> 

Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>

Thanks,
Thinh

Re: [PATCH v10 06/11] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver

[Bjorn Andersson]

On Fri, Jul 28, 2023 at 04:03:02AM +0530, Krishna Kurapati wrote:
> Refactor setup_irq call to facilitate reading multiport IRQ's along
> with non mulitport ones. For SA8295, there are 4-DP/4-DM and 2-SS
> IRQ's. Check whether device is multiport capable or not and read all
> interrupts for DP/DM/SS on each port accordingly.
> 
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
>  drivers/usb/dwc3/dwc3-qcom.c | 277 ++++++++++++++++++++++++-----------
>  1 file changed, 190 insertions(+), 87 deletions(-)
> 
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index 3de43df6bbe8..ad89ded116d3 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -64,33 +64,61 @@ struct dwc3_acpi_pdata {
>  	bool			is_urs;
>  };
>  
> +struct dwc3_qcom_of_match_data {
> +	u8	num_ports;
> +};
> +
>  struct dwc3_qcom {
> -	struct device		*dev;
> -	void __iomem		*qscratch_base;
> -	struct platform_device	*dwc3;
> -	struct platform_device	*urs_usb;
> -	struct clk		**clks;
> -	int			num_clocks;
> -	struct reset_control	*resets;
> -
> -	int			hs_phy_irq;
> -	int			dp_hs_phy_irq;
> -	int			dm_hs_phy_irq;
> -	int			ss_phy_irq;
> -	enum usb_device_speed	usb2_speed;
> -
> -	struct extcon_dev	*edev;
> -	struct extcon_dev	*host_edev;
> -	struct notifier_block	vbus_nb;
> -	struct notifier_block	host_nb;
> +	struct device				*dev;
> +	void __iomem				*qscratch_base;
> +	struct platform_device			*dwc3;
> +	struct platform_device			*urs_usb;
> +	struct clk				**clks;
> +	int					num_clocks;
> +	struct reset_control			*resets;
> +
> +	int					hs_phy_irq;
> +	int					dp_hs_phy_irq[DWC3_MAX_PORTS];
> +	int					dm_hs_phy_irq[DWC3_MAX_PORTS];
> +	int					ss_phy_irq[DWC3_MAX_PORTS];
> +	enum usb_device_speed			usb2_speed;
> +
> +	struct extcon_dev			*edev;
> +	struct extcon_dev			*host_edev;
> +	struct notifier_block			vbus_nb;
> +	struct notifier_block			host_nb;
> +
> +	const struct dwc3_acpi_pdata		*acpi_pdata;
> +
> +	enum usb_dr_mode			mode;
> +	bool					is_suspended;
> +	bool					pm_suspended;
> +	struct icc_path				*icc_path_ddr;
> +	struct icc_path				*icc_path_apps;
> +	const struct dwc3_qcom_of_match_data	*data;

Please don't adjust indentation of unrelated code, it makes it hard to
see what actually changed.

> +};
> +
> +static const struct dwc3_qcom_of_match_data qcom_dwc3  = {
> +	.num_ports = 1,
> +};
>  
> -	const struct dwc3_acpi_pdata *acpi_pdata;
> +static const struct dwc3_qcom_of_match_data sx8280xp_qcom_dwc3 = {
> +	.num_ports = 4,
> +};
>  
> -	enum usb_dr_mode	mode;
> -	bool			is_suspended;
> -	bool			pm_suspended;
> -	struct icc_path		*icc_path_ddr;
> -	struct icc_path		*icc_path_apps;
> +/*
> + * Driver needs to read HS/DP_HS/DM_HS/SS IRQ's. Currently, for
> + * SA8295 which supports mutliport, thre are 4 DP/ 4 DM/ 2 SS IRQ's
> + * and 1 HS IRQ present. So avoid trying to read HS_PHY_IRQ for 4
> + * ports of SA8295.
> + */

The last part here is relevant information, but it doesn't seem to
relate to this define.

Also, does all platforms have this configuration of interrupts?

> +#define MAX_PHY_IRQ	4
> +
> +enum dwc3_qcom_phy_irq_identifier {
> +	HS_PHY_IRQ = 0,
> +	DP_HS_PHY_IRQ,
> +	DM_HS_PHY_IRQ,
> +	SS_PHY_IRQ,
>  };

This enum is unused.

>  
[..]
> +static int dwc3_get_acpi_index(const struct dwc3_acpi_pdata *pdata, int irq_index)
> +{
> +	int acpi_index = -1;
> +
> +	if (!pdata)
> +		return -1;
> +
> +	if (irq_index == DP_HS_PHY_IRQ)
> +		acpi_index = pdata->dp_hs_phy_irq_index;
> +	else if (irq_index == DM_HS_PHY_IRQ)
> +		acpi_index = pdata->dm_hs_phy_irq_index;
> +	else if (irq_index == SS_PHY_IRQ)
> +		acpi_index = pdata->ss_phy_irq_index;

It looks favourable to put these in an array, instead of having to pull
them out of 4 different variables conditionally.

> +
> +	return acpi_index;
> +}
> +
> +static int dwc3_get_port_irq(struct platform_device *pdev, u8 port_index)
> +{
> +	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
> +	bool is_mp_supported = (qcom->data->num_ports > 1) ? true : false;
> +	const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
> +	char *disp_name;
> +	int acpi_index;
> +	char *dt_name;
> +	int ret;
> +	int irq;
> +	int i;
> +
> +	/*
> +	 * We need to read only DP/DM/SS IRQ's here.
> +	 * So loop over from 1->3 and accordingly modify respective phy_irq[].
> +	 */
> +	for (i = 1; i < MAX_PHY_IRQ; i++) {
> +
> +		if (!is_mp_supported && (port_index == 0)) {
> +			if (i == DP_HS_PHY_IRQ) {
> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"dp_hs_phy_irq");
> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"qcom_dwc3 DP_HS");
> +			} else if (i == DM_HS_PHY_IRQ) {
> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"dm_hs_phy_irq");
> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"qcom_dwc3 DM_HS");
> +			} else if (i == SS_PHY_IRQ) {
> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"ss_phy_irq");
> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"qcom_dwc3 SS");
> +			}
> +		} else {
> +			if (i == DP_HS_PHY_IRQ) {
> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"dp_hs_phy_%d", port_index + 1);
> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"qcom_dwc3 DP_HS%d", port_index + 1);
> +			} else if (i == DM_HS_PHY_IRQ) {
> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"dm_hs_phy_%d", port_index + 1);
> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"qcom_dwc3 DM_HS%d", port_index + 1);
> +			} else if (i == SS_PHY_IRQ) {
> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"ss_phy_%d", port_index + 1);
> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +					"qcom_dwc3 SS%d", port_index + 1);
> +			}

There is too much repetition in this for my liking.

>  		}
> -		qcom->hs_phy_irq = irq;
> -	}
>  
> -	irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
> -				pdata ? pdata->dp_hs_phy_irq_index : -1);
> -	if (irq > 0) {
> -		irq_set_status_flags(irq, IRQ_NOAUTOEN);
> -		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
> -					qcom_dwc3_resume_irq,
> -					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
> -					"qcom_dwc3 DP_HS", qcom);
> -		if (ret) {
> -			dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
> -			return ret;
> +		if (!dt_name || !disp_name)
> +			return -ENOMEM;
> +
> +		acpi_index = !is_mp_supported ? dwc3_get_acpi_index(pdata, i) : -1;
> +
> +		irq = dwc3_qcom_get_irq(pdev, dt_name, acpi_index);
> +		if (irq > 0) {
> +			ret = dwc3_qcom_prep_irq(qcom, dt_name, disp_name, irq);
> +			if (ret)
> +				return ret;
> +
> +			if (i == DP_HS_PHY_IRQ)
> +				qcom->dp_hs_phy_irq[port_index] = irq;
> +			else if (i == DM_HS_PHY_IRQ)
> +				qcom->dm_hs_phy_irq[port_index] = irq;
> +			else if (i == SS_PHY_IRQ)
> +				qcom->ss_phy_irq[port_index] = irq;
>  		}
> -		qcom->dp_hs_phy_irq = irq;
>  	}
>  
> -	irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
> -				pdata ? pdata->dm_hs_phy_irq_index : -1);
> +	return 0;
> +}
> +
> +static int dwc3_qcom_setup_irq(struct platform_device *pdev)
> +{
> +	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
> +	const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
> +	int irq;
> +	int ret;
> +	int i;
> +
> +	irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
> +				pdata ? pdata->hs_phy_irq_index : -1);
>  	if (irq > 0) {
> -		irq_set_status_flags(irq, IRQ_NOAUTOEN);
> -		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
> -					qcom_dwc3_resume_irq,
> -					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
> -					"qcom_dwc3 DM_HS", qcom);
> -		if (ret) {
> -			dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
> +		ret = dwc3_qcom_prep_irq(qcom, "hs_phy_irq", "qcom_dwc3 HS",irq);
> +		if (ret)

It would be nice to have this refactored out in a separate commit.

>  			return ret;
> -		}
> -		qcom->dm_hs_phy_irq = irq;
> +		qcom->hs_phy_irq = irq;
>  	}
>  
> -	irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
> -				pdata ? pdata->ss_phy_irq_index : -1);
> -	if (irq > 0) {
> -		irq_set_status_flags(irq, IRQ_NOAUTOEN);
> -		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
> -					qcom_dwc3_resume_irq,
> -					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
> -					"qcom_dwc3 SS", qcom);
> -		if (ret) {
> -			dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
> +	for (i = 0; i < qcom->data->num_ports; i++) {
> +		ret = dwc3_get_port_irq(pdev, i);
> +		if (ret)
>  			return ret;
> -		}
> -		qcom->ss_phy_irq = irq;
>  	}
>  
>  	return 0;
> @@ -811,6 +905,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>  	platform_set_drvdata(pdev, qcom);
>  	qcom->dev = &pdev->dev;
>  
> +	qcom->data = of_device_get_match_data(qcom->dev);
> +
>  	if (has_acpi_companion(dev)) {
>  		qcom->acpi_pdata = acpi_device_get_match_data(dev);
>  		if (!qcom->acpi_pdata) {
> @@ -1023,8 +1119,15 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
>  };
>  
>  static const struct of_device_id dwc3_qcom_of_match[] = {
> -	{ .compatible = "qcom,dwc3" },
> -	{ }
> +	{
> +		.compatible = "qcom,dwc3",
> +		.data = &qcom_dwc3,
> +	},
> +	{
> +		.compatible = "qcom,sc8280xp-dwc3-mp",
> +		.data = &sx8280xp_qcom_dwc3,
> +	},

I would prefer that we don't add a separate compatible, but rather just
try to parse the interrupts for multiport and fall back to single port.

If/when we figure out how to peak into the dwc3 core, we could
potentially introduce a check to aid the developer.

Regards,
Bjorn

> +	{ },
>  };
>  MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
>  
> -- 
> 2.40.0
> 

Re: [PATCH v10 06/11] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver

[Krishna Kurapati PSSNV]

On 8/6/2023 10:41 AM, Bjorn Andersson wrote:
> On Fri, Jul 28, 2023 at 04:03:02AM +0530, Krishna Kurapati wrote:
>> Refactor setup_irq call to facilitate reading multiport IRQ's along
>> with non mulitport ones. For SA8295, there are 4-DP/4-DM and 2-SS
>> IRQ's. Check whether device is multiport capable or not and read all
>> interrupts for DP/DM/SS on each port accordingly.
>> +/*
>> + * Driver needs to read HS/DP_HS/DM_HS/SS IRQ's. Currently, for
>> + * SA8295 which supports mutliport, thre are 4 DP/ 4 DM/ 2 SS IRQ's
>> + * and 1 HS IRQ present. So avoid trying to read HS_PHY_IRQ for 4
>> + * ports of SA8295.
>> + */
> 
> The last part here is relevant information, but it doesn't seem to
> relate to this define.
> 
> Also, does all platforms have this configuration of interrupts?
> 
Hi Bjorn,

Yes, all targets have the same IRQ's. Just that MP one's have multiple 
IRQ's of each type. But hs-phy_irq is only one in SC8280 as well.

>> +#define MAX_PHY_IRQ	4
>> +
>> +enum dwc3_qcom_phy_irq_identifier {
>> +	HS_PHY_IRQ = 0,
>> +	DP_HS_PHY_IRQ,
>> +	DM_HS_PHY_IRQ,
>> +	SS_PHY_IRQ,
>>   };
> 
> This enum is unused.
> 
>>   
> [..]
>> +static int dwc3_get_acpi_index(const struct dwc3_acpi_pdata *pdata, int irq_index)
>> +{
>> +	int acpi_index = -1;
>> +
>> +	if (!pdata)
>> +		return -1;
>> +
>> +	if (irq_index == DP_HS_PHY_IRQ)
>> +		acpi_index = pdata->dp_hs_phy_irq_index;
>> +	else if (irq_index == DM_HS_PHY_IRQ)
>> +		acpi_index = pdata->dm_hs_phy_irq_index;
>> +	else if (irq_index == SS_PHY_IRQ)
>> +		acpi_index = pdata->ss_phy_irq_index;
> 
> It looks favourable to put these in an array, instead of having to pull
> them out of 4 different variables conditionally.
> 
Sure, will move them to an array to remove this if-else stuff.
>> +
>> +	return acpi_index;
>> +		} else {
>> +			if (i == DP_HS_PHY_IRQ) {
>> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"dp_hs_phy_%d", port_index + 1);
>> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"qcom_dwc3 DP_HS%d", port_index + 1);
>> +			} else if (i == DM_HS_PHY_IRQ) {
>> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"dm_hs_phy_%d", port_index + 1);
>> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"qcom_dwc3 DM_HS%d", port_index + 1);
>> +			} else if (i == SS_PHY_IRQ) {
>> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"ss_phy_%d", port_index + 1);
>> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"qcom_dwc3 SS%d", port_index + 1);
>> +			}
> 
> There is too much repetition in this for my liking.
Will try to put dp/dm/ss too in an array in dwc3_qcom structure and 
merge these 3 loops into '1'. But that would mean I need to add a global 
structure to avoid adding if else statements to do proper kasprintf 
stuff. If its fine to add a global array with all names and use them 
here, then it would be easy to merge the loops into one for loop. But if 
we are not supposed to add global array of names, then I would keep 
these 3 repetitive code blocks as is.
> 
>>   		}
>> -		qcom->hs_phy_irq = irq;
>> -	}
>>   
>> -	irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
>> -				pdata ? pdata->dp_hs_phy_irq_index : -1);
>> -	if (irq > 0) {
>> -		irq_set_status_flags(irq, IRQ_NOAUTOEN);
>> -		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
>> -					qcom_dwc3_resume_irq,
>> -					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
>> -					"qcom_dwc3 DP_HS", qcom);
>> -		if (ret) {
>> -			dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
>> -			return ret;
>> +		if (!dt_name || !disp_name)
>> +			return -ENOMEM;
>> +
>> +		acpi_index = !is_mp_supported ? dwc3_get_acpi_index(pdata, i) : -1;
>> +
>> +		irq = dwc3_qcom_get_irq(pdev, dt_name, acpi_index);
>> +		if (irq > 0) {
>> +			ret = dwc3_qcom_prep_irq(qcom, dt_name, disp_name, irq);
>> +			if (ret)
>> +				return ret;
>> +
>> +			if (i == DP_HS_PHY_IRQ)
>> +				qcom->dp_hs_phy_irq[port_index] = irq;
>> +			else if (i == DM_HS_PHY_IRQ)
>> +				qcom->dm_hs_phy_irq[port_index] = irq;
>> +			else if (i == SS_PHY_IRQ)
>> +				qcom->ss_phy_irq[port_index] = irq;
>>   		}
>> -		qcom->dp_hs_phy_irq = irq;
>>   	}
>>   
>> -	irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
>> -				pdata ? pdata->dm_hs_phy_irq_index : -1);
>> +	return 0;
>> +}
>> +
>> +static int dwc3_qcom_setup_irq(struct platform_device *pdev)
>> +{
>> +	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
>> +	const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
>> +	int irq;
>> +	int ret;
>> +	int i;
>> +
>> +	irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
>> +				pdata ? pdata->hs_phy_irq_index : -1);
>>   	if (irq > 0) {
>> -		irq_set_status_flags(irq, IRQ_NOAUTOEN);
>> -		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
>> -					qcom_dwc3_resume_irq,
>> -					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
>> -					"qcom_dwc3 DM_HS", qcom);
>> -		if (ret) {
>> -			dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
>> +		ret = dwc3_qcom_prep_irq(qcom, "hs_phy_irq", "qcom_dwc3 HS",irq);
>> +		if (ret)
> 
> It would be nice to have this refactored out in a separate commit.
> 
Sure, will add the prep irq in a seperate commit before we read the MP 
IRQ's.
>>   			return ret;
>> -		}
>> -		qcom->dm_hs_phy_irq = irq;
>> +		qcom->hs_phy_irq = irq;
>>   	}
>>   
>> -	irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
>> -				pdata ? pdata->ss_phy_irq_index : -1);
>> -	if (irq > 0) {
>> -		irq_set_status_flags(irq, IRQ_NOAUTOEN);
>> -		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
>> -					qcom_dwc3_resume_irq,
>> -					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
>> -					"qcom_dwc3 SS", qcom);
>> -		if (ret) {
>> -			dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
>> +	for (i = 0; i < qcom->data->num_ports; i++) {
>> +		ret = dwc3_get_port_irq(pdev, i);
>> +		if (ret)
>>   			return ret;
>> -		}
>> -		qcom->ss_phy_irq = irq;
>>   	}
>>   
>>   	return 0;
>> @@ -811,6 +905,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>>   	platform_set_drvdata(pdev, qcom);
>>   	qcom->dev = &pdev->dev;
>>   
>> +	qcom->data = of_device_get_match_data(qcom->dev);
>> +
>>   	if (has_acpi_companion(dev)) {
>>   		qcom->acpi_pdata = acpi_device_get_match_data(dev);
>>   		if (!qcom->acpi_pdata) {
>> @@ -1023,8 +1119,15 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
>>   };
>>   
>>   static const struct of_device_id dwc3_qcom_of_match[] = {
>> -	{ .compatible = "qcom,dwc3" },
>> -	{ }
>> +	{
>> +		.compatible = "qcom,dwc3",
>> +		.data = &qcom_dwc3,
>> +	},
>> +	{
>> +		.compatible = "qcom,sc8280xp-dwc3-mp",
>> +		.data = &sx8280xp_qcom_dwc3,
>> +	},
> 
> I would prefer that we don't add a separate compatible, but rather just
> try to parse the interrupts for multiport and fall back to single port.
> 
> If/when we figure out how to peak into the dwc3 core, we could
> potentially introduce a check to aid the developer.
> 

Only reason I chose this path is it is unabiguous. With this path, we 
don't need to worry about whether the user skipped any irq's in the DT 
or not. If we rely on the IRQ parsing from DT, then we might need to 
calculate effective port count while parsing the irq loop making it 
ambigous and prone to error I believe. I would like to keep this 
compatible as it and use this in the file wherever needed. And since 
peeking into dwc3-core before we call of_platform_populate is not 
possible and we need port_count, I kept a compatible here. I could move 
the setup_irq call to after completion of of_platform_populate, but 
still there is risk of dwc3 probe getting deferred or failing and we end 
up not being able to peek into dwc3.

Request you to reconsider and accept adding a compatible here.

Regards,
Krishna,

Re: [PATCH v10 06/11] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver

[Krishna Kurapati PSSNV]

  +
>> +enum dwc3_qcom_phy_irq_identifier {
>> +	HS_PHY_IRQ = 0,
>> +	DP_HS_PHY_IRQ,
>> +	DM_HS_PHY_IRQ,
>> +	SS_PHY_IRQ,
>>   };
> 
> This enum is unused.
> 

Hi Bjorn,

  I didn't use the enum directly, but used its members in the 
get_port_irq call below.

> [..]
>> +static int dwc3_get_acpi_index(const struct dwc3_acpi_pdata *pdata, int irq_index)
>> +{
>> +	int acpi_index = -1;
>> +
>> +	if (!pdata)
>> +		return -1;
>> +
>> +	if (irq_index == DP_HS_PHY_IRQ)
>> +		acpi_index = pdata->dp_hs_phy_irq_index;
>> +	else if (irq_index == DM_HS_PHY_IRQ)
>> +		acpi_index = pdata->dm_hs_phy_irq_index;
>> +	else if (irq_index == SS_PHY_IRQ)
>> +		acpi_index = pdata->ss_phy_irq_index;
> 
> It looks favourable to put these in an array, instead of having to pull
> them out of 4 different variables conditionally.
> 
>> +
>> +	return acpi_index;
>> +}
>> +
>> +static int dwc3_get_port_irq(struct platform_device *pdev, u8 port_index)
>> +{
>> +	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
>> +	bool is_mp_supported = (qcom->data->num_ports > 1) ? true : false;
>> +	const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
>> +	char *disp_name;
>> +	int acpi_index;
>> +	char *dt_name;
>> +	int ret;
>> +	int irq;
>> +	int i;
>> +
>> +	/*
>> +	 * We need to read only DP/DM/SS IRQ's here.
>> +	 * So loop over from 1->3 and accordingly modify respective phy_irq[].
>> +	 */
>> +	for (i = 1; i < MAX_PHY_IRQ; i++) {
>> +
>> +		if (!is_mp_supported && (port_index == 0)) {
>> +			if (i == DP_HS_PHY_IRQ) {
>> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"dp_hs_phy_irq");
>> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"qcom_dwc3 DP_HS");
>> +			} else if (i == DM_HS_PHY_IRQ) {
>> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"dm_hs_phy_irq");
>> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"qcom_dwc3 DM_HS");
>> +			} else if (i == SS_PHY_IRQ) {
>> +				dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"ss_phy_irq");
>> +				disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>> +					"qcom_dwc3 SS");
Bjorn, Konrad,

If we are to remove this repetitive loops, we might need to make a 2D 
array for all of Dp/Dm/Ss interrutps and make a global array of names to 
be used for irq lookup and use them to reduce the if-else-if stuff here. 
If that is fine, I can make those changes, else I would like to stick to 
this approach for now because if we don't add the global array of names, 
prepping them seperately for dp/dm/ss would again lead us to making 
if-else loops like above.

Please let me know your thoughts on this.

Regards,
Krishna,

Re: [PATCH v10 06/11] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver

[Konrad Dybcio]

On 8.08.2023 10:32, Krishna Kurapati PSSNV wrote:
>  +
>>> +enum dwc3_qcom_phy_irq_identifier {
>>> +    HS_PHY_IRQ = 0,
>>> +    DP_HS_PHY_IRQ,
>>> +    DM_HS_PHY_IRQ,
>>> +    SS_PHY_IRQ,
>>>   };
>>
>> This enum is unused.
>>
> 
> Hi Bjorn,
> 
>  I didn't use the enum directly, but used its members in the get_port_irq call below.
> 
>> [..]
>>> +static int dwc3_get_acpi_index(const struct dwc3_acpi_pdata *pdata, int irq_index)
>>> +{
>>> +    int acpi_index = -1;
>>> +
>>> +    if (!pdata)
>>> +        return -1;
>>> +
>>> +    if (irq_index == DP_HS_PHY_IRQ)
>>> +        acpi_index = pdata->dp_hs_phy_irq_index;
>>> +    else if (irq_index == DM_HS_PHY_IRQ)
>>> +        acpi_index = pdata->dm_hs_phy_irq_index;
>>> +    else if (irq_index == SS_PHY_IRQ)
>>> +        acpi_index = pdata->ss_phy_irq_index;
>>
>> It looks favourable to put these in an array, instead of having to pull
>> them out of 4 different variables conditionally.
>>
>>> +
>>> +    return acpi_index;
>>> +}
>>> +
>>> +static int dwc3_get_port_irq(struct platform_device *pdev, u8 port_index)
>>> +{
>>> +    struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
>>> +    bool is_mp_supported = (qcom->data->num_ports > 1) ? true : false;
>>> +    const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
>>> +    char *disp_name;
>>> +    int acpi_index;
>>> +    char *dt_name;
>>> +    int ret;
>>> +    int irq;
>>> +    int i;
>>> +
>>> +    /*
>>> +     * We need to read only DP/DM/SS IRQ's here.
>>> +     * So loop over from 1->3 and accordingly modify respective phy_irq[].
>>> +     */
>>> +    for (i = 1; i < MAX_PHY_IRQ; i++) {
>>> +
>>> +        if (!is_mp_supported && (port_index == 0)) {
>>> +            if (i == DP_HS_PHY_IRQ) {
>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>> +                    "dp_hs_phy_irq");
>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>> +                    "qcom_dwc3 DP_HS");
>>> +            } else if (i == DM_HS_PHY_IRQ) {
>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>> +                    "dm_hs_phy_irq");
>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>> +                    "qcom_dwc3 DM_HS");
>>> +            } else if (i == SS_PHY_IRQ) {
>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>> +                    "ss_phy_irq");
>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>> +                    "qcom_dwc3 SS");
> Bjorn, Konrad,
> 
> If we are to remove this repetitive loops, we might need to make a 2D array for all of Dp/Dm/Ss interrutps and make a global array of names to be used for irq lookup and use them to reduce the if-else-if stuff here. If that is fine, I can make those changes, else I would like to stick to this approach for now because if we don't add the global array of names, prepping them seperately for dp/dm/ss would again lead us to making if-else loops like above.
> 
> Please let me know your thoughts on this.
Can we not just reuse the associated interrupt-names from the devicetree
if present?

Konrad

Re: [PATCH v10 06/11] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver

[Krishna Kurapati PSSNV]

On 8/8/2023 5:20 PM, Konrad Dybcio wrote:
> On 8.08.2023 10:32, Krishna Kurapati PSSNV wrote:
>>   +
>>>> +enum dwc3_qcom_phy_irq_identifier {
>>>> +    HS_PHY_IRQ = 0,
>>>> +    DP_HS_PHY_IRQ,
>>>> +    DM_HS_PHY_IRQ,
>>>> +    SS_PHY_IRQ,
>>>>    };
>>>
>>> This enum is unused.
>>>
>>
>> Hi Bjorn,
>>
>>   I didn't use the enum directly, but used its members in the get_port_irq call below.
>>
>>> [..]
>>>> +static int dwc3_get_acpi_index(const struct dwc3_acpi_pdata *pdata, int irq_index)
>>>> +{
>>>> +    int acpi_index = -1;
>>>> +
>>>> +    if (!pdata)
>>>> +        return -1;
>>>> +
>>>> +    if (irq_index == DP_HS_PHY_IRQ)
>>>> +        acpi_index = pdata->dp_hs_phy_irq_index;
>>>> +    else if (irq_index == DM_HS_PHY_IRQ)
>>>> +        acpi_index = pdata->dm_hs_phy_irq_index;
>>>> +    else if (irq_index == SS_PHY_IRQ)
>>>> +        acpi_index = pdata->ss_phy_irq_index;
>>>
>>> It looks favourable to put these in an array, instead of having to pull
>>> them out of 4 different variables conditionally.
>>>
>>>> +
>>>> +    return acpi_index;
>>>> +}
>>>> +
>>>> +static int dwc3_get_port_irq(struct platform_device *pdev, u8 port_index)
>>>> +{
>>>> +    struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
>>>> +    bool is_mp_supported = (qcom->data->num_ports > 1) ? true : false;
>>>> +    const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
>>>> +    char *disp_name;
>>>> +    int acpi_index;
>>>> +    char *dt_name;
>>>> +    int ret;
>>>> +    int irq;
>>>> +    int i;
>>>> +
>>>> +    /*
>>>> +     * We need to read only DP/DM/SS IRQ's here.
>>>> +     * So loop over from 1->3 and accordingly modify respective phy_irq[].
>>>> +     */
>>>> +    for (i = 1; i < MAX_PHY_IRQ; i++) {
>>>> +
>>>> +        if (!is_mp_supported && (port_index == 0)) {
>>>> +            if (i == DP_HS_PHY_IRQ) {
>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>> +                    "dp_hs_phy_irq");
>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>> +                    "qcom_dwc3 DP_HS");
>>>> +            } else if (i == DM_HS_PHY_IRQ) {
>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>> +                    "dm_hs_phy_irq");
>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>> +                    "qcom_dwc3 DM_HS");
>>>> +            } else if (i == SS_PHY_IRQ) {
>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>> +                    "ss_phy_irq");
>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>> +                    "qcom_dwc3 SS");
>> Bjorn, Konrad,
>>
>> If we are to remove this repetitive loops, we might need to make a 2D array for all of Dp/Dm/Ss interrutps and make a global array of names to be used for irq lookup and use them to reduce the if-else-if stuff here. If that is fine, I can make those changes, else I would like to stick to this approach for now because if we don't add the global array of names, prepping them seperately for dp/dm/ss would again lead us to making if-else loops like above.
>>
>> Please let me know your thoughts on this.
> Can we not just reuse the associated interrupt-names from the devicetree
> if present?
> 
Hi Konrad,

  Thanks for the comments but one more confirmation.
We can read the interrupts from DT but I believe the compatible would 
still need to stay. We need the num_ports information not just for 
registering interrupts but for modifying the pwr_event_irq registers 
during suspend/resume. If we rely on the interrupts to find the number 
of ports, the user is free to remove any IRQ and we might end up in a 
situation where glue and core are not having same view of how many 
number of ports present. So I believe its best to keep the compatible 
and get num_ports info from there and rely on reading interrupt-names to 
get interrupts cleanly. Can you let me know your view on the same.

Regards,
Krishna,

Re: [PATCH v10 06/11] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver

[Konrad Dybcio]

On 9.08.2023 08:06, Krishna Kurapati PSSNV wrote:
> 
> 
> On 8/8/2023 5:20 PM, Konrad Dybcio wrote:
>> On 8.08.2023 10:32, Krishna Kurapati PSSNV wrote:
>>>   +
>>>>> +enum dwc3_qcom_phy_irq_identifier {
>>>>> +    HS_PHY_IRQ = 0,
>>>>> +    DP_HS_PHY_IRQ,
>>>>> +    DM_HS_PHY_IRQ,
>>>>> +    SS_PHY_IRQ,
>>>>>    };
>>>>
>>>> This enum is unused.
>>>>
>>>
>>> Hi Bjorn,
>>>
>>>   I didn't use the enum directly, but used its members in the get_port_irq call below.
>>>
>>>> [..]
>>>>> +static int dwc3_get_acpi_index(const struct dwc3_acpi_pdata *pdata, int irq_index)
>>>>> +{
>>>>> +    int acpi_index = -1;
>>>>> +
>>>>> +    if (!pdata)
>>>>> +        return -1;
>>>>> +
>>>>> +    if (irq_index == DP_HS_PHY_IRQ)
>>>>> +        acpi_index = pdata->dp_hs_phy_irq_index;
>>>>> +    else if (irq_index == DM_HS_PHY_IRQ)
>>>>> +        acpi_index = pdata->dm_hs_phy_irq_index;
>>>>> +    else if (irq_index == SS_PHY_IRQ)
>>>>> +        acpi_index = pdata->ss_phy_irq_index;
>>>>
>>>> It looks favourable to put these in an array, instead of having to pull
>>>> them out of 4 different variables conditionally.
>>>>
>>>>> +
>>>>> +    return acpi_index;
>>>>> +}
>>>>> +
>>>>> +static int dwc3_get_port_irq(struct platform_device *pdev, u8 port_index)
>>>>> +{
>>>>> +    struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
>>>>> +    bool is_mp_supported = (qcom->data->num_ports > 1) ? true : false;
>>>>> +    const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
>>>>> +    char *disp_name;
>>>>> +    int acpi_index;
>>>>> +    char *dt_name;
>>>>> +    int ret;
>>>>> +    int irq;
>>>>> +    int i;
>>>>> +
>>>>> +    /*
>>>>> +     * We need to read only DP/DM/SS IRQ's here.
>>>>> +     * So loop over from 1->3 and accordingly modify respective phy_irq[].
>>>>> +     */
>>>>> +    for (i = 1; i < MAX_PHY_IRQ; i++) {
>>>>> +
>>>>> +        if (!is_mp_supported && (port_index == 0)) {
>>>>> +            if (i == DP_HS_PHY_IRQ) {
>>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>> +                    "dp_hs_phy_irq");
>>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>> +                    "qcom_dwc3 DP_HS");
>>>>> +            } else if (i == DM_HS_PHY_IRQ) {
>>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>> +                    "dm_hs_phy_irq");
>>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>> +                    "qcom_dwc3 DM_HS");
>>>>> +            } else if (i == SS_PHY_IRQ) {
>>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>> +                    "ss_phy_irq");
>>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>> +                    "qcom_dwc3 SS");
>>> Bjorn, Konrad,
>>>
>>> If we are to remove this repetitive loops, we might need to make a 2D array for all of Dp/Dm/Ss interrutps and make a global array of names to be used for irq lookup and use them to reduce the if-else-if stuff here. If that is fine, I can make those changes, else I would like to stick to this approach for now because if we don't add the global array of names, prepping them seperately for dp/dm/ss would again lead us to making if-else loops like above.
>>>
>>> Please let me know your thoughts on this.
>> Can we not just reuse the associated interrupt-names from the devicetree
>> if present?
>>
> Hi Konrad,
> 
>  Thanks for the comments but one more confirmation.
> We can read the interrupts from DT but I believe the compatible would still need to stay. We need the num_ports information not just for registering interrupts but for modifying the pwr_event_irq registers during suspend/resume. If we rely on the interrupts to find the number of ports, the user is free to remove any IRQ and we might end up in a situation where glue and core are not having same view of how many number of ports present. So I believe its best to keep the compatible and get num_ports info from there and rely on reading interrupt-names to get interrupts cleanly. Can you let me know your view on the same.
So is "is it okay to add SoC-specific compatibles and add the port number in
match data" what you're asking?

If so, that doesn't seem right.

The user should not "feel free to remove any IRQ", modifying the devicetree to
depict a subset of the hardware is not something we want to support. The driver
has to work with the "full" description in accordance with the bindings.

Konrad

Re: [PATCH v10 06/11] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver

[Krishna Kurapati PSSNV]

On 8/11/2023 10:35 PM, Konrad Dybcio wrote:
>>>>>> +static int dwc3_get_port_irq(struct platform_device *pdev, u8 port_index)
>>>>>> +{
>>>>>> +    struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
>>>>>> +    bool is_mp_supported = (qcom->data->num_ports > 1) ? true : false;
>>>>>> +    const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
>>>>>> +    char *disp_name;
>>>>>> +    int acpi_index;
>>>>>> +    char *dt_name;
>>>>>> +    int ret;
>>>>>> +    int irq;
>>>>>> +    int i;
>>>>>> +
>>>>>> +    /*
>>>>>> +     * We need to read only DP/DM/SS IRQ's here.
>>>>>> +     * So loop over from 1->3 and accordingly modify respective phy_irq[].
>>>>>> +     */
>>>>>> +    for (i = 1; i < MAX_PHY_IRQ; i++) {
>>>>>> +
>>>>>> +        if (!is_mp_supported && (port_index == 0)) {
>>>>>> +            if (i == DP_HS_PHY_IRQ) {
>>>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "dp_hs_phy_irq");
>>>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "qcom_dwc3 DP_HS");
>>>>>> +            } else if (i == DM_HS_PHY_IRQ) {
>>>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "dm_hs_phy_irq");
>>>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "qcom_dwc3 DM_HS");
>>>>>> +            } else if (i == SS_PHY_IRQ) {
>>>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "ss_phy_irq");
>>>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "qcom_dwc3 SS");
>>>> Bjorn, Konrad,
>>>>
>>>> If we are to remove this repetitive loops, we might need to make a 2D array for all of Dp/Dm/Ss interrutps and make a global array of names to be used for irq lookup and use them to reduce the if-else-if stuff here. If that is fine, I can make those changes, else I would like to stick to this approach for now because if we don't add the global array of names, prepping them seperately for dp/dm/ss would again lead us to making if-else loops like above.
>>>>
>>>> Please let me know your thoughts on this.
>>> Can we not just reuse the associated interrupt-names from the devicetree
>>> if present?
>>>
>> Hi Konrad,
>>
>>   Thanks for the comments but one more confirmation.
>> We can read the interrupts from DT but I believe the compatible would still need to stay. We need the num_ports information not just for registering interrupts but for modifying the pwr_event_irq registers during suspend/resume. If we rely on the interrupts to find the number of ports, the user is free to remove any IRQ and we might end up in a situation where glue and core are not having same view of how many number of ports present. So I believe its best to keep the compatible and get num_ports info from there and rely on reading interrupt-names to get interrupts cleanly. Can you let me know your view on the same.
> So is "is it okay to add SoC-specific compatibles and add the port number in
> match data" what you're asking?
> 
> If so, that doesn't seem right.
> 
> The user should not "feel free to remove any IRQ", modifying the devicetree to
> depict a subset of the hardware is not something we want to support. The driver
> has to work with the "full" description in accordance with the bindings.
> 

Hi Konrad,

Thanks for the review.

While I agree with you that we must not skip any hw specifics in DT, 
there is nothing stopping the user from doing so right ?

And whatever be the case, we must be a fool-proof and fail safe system 
able to handle all such situations. While we can read interrupt IRQ 
prefixes to get port count in one way or other, adding a compatible 
would be the least ambiguous path. Is there any other concern you see in 
adding a compatible ? I might be missing something because even Bjorn's 
suggestion too was to try and avoid a new compatible addition and to add 
it only if we have no other way of reliably reading the port count 
(which I believe would be an issue if we need to rely on interrupt name 
reading).

Regards,
Krishna,

Re: [PATCH v10 06/11] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver

[Krishna Kurapati PSSNV]

[-- Attachment #1: Type: text/plain, Size: 1628 bytes --]



On 8/12/2023 2:14 PM, Krishna Kurapati PSSNV wrote:
>> So is "is it okay to add SoC-specific compatibles and add the port 
>> number in
>> match data" what you're asking?
>>
>> If so, that doesn't seem right.
>>
>> The user should not "feel free to remove any IRQ", modifying the 
>> devicetree to
>> depict a subset of the hardware is not something we want to support. 
>> The driver
>> has to work with the "full" description in accordance with the bindings.
>>
> 
> Hi Konrad,
> 
> Thanks for the review.
> 
> While I agree with you that we must not skip any hw specifics in DT, 
> there is nothing stopping the user from doing so right ?
> 
> And whatever be the case, we must be a fool-proof and fail safe system 
> able to handle all such situations. While we can read interrupt IRQ 
> prefixes to get port count in one way or other, adding a compatible 
> would be the least ambiguous path. Is there any other concern you see in 
> adding a compatible ? I might be missing something because even Bjorn's 
> suggestion too was to try and avoid a new compatible addition and to add 
> it only if we have no other way of reliably reading the port count 
> (which I believe would be an issue if we need to rely on interrupt name 
> reading).
> 
Hi Konrad. Came up with an implementation of reading the interrupt names 
and parsing for port count and added them as attachments. I still feel 
adding a compatible is a better option. Let me know which one is the 
better path. The one in v10, or something similar to the attached patch. 
(I tested it on sc7280/sc8280 and interrupts are registered properly)

Regards,
Krishna,

[-- Attachment #2: 0001-usb-dwc3-qcom-Add-helper-function-to-request-threade.patch --]
[-- Type: text/plain, Size: 3716 bytes --]

From 60d5d0a678b864756a18ff17337ecddc257c9b44 Mon Sep 17 00:00:00 2001
From: Krishna Kurapati <quic_kriskura@quicinc.com>
Date: Tue, 22 Aug 2023 09:42:59 +0530
Subject: [PATCH 1/2] usb: dwc3: qcom: Add helper function to request threaded
 IRQ

Cleanup setup irq call by implementing a new prep_irq helper function
and using it to request threaded IRQ's.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Change-Id: Ic136d1cdbf72602a0b8b0bf7ec4d6a7a723431de
---
 drivers/usb/dwc3/dwc3-qcom.c | 63 +++++++++++++++++-------------------
 1 file changed, 30 insertions(+), 33 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 3de43df6bbe8..f14ddc9c541d 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -535,6 +535,24 @@ static int dwc3_qcom_get_irq(struct platform_device *pdev,
 	return ret;
 }
 
+static int dwc3_qcom_prep_irq(struct dwc3_qcom *qcom, char *irq_name,
+				char *disp_name, int irq)
+{
+	int ret;
+
+	/* Keep wakeup interrupts disabled until suspend */
+	irq_set_status_flags(irq, IRQ_NOAUTOEN);
+	ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
+					qcom_dwc3_resume_irq,
+					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+					disp_name, qcom);
+
+	if (ret)
+		dev_err(qcom->dev, "%s failed: %d\n", irq_name, ret);
+
+	return ret;
+}
+
 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
 {
 	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
@@ -545,61 +563,40 @@ static int dwc3_qcom_setup_irq(struct platform_device *pdev)
 	irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
 				pdata ? pdata->hs_phy_irq_index : -1);
 	if (irq > 0) {
-		/* Keep wakeup interrupts disabled until suspend */
-		irq_set_status_flags(irq, IRQ_NOAUTOEN);
-		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
-					qcom_dwc3_resume_irq,
-					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
-					"qcom_dwc3 HS", qcom);
-		if (ret) {
-			dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
+		ret = dwc3_qcom_prep_irq(qcom, "hs_phy_irq",
+						"qcom_dwc3 HS", irq);
+		if (ret)
 			return ret;
-		}
 		qcom->hs_phy_irq = irq;
 	}
 
 	irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
 				pdata ? pdata->dp_hs_phy_irq_index : -1);
 	if (irq > 0) {
-		irq_set_status_flags(irq, IRQ_NOAUTOEN);
-		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
-					qcom_dwc3_resume_irq,
-					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
-					"qcom_dwc3 DP_HS", qcom);
-		if (ret) {
-			dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
+		ret = dwc3_qcom_prep_irq(qcom, "dp_hs_phy_irq",
+						"qcom_dwc3 DP_HS", irq);
+		if (ret)
 			return ret;
-		}
 		qcom->dp_hs_phy_irq = irq;
 	}
 
 	irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
 				pdata ? pdata->dm_hs_phy_irq_index : -1);
 	if (irq > 0) {
-		irq_set_status_flags(irq, IRQ_NOAUTOEN);
-		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
-					qcom_dwc3_resume_irq,
-					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
-					"qcom_dwc3 DM_HS", qcom);
-		if (ret) {
-			dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
+		ret = dwc3_qcom_prep_irq(qcom, "dm_hs_phy_irq",
+						"qcom_dwc3 DM_HS", irq);
+		if (ret)
 			return ret;
-		}
 		qcom->dm_hs_phy_irq = irq;
 	}
 
 	irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
 				pdata ? pdata->ss_phy_irq_index : -1);
 	if (irq > 0) {
-		irq_set_status_flags(irq, IRQ_NOAUTOEN);
-		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
-					qcom_dwc3_resume_irq,
-					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
-					"qcom_dwc3 SS", qcom);
-		if (ret) {
-			dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
+		ret = dwc3_qcom_prep_irq(qcom, "ss_phy_irq",
+						"qcom_dwc3 SS", irq);
+		if (ret)
 			return ret;
-		}
 		qcom->ss_phy_irq = irq;
 	}
 
-- 
2.40.0


[-- Attachment #3: 0002-usb-dwc3-qcom-Read-multiport-interrupts.patch --]
[-- Type: text/plain, Size: 8825 bytes --]

From 418ac10e88c53f67e947f754aebd3bd97ea67e8a Mon Sep 17 00:00:00 2001
From: Krishna Kurapati <quic_kriskura@quicinc.com>
Date: Tue, 22 Aug 2023 15:25:12 +0530
Subject: [PATCH 2/2] usb: dwc3: qcom: Read multiport interrupts

Read multiport interrupts in qcom driver.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Change-Id: Ic2bf8cad70c1478c79eb7e9d3dc5d9082c5bb1f9
---
 drivers/usb/dwc3/dwc3-qcom.c | 193 ++++++++++++++++++++++++-----------
 1 file changed, 134 insertions(+), 59 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index f14ddc9c541d..a0ba71ea9541 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -53,14 +53,19 @@
 #define APPS_USB_AVG_BW 0
 #define APPS_USB_PEAK_BW MBps_to_icc(40)
 
+#define NUM_PHY_IRQ	4
+
+#define DP_HS_PHY_IRQ_INDEX	0
+#define DM_HS_PHY_IRQ_INDEX	1
+#define SS_PHY_IRQ_INDEX	2
+#define HS_PHY_IRQ_INDEX	3
+
 struct dwc3_acpi_pdata {
 	u32			qscratch_base_offset;
 	u32			qscratch_base_size;
 	u32			dwc3_core_base_size;
+	int			phy_irq_index[NUM_PHY_IRQ - 1];
 	int			hs_phy_irq_index;
-	int			dp_hs_phy_irq_index;
-	int			dm_hs_phy_irq_index;
-	int			ss_phy_irq_index;
 	bool			is_urs;
 };
 
@@ -73,10 +78,8 @@ struct dwc3_qcom {
 	int			num_clocks;
 	struct reset_control	*resets;
 
-	int			hs_phy_irq;
-	int			dp_hs_phy_irq;
-	int			dm_hs_phy_irq;
-	int			ss_phy_irq;
+	int			phy_irq[NUM_PHY_IRQ - 1][DWC3_MAX_PORTS];
+	int 			hs_phy_irq;
 	enum usb_device_speed	usb2_speed;
 
 	struct extcon_dev	*edev;
@@ -91,6 +94,8 @@ struct dwc3_qcom {
 	bool			pm_suspended;
 	struct icc_path		*icc_path_ddr;
 	struct icc_path		*icc_path_apps;
+
+	int			num_ports;
 };
 
 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
@@ -375,16 +380,16 @@ static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
 	dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
 
 	if (qcom->usb2_speed == USB_SPEED_LOW) {
-		dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
+		dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0]);
 	} else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
 			(qcom->usb2_speed == USB_SPEED_FULL)) {
-		dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
+		dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0]);
 	} else {
-		dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
-		dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
+		dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0]);
+		dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0]);
 	}
 
-	dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
+	dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[SS_PHY_IRQ_INDEX][0]);
 }
 
 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
@@ -401,20 +406,20 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
 	 */
 
 	if (qcom->usb2_speed == USB_SPEED_LOW) {
-		dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
+		dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0],
 						IRQ_TYPE_EDGE_FALLING);
 	} else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
 			(qcom->usb2_speed == USB_SPEED_FULL)) {
-		dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
+		dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0],
 						IRQ_TYPE_EDGE_FALLING);
 	} else {
-		dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
+		dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0],
 						IRQ_TYPE_EDGE_RISING);
-		dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
+		dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0],
 						IRQ_TYPE_EDGE_RISING);
 	}
 
-	dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
+	dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[SS_PHY_IRQ_INDEX][0], 0);
 }
 
 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
@@ -553,51 +558,125 @@ static int dwc3_qcom_prep_irq(struct dwc3_qcom *qcom, char *irq_name,
 	return ret;
 }
 
+static int dwc3_qcom_get_irq_index(const char *irq_name)
+{
+	/*
+	 * If we are reading IRQ not supported by the driver
+	 * like pwr_event_irq, then return -1 indicating the next
+	 * helper function to skip processing IRQ name further.
+	 */
+	int irq_index = -1;
+
+	if (strncmp(irq_name, "dp_hs_phy", 9) == 0)
+		irq_index = DP_HS_PHY_IRQ_INDEX;
+	else if(strncmp(irq_name, "dm_hs_phy", 9) == 0)
+		irq_index = DM_HS_PHY_IRQ_INDEX;
+	else if(strncmp(irq_name, "ss_phy", 6) == 0)
+		irq_index = SS_PHY_IRQ_INDEX;
+	else if(strncmp(irq_name, "hs_phy", 6) == 0)
+		irq_index = HS_PHY_IRQ_INDEX;
+
+	return irq_index;
+}
+
+static int dwc3_qcom_get_port_index(const char *irq_name, int irq_index)
+{
+	int port_index = -1;
+
+	switch (irq_index) {
+		case DP_HS_PHY_IRQ_INDEX:
+			if (strcmp(irq_name, "dp_hs_phy_irq") == 0)
+				port_index = 1;
+			else
+				sscanf(irq_name, "dp_hs_phy_%d", &port_index);
+			break;
+
+		case DM_HS_PHY_IRQ_INDEX:
+			if (strcmp(irq_name, "dm_hs_phy_irq") == 0)
+				port_index = 1;
+			else
+				sscanf(irq_name, "dm_hs_phy_%d", &port_index);
+			break;
+
+		case SS_PHY_IRQ_INDEX:
+			if (strcmp(irq_name, "ss_phy_irq") == 0)
+				port_index = 1;
+			else
+				sscanf(irq_name, "ss_phy_%d", &port_index);
+			break;
+
+		case HS_PHY_IRQ_INDEX:
+			port_index = 1;
+			break;
+	}
+
+done:
+	return port_index;
+}
+
+static int dwc3_qcom_get_acpi_index(struct dwc3_qcom *qcom, int irq_index,
+					int port_index)
+{
+	const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
+	int acpi_index = -1;
+
+	if ((pdata == NULL) || (port_index != 1))
+		goto done;
+
+	if (irq_index == HS_PHY_IRQ_INDEX)
+		acpi_index = pdata->hs_phy_irq_index;
+	else if (port_index != -1)
+		acpi_index = pdata->phy_irq_index[irq_index];
+
+done:
+	return acpi_index;
+}
+
 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
 {
 	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
-	const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
+	struct device_node *np = pdev->dev.of_node;
+	const char **irq_names;
+	int port_index;
+	int acpi_index;
+	int irq_count;
+	int irq_index;
 	int irq;
 	int ret;
+	int i;
 
-	irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
-				pdata ? pdata->hs_phy_irq_index : -1);
-	if (irq > 0) {
-		ret = dwc3_qcom_prep_irq(qcom, "hs_phy_irq",
-						"qcom_dwc3 HS", irq);
-		if (ret)
-			return ret;
-		qcom->hs_phy_irq = irq;
-	}
+	irq_count = of_property_count_strings(np, "interrupt-names");
+	irq_names = devm_kzalloc(&pdev->dev, sizeof(*irq_names) * irq_count, GFP_KERNEL);
+	if (!irq_names)
+		return -ENOMEM;
 
-	irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
-				pdata ? pdata->dp_hs_phy_irq_index : -1);
-	if (irq > 0) {
-		ret = dwc3_qcom_prep_irq(qcom, "dp_hs_phy_irq",
-						"qcom_dwc3 DP_HS", irq);
-		if (ret)
-			return ret;
-		qcom->dp_hs_phy_irq = irq;
-	}
+	ret = of_property_read_string_array(np, "interrupt-names",
+						irq_names, irq_count);
+	for (i = 0; i < irq_count; i++) {
+		irq_index = dwc3_qcom_get_irq_index(irq_names[i]);
+		if (irq_index == -1) {
+			dev_dbg(&pdev->dev, "IRQ not handled");
+			continue;
+		}
 
-	irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
-				pdata ? pdata->dm_hs_phy_irq_index : -1);
-	if (irq > 0) {
-		ret = dwc3_qcom_prep_irq(qcom, "dm_hs_phy_irq",
-						"qcom_dwc3 DM_HS", irq);
-		if (ret)
-			return ret;
-		qcom->dm_hs_phy_irq = irq;
-	}
+		port_index = dwc3_qcom_get_port_index(irq_names[i], irq_index);
+		acpi_index = dwc3_qcom_get_acpi_index(qcom, irq_index, port_index);
 
-	irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
-				pdata ? pdata->ss_phy_irq_index : -1);
-	if (irq > 0) {
-		ret = dwc3_qcom_prep_irq(qcom, "ss_phy_irq",
-						"qcom_dwc3 SS", irq);
-		if (ret)
-			return ret;
-		qcom->ss_phy_irq = irq;
+		irq = dwc3_qcom_get_irq(pdev, irq_names[i], acpi_index);
+		if (irq > 0) {
+			ret = dwc3_qcom_prep_irq(qcom, irq_names[i],
+							irq_names[i], irq);
+			if (ret)
+				return ret;
+
+			if (irq_index == HS_PHY_IRQ_INDEX)
+				qcom->hs_phy_irq = irq;
+			else
+				qcom->phy_irq[irq_index][port_index-1] = irq;
+
+			if (qcom->num_ports < port_index)
+				qcom->num_ports = port_index;
+		}
 	}
 
 	return 0;
@@ -1030,20 +1109,16 @@ static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
 	.qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
 	.qscratch_base_size = SDM845_QSCRATCH_SIZE,
 	.dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
+	.phy_irq_index = {4, 3, 2},
 	.hs_phy_irq_index = 1,
-	.dp_hs_phy_irq_index = 4,
-	.dm_hs_phy_irq_index = 3,
-	.ss_phy_irq_index = 2
 };
 
 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
 	.qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
 	.qscratch_base_size = SDM845_QSCRATCH_SIZE,
 	.dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
+	.phy_irq_index = {4, 3, 2},
 	.hs_phy_irq_index = 1,
-	.dp_hs_phy_irq_index = 4,
-	.dm_hs_phy_irq_index = 3,
-	.ss_phy_irq_index = 2,
 	.is_urs = true,
 };
 
-- 
2.40.0

Re: [PATCH v10 06/11] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver

[Krishna Kurapati PSSNV]

On 8/11/2023 10:35 PM, Konrad Dybcio wrote:
>>>>>> +
>>>>>> +static int dwc3_get_port_irq(struct platform_device *pdev, u8 port_index)
>>>>>> +{
>>>>>> +    struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
>>>>>> +    bool is_mp_supported = (qcom->data->num_ports > 1) ? true : false;
>>>>>> +    const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
>>>>>> +    char *disp_name;
>>>>>> +    int acpi_index;
>>>>>> +    char *dt_name;
>>>>>> +    int ret;
>>>>>> +    int irq;
>>>>>> +    int i;
>>>>>> +
>>>>>> +    /*
>>>>>> +     * We need to read only DP/DM/SS IRQ's here.
>>>>>> +     * So loop over from 1->3 and accordingly modify respective phy_irq[].
>>>>>> +     */
>>>>>> +    for (i = 1; i < MAX_PHY_IRQ; i++) {
>>>>>> +
>>>>>> +        if (!is_mp_supported && (port_index == 0)) {
>>>>>> +            if (i == DP_HS_PHY_IRQ) {
>>>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "dp_hs_phy_irq");
>>>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "qcom_dwc3 DP_HS");
>>>>>> +            } else if (i == DM_HS_PHY_IRQ) {
>>>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "dm_hs_phy_irq");
>>>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "qcom_dwc3 DM_HS");
>>>>>> +            } else if (i == SS_PHY_IRQ) {
>>>>>> +                dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "ss_phy_irq");
>>>>>> +                disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
>>>>>> +                    "qcom_dwc3 SS");
>>>> Bjorn, Konrad,
>>>>
>>>> If we are to remove this repetitive loops, we might need to make a 2D array for all of Dp/Dm/Ss interrutps and make a global array of names to be used for irq lookup and use them to reduce the if-else-if stuff here. If that is fine, I can make those changes, else I would like to stick to this approach for now because if we don't add the global array of names, prepping them seperately for dp/dm/ss would again lead us to making if-else loops like above.
>>>>
>>>> Please let me know your thoughts on this.
>>> Can we not just reuse the associated interrupt-names from the devicetree
>>> if present?
>>>
>> Hi Konrad,
>>
>>   Thanks for the comments but one more confirmation.
>> We can read the interrupts from DT but I believe the compatible would still need to stay. We need the num_ports information not just for registering interrupts but for modifying the pwr_event_irq registers during suspend/resume. If we rely on the interrupts to find the number of ports, the user is free to remove any IRQ and we might end up in a situation where glue and core are not having same view of how many number of ports present. So I believe its best to keep the compatible and get num_ports info from there and rely on reading interrupt-names to get interrupts cleanly. Can you let me know your view on the same.
> So is "is it okay to add SoC-specific compatibles and add the port number in
> match data" what you're asking?
> 
> If so, that doesn't seem right.
> 
> The user should not "feel free to remove any IRQ", modifying the devicetree to
> depict a subset of the hardware is not something we want to support. The driver
> has to work with the "full" description in accordance with the bindings.
> 

Hi Konrad, Johan,

Thanks for the suggestions / review comments and taking the time out for 
reviewing them. Pushed v11 implementing the above suggestion of 
identifying port_count by reading through the interrupt-names. Please 
help let know your review on the same.

Regards,
Krishna,