From: Zenghui Yu <yuzenghui@huawei.com>
To: Marc Zyngier <maz@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <kvm@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jason Cooper <jason@lakedaemon.net>,
Robert Richter <rrichter@marvell.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
Eric Auger <eric.auger@redhat.com>,
"James Morse" <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: Re: [PATCH v5 03/23] irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access
Date: Thu, 12 Mar 2020 14:56:56 +0800 [thread overview]
Message-ID: <b2c9b596-29b9-d785-3a60-9814d1c35655@huawei.com> (raw)
In-Reply-To: <20200304203330.4967-4-maz@kernel.org>
On 2020/3/5 4:33, Marc Zyngier wrote:
> Before GICv4.1, all operations would be serialized with the affinity
> changes by virtue of using the same ITS command queue. With v4.1, things
> change, as invalidations (and a number of other operations) are issued
> using the redistributor MMIO frame.
>
> We must thus make sure that these redistributor accesses cannot race
> against aginst the affinity change, or we may end-up talking to the
^^^^^^
> wrong redistributor.
>
> To ensure this, we expand the irq_to_cpuid() helper to take a spinlock
> when the LPI is mapped to a vLPI (a new per-VPE lock) on each operation
> that requires mutual exclusion.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Thanks
> ---
> drivers/irqchip/irq-gic-v3-its.c | 56 +++++++++++++++++++++++++-----
> include/linux/irqchip/arm-gic-v4.h | 5 +++
> 2 files changed, 53 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index da883a691028..1af713990123 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -239,15 +239,41 @@ static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
> return NULL;
> }
>
> -static int irq_to_cpuid(struct irq_data *d)
> +static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)
> +{
> + raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);
> + return vpe->col_idx;
> +}
> +
> +static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
> +{
> + raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
> +}
> +
> +static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
> {
> - struct its_device *its_dev = irq_data_get_irq_chip_data(d);
> struct its_vlpi_map *map = get_vlpi_map(d);
> + int cpu;
>
> - if (map)
> - return map->vpe->col_idx;
> + if (map) {
> + cpu = vpe_to_cpuid_lock(map->vpe, flags);
> + } else {
> + /* Physical LPIs are already locked via the irq_desc lock */
> + struct its_device *its_dev = irq_data_get_irq_chip_data(d);
> + cpu = its_dev->event_map.col_map[its_get_event_id(d)];
> + /* Keep GCC quiet... */
> + *flags = 0;
> + }
>
> - return its_dev->event_map.col_map[its_get_event_id(d)];
> + return cpu;
> +}
> +
> +static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
> +{
> + struct its_vlpi_map *map = get_vlpi_map(d);
> +
> + if (map)
> + vpe_to_cpuid_unlock(map->vpe, flags);
> }
>
> static struct its_collection *valid_col(struct its_collection *col)
> @@ -1329,7 +1355,9 @@ static void direct_lpi_inv(struct irq_data *d)
> {
> struct its_vlpi_map *map = get_vlpi_map(d);
> void __iomem *rdbase;
> + unsigned long flags;
> u64 val;
> + int cpu;
>
> if (map) {
> struct its_device *its_dev = irq_data_get_irq_chip_data(d);
> @@ -1344,10 +1372,12 @@ static void direct_lpi_inv(struct irq_data *d)
> }
>
> /* Target the redistributor this LPI is currently routed to */
> - rdbase = per_cpu_ptr(gic_rdists->rdist, irq_to_cpuid(d))->rd_base;
> + cpu = irq_to_cpuid_lock(d, &flags);
> + rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
> gic_write_lpir(val, rdbase + GICR_INVLPIR);
>
> wait_for_syncr(rdbase);
> + irq_to_cpuid_unlock(d, flags);
> }
>
> static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
> @@ -3486,17 +3516,25 @@ static int its_vpe_set_affinity(struct irq_data *d,
> {
> struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
> int from, cpu = cpumask_first(mask_val);
> + unsigned long flags;
>
> /*
> * Changing affinity is mega expensive, so let's be as lazy as
> * we can and only do it if we really have to. Also, if mapped
> * into the proxy device, we need to move the doorbell
> * interrupt to its new location.
> + *
> + * Another thing is that changing the affinity of a vPE affects
> + * *other interrupts* such as all the vLPIs that are routed to
> + * this vPE. This means that the irq_desc lock is not enough to
> + * protect us, and that we must ensure nobody samples vpe->col_idx
> + * during the update, hence the lock below which must also be
> + * taken on any vLPI handling path that evaluates vpe->col_idx.
> */
> - if (vpe->col_idx == cpu)
> + from = vpe_to_cpuid_lock(vpe, &flags);
> + if (from == cpu)
> goto out;
>
> - from = vpe->col_idx;
> vpe->col_idx = cpu;
>
> /*
> @@ -3512,6 +3550,7 @@ static int its_vpe_set_affinity(struct irq_data *d,
>
> out:
> irq_data_update_effective_affinity(d, cpumask_of(cpu));
> + vpe_to_cpuid_unlock(vpe, flags);
>
> return IRQ_SET_MASK_OK_DONE;
> }
> @@ -3855,6 +3894,7 @@ static int its_vpe_init(struct its_vpe *vpe)
> return -ENOMEM;
> }
>
> + raw_spin_lock_init(&vpe->vpe_lock);
> vpe->vpe_id = vpe_id;
> vpe->vpt_page = vpt_page;
> if (gic_rdists->has_rvpeid)
> diff --git a/include/linux/irqchip/arm-gic-v4.h b/include/linux/irqchip/arm-gic-v4.h
> index d9c34968467a..439963f4c66a 100644
> --- a/include/linux/irqchip/arm-gic-v4.h
> +++ b/include/linux/irqchip/arm-gic-v4.h
> @@ -53,6 +53,11 @@ struct its_vpe {
> };
> };
>
> + /*
> + * Ensures mutual exclusion between affinity setting of the
> + * vPE and vLPI operations using vpe->col_idx.
> + */
> + raw_spinlock_t vpe_lock;
> /*
> * This collection ID is used to indirect the target
> * redistributor for this VPE. The ID itself isn't involved in
>
next prev parent reply other threads:[~2020-03-12 6:57 UTC|newest]
Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-04 20:33 [PATCH v5 00/23] irqchip/gic-v4: GICv4.1 architecture support Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 01/23] irqchip/gic-v3: Use SGIs without active state if offered Marc Zyngier
2020-03-12 6:30 ` Zenghui Yu
2020-03-12 9:28 ` Marc Zyngier
2020-03-12 12:05 ` Marc Zyngier
2020-03-13 1:39 ` Zenghui Yu
2020-03-12 17:16 ` Auger Eric
2020-03-12 17:23 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 02/23] irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 03/23] irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access Marc Zyngier
2020-03-12 6:56 ` Zenghui Yu [this message]
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 04/23] irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation Marc Zyngier
2020-03-20 14:23 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 05/23] irqchip/gic-v4.1: Ensure mutual exclusion betwen invalidations on the same RD Marc Zyngier
2020-03-12 7:11 ` Zenghui Yu
2020-03-20 14:23 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 06/23] irqchip/gic-v4.1: Advertise support v4.1 to KVM Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 07/23] irqchip/gic-v4.1: Map the ITS SGIR register page Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 08/23] irqchip/gic-v4.1: Plumb skeletal VSGI irqchip Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-19 10:03 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 09/23] irqchip/gic-v4.1: Add initial SGI configuration Marc Zyngier
2020-03-16 17:53 ` Auger Eric
2020-03-17 2:02 ` Zenghui Yu
2020-03-17 8:36 ` Auger Eric
2020-03-19 10:20 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 10/23] irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks Marc Zyngier
2020-03-16 18:15 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 11/23] irqchip/gic-v4.1: Plumb get/set_irqchip_state " Marc Zyngier
2020-03-12 7:41 ` Zenghui Yu
2020-03-16 21:43 ` Auger Eric
2020-03-19 10:27 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 12/23] irqchip/gic-v4.1: Plumb set_vcpu_affinity " Marc Zyngier
2020-03-17 10:35 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 13/23] irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer Marc Zyngier
2020-03-12 8:20 ` Zenghui Yu
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 14/23] irqchip/gic-v4.1: Add VSGI allocation/teardown Marc Zyngier
2020-03-12 8:06 ` Zenghui Yu
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 15/23] irqchip/gic-v4.1: Add VSGI property setup Marc Zyngier
2020-03-12 8:09 ` Zenghui Yu
2020-03-17 10:30 ` Auger Eric
2020-03-19 10:57 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 16/23] irqchip/gic-v4.1: Eagerly vmap vPEs Marc Zyngier
2020-03-12 8:12 ` Zenghui Yu
2020-03-17 2:49 ` Zenghui Yu
2020-03-19 10:55 ` Marc Zyngier
2020-03-20 2:31 ` Zenghui Yu
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 17/23] KVM: arm64: GICv4.1: Let doorbells be auto-enabled Marc Zyngier
2020-03-12 8:15 ` Zenghui Yu
2020-03-17 11:04 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 18/23] KVM: arm64: GICv4.1: Add direct injection capability to SGI registers Marc Zyngier
2020-03-18 3:28 ` Zenghui Yu
2020-03-20 8:11 ` Auger Eric
2020-03-20 10:05 ` Marc Zyngier
2020-03-20 10:56 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 19/23] KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts Marc Zyngier
2020-03-19 16:16 ` Auger Eric
2020-03-19 19:52 ` Marc Zyngier
2020-03-19 20:13 ` Auger Eric
2020-03-20 9:17 ` Marc Zyngier
2020-03-20 4:22 ` Zenghui Yu
2020-03-04 20:33 ` [PATCH v5 20/23] KVM: arm64: GICv4.1: Plumb SGI implementation selection in the distributor Marc Zyngier
2020-03-18 6:34 ` Zenghui Yu
2020-03-19 12:10 ` Marc Zyngier
2020-03-19 20:38 ` Auger Eric
2020-03-20 3:08 ` Zenghui Yu
2020-03-20 7:59 ` Auger Eric
2020-03-20 9:46 ` Marc Zyngier
2020-03-20 11:09 ` Auger Eric
2020-03-20 11:20 ` Marc Zyngier
2020-03-20 3:53 ` Zenghui Yu
2020-03-20 9:01 ` Marc Zyngier
2020-03-23 8:11 ` Zenghui Yu
2020-03-23 8:25 ` Marc Zyngier
2020-03-23 12:40 ` Zenghui Yu
2020-03-04 20:33 ` [PATCH v5 21/23] KVM: arm64: GICv4.1: Reload VLPI configuration on distributor enable/disable Marc Zyngier
2020-03-18 3:17 ` Zenghui Yu
2020-03-19 12:18 ` Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 22/23] KVM: arm64: GICv4.1: Allow non-trapping WFI when using HW SGIs Marc Zyngier
2020-03-20 4:23 ` Zenghui Yu
2020-03-20 8:12 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 23/23] KVM: arm64: GICv4.1: Expose HW-based SGIs in debugfs Marc Zyngier
2020-03-18 3:19 ` Zenghui Yu
2020-03-19 15:05 ` Auger Eric
2020-03-19 15:21 ` Marc Zyngier
2020-03-19 15:43 ` Auger Eric
2020-03-19 16:16 ` Marc Zyngier
2020-03-19 16:17 ` Auger Eric
2020-03-20 4:38 ` Zenghui Yu
2020-03-20 9:09 ` Marc Zyngier
2020-03-20 11:35 ` Zenghui Yu
2020-03-20 11:46 ` Marc Zyngier
2020-03-20 12:09 ` Zenghui Yu
2020-03-05 3:39 ` [PATCH v5 00/23] irqchip/gic-v4: GICv4.1 architecture support Zenghui Yu
2020-03-09 8:17 ` Zenghui Yu
2020-03-09 8:46 ` Marc Zyngier
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