[PATCH 00/14] PHY: Add multilink DP support in Cadence Torrent PHY driver

[PATCH 00/14] PHY: Add multilink DP support in Cadence Torrent PHY driver

[Swapnil Jakhade]

This patch series enables Torrent PHY driver to support different input
reference clock frequencies. It also adds support for multilink
multiprotocol DisplayPort configuration. Currently, PCIe + DP multilink
register sequences are added.

Swapnil Jakhade (14):
  phy: cadence-torrent: Remove use of CamelCase to fix checkpatch CHECK
    message
  phy: cadence-torrent: Reorder few functions to remove function
    declarations
  phy: cadence-torrent: Add enum to support different input reference
    clocks
  phy: cadence-torrent: Select register configuration based on PHY
    reference clock
  phy: cadence-torrent: Add PHY registers for DP in array format
  phy: cadence-torrent: Reorder functions to avoid function declarations
  phy: cadence-torrent: Reorder functions to avoid function declarations
  phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref
    clock
  phy: cadence-torrent: Add separate functions for reusable code
  phy: cadence-torrent: Add function to get PLL to be configured for DP
  phy: cadence-torrent: Add multilink DP support
  phy: cadence-torrent: Add PCIe + DP multilink configuration
  phy: cadence-torrent: Add debug information for PHY configuration
  phy: cadence-torrent: Check PIPE mode PHY status to be ready for
    operation

 drivers/phy/cadence/phy-cadence-torrent.c | 3422 ++++++++++++---------
 1 file changed, 1993 insertions(+), 1429 deletions(-)

-- 
2.26.1

[PATCH 01/14] phy: cadence-torrent: Remove use of CamelCase to fix checkpatch CHECK message

[Swapnil Jakhade]

Script checkpatch with --strict option gives message:
CHECK: Avoid CamelCase: <REF_CLK_19_2MHz>
CHECK: Avoid CamelCase: <REF_CLK_25MHz>
Fix this by removing CamelCase usage. No functional change.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 24 +++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 0477e7beebbf..ff647669f1a3 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -24,8 +24,8 @@
 #include <linux/reset.h>
 #include <linux/regmap.h>
 
-#define REF_CLK_19_2MHz		19200000
-#define REF_CLK_25MHz		25000000
+#define REF_CLK_19_2MHZ		19200000
+#define REF_CLK_25MHZ		25000000
 
 #define MAX_NUM_LANES		4
 #define DEFAULT_MAX_BIT_RATE	8100 /* in Mbps */
@@ -695,12 +695,12 @@ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
 	ndelay(200);
 
 	/* DP Rate Change - VCO Output settings. */
-	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) {
+	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ) {
 		/* PMA common configuration 19.2MHz */
 		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
 							dp->ssc);
 		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
-	} else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) {
+	} else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ) {
 		/* PMA common configuration 25MHz */
 		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
 						      dp->ssc);
@@ -993,8 +993,8 @@ static int cdns_torrent_dp_init(struct phy *phy)
 	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
 
 	switch (cdns_phy->ref_clk_rate) {
-	case REF_CLK_19_2MHz:
-	case REF_CLK_25MHz:
+	case REF_CLK_19_2MHZ:
+	case REF_CLK_25MHZ:
 		/* Valid Ref Clock Rate */
 		break;
 	default:
@@ -1026,11 +1026,11 @@ static int cdns_torrent_dp_init(struct phy *phy)
 
 	/* PHY PMA registers configuration functions */
 	/* Initialize PHY with max supported link rate, without SSC. */
-	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
+	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
 		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
 							cdns_phy->max_bit_rate,
 							false);
-	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
+	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
 		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
 						      cdns_phy->max_bit_rate,
 						      false);
@@ -1074,10 +1074,10 @@ static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
 {
 	unsigned int i;
 
-	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
+	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
 		/* PMA common configuration 19.2MHz */
 		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
-	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
+	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
 		/* PMA common configuration 25MHz */
 		cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
 
@@ -1529,10 +1529,10 @@ static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
 					 unsigned int lane)
 {
 	/* Per lane, refclock-dependent receiver detection setting */
-	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
+	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
 		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
 				       TX_RCVDET_ST_TMR, 0x0780);
-	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
+	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
 		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
 				       TX_RCVDET_ST_TMR, 0x09C4);
 
-- 
2.26.1

Re: [PATCH 01/14] phy: cadence-torrent: Remove use of CamelCase to fix checkpatch CHECK message

[Kishon Vijay Abraham I]

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Script checkpatch with --strict option gives message:
> CHECK: Avoid CamelCase: <REF_CLK_19_2MHz>
> CHECK: Avoid CamelCase: <REF_CLK_25MHz>
> Fix this by removing CamelCase usage. No functional change.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>

Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 24 +++++++++++------------
>  1 file changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index 0477e7beebbf..ff647669f1a3 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -24,8 +24,8 @@
>  #include <linux/reset.h>
>  #include <linux/regmap.h>
>  
> -#define REF_CLK_19_2MHz		19200000
> -#define REF_CLK_25MHz		25000000
> +#define REF_CLK_19_2MHZ		19200000
> +#define REF_CLK_25MHZ		25000000
>  
>  #define MAX_NUM_LANES		4
>  #define DEFAULT_MAX_BIT_RATE	8100 /* in Mbps */
> @@ -695,12 +695,12 @@ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
>  	ndelay(200);
>  
>  	/* DP Rate Change - VCO Output settings. */
> -	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) {
> +	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ) {
>  		/* PMA common configuration 19.2MHz */
>  		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
>  							dp->ssc);
>  		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
> -	} else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) {
> +	} else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ) {
>  		/* PMA common configuration 25MHz */
>  		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
>  						      dp->ssc);
> @@ -993,8 +993,8 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
>  
>  	switch (cdns_phy->ref_clk_rate) {
> -	case REF_CLK_19_2MHz:
> -	case REF_CLK_25MHz:
> +	case REF_CLK_19_2MHZ:
> +	case REF_CLK_25MHZ:
>  		/* Valid Ref Clock Rate */
>  		break;
>  	default:
> @@ -1026,11 +1026,11 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  
>  	/* PHY PMA registers configuration functions */
>  	/* Initialize PHY with max supported link rate, without SSC. */
> -	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
> +	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
>  		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
>  							cdns_phy->max_bit_rate,
>  							false);
> -	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
> +	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
>  		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
>  						      cdns_phy->max_bit_rate,
>  						      false);
> @@ -1074,10 +1074,10 @@ static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
>  {
>  	unsigned int i;
>  
> -	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
> +	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
>  		/* PMA common configuration 19.2MHz */
>  		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
> -	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
> +	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
>  		/* PMA common configuration 25MHz */
>  		cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
>  
> @@ -1529,10 +1529,10 @@ static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
>  					 unsigned int lane)
>  {
>  	/* Per lane, refclock-dependent receiver detection setting */
> -	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
> +	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
>  		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
>  				       TX_RCVDET_ST_TMR, 0x0780);
> -	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
> +	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
>  		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
>  				       TX_RCVDET_ST_TMR, 0x09C4);
>  
> 

[PATCH 02/14] phy: cadence-torrent: Reorder few functions to remove function declarations

[Swapnil Jakhade]

Reorder some functions to avoid function declarations.
No functional change.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 474 +++++++++++-----------
 1 file changed, 229 insertions(+), 245 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index ff647669f1a3..6eeb753fbb78 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -333,12 +333,6 @@ struct cdns_torrent_derived_refclk {
 #define to_cdns_torrent_derived_refclk(_hw)	\
 			container_of(_hw, struct cdns_torrent_derived_refclk, hw)
 
-static int cdns_torrent_phy_init(struct phy *phy);
-static int cdns_torrent_dp_init(struct phy *phy);
-static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
-			       u32 num_lanes);
-static
-int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
 static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
 				    struct cdns_torrent_inst *inst);
 static
@@ -353,36 +347,6 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
 					   u32 rate, bool ssc);
 static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
 					 unsigned int lane);
-static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
-					 u32 rate, u32 num_lanes);
-static int cdns_torrent_dp_configure(struct phy *phy,
-				     union phy_configure_opts *opts);
-static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
-					   u32 num_lanes,
-					   enum phy_powerstate powerstate);
-static int cdns_torrent_phy_on(struct phy *phy);
-static int cdns_torrent_phy_off(struct phy *phy);
-
-static const struct phy_ops cdns_torrent_phy_ops = {
-	.init		= cdns_torrent_phy_init,
-	.configure	= cdns_torrent_dp_configure,
-	.power_on	= cdns_torrent_phy_on,
-	.power_off	= cdns_torrent_phy_off,
-	.owner		= THIS_MODULE,
-};
-
-static int cdns_torrent_noop_phy_on(struct phy *phy)
-{
-	/* Give 5ms to 10ms delay for the PIPE clock to be stable */
-	usleep_range(5000, 10000);
-
-	return 0;
-}
-
-static const struct phy_ops noop_ops = {
-	.power_on	= cdns_torrent_noop_phy_on,
-	.owner		= THIS_MODULE,
-};
 
 struct cdns_reg_pairs {
 	u32 val;
@@ -669,6 +633,164 @@ static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
 	return ret;
 }
 
+static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
+					   u32 num_lanes,
+					   enum phy_powerstate powerstate)
+{
+	/* Register value for power state for a single byte. */
+	u32 value_part;
+	u32 value;
+	u32 mask;
+	u32 read_val;
+	u32 ret;
+	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
+
+	switch (powerstate) {
+	case (POWERSTATE_A0):
+		value_part = 0x01U;
+		break;
+	case (POWERSTATE_A2):
+		value_part = 0x04U;
+		break;
+	default:
+		/* Powerstate A3 */
+		value_part = 0x08U;
+		break;
+	}
+
+	/* Select values of registers and mask, depending on enabled
+	 * lane count.
+	 */
+	switch (num_lanes) {
+	/* lane 0 */
+	case (1):
+		value = value_part;
+		mask = 0x0000003FU;
+		break;
+	/* lanes 0-1 */
+	case (2):
+		value = (value_part
+			 | (value_part << 8));
+		mask = 0x00003F3FU;
+		break;
+	/* lanes 0-3, all */
+	default:
+		value = (value_part
+			 | (value_part << 8)
+			 | (value_part << 16)
+			 | (value_part << 24));
+		mask = 0x3F3F3F3FU;
+		break;
+	}
+
+	/* Set power state A<n>. */
+	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
+	/* Wait, until PHY acknowledges power state completion. */
+	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
+				       read_val, (read_val & mask) == value, 0,
+				       POLL_TIMEOUT_US);
+	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
+	ndelay(100);
+
+	return ret;
+}
+
+static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
+{
+	unsigned int read_val;
+	int ret;
+	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
+
+	/*
+	 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
+	 * master lane
+	 */
+	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
+				       read_val, read_val & 1,
+				       0, POLL_TIMEOUT_US);
+	if (ret == -ETIMEDOUT) {
+		dev_err(cdns_phy->dev,
+			"timeout waiting for link PLL clock enable ack\n");
+		return ret;
+	}
+
+	ndelay(100);
+
+	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
+					      POWERSTATE_A2);
+	if (ret)
+		return ret;
+
+	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
+					      POWERSTATE_A0);
+
+	return ret;
+}
+
+static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
+{
+	unsigned int reg;
+	int ret;
+	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
+
+	ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
+				       reg & 1, 0, POLL_TIMEOUT_US);
+	if (ret == -ETIMEDOUT) {
+		dev_err(cdns_phy->dev,
+			"timeout waiting for PMA common ready\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
+					 u32 rate, u32 num_lanes)
+{
+	unsigned int clk_sel_val = 0;
+	unsigned int hsclk_div_val = 0;
+	unsigned int i;
+
+	/* 16'h0000 for single DP link configuration */
+	regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
+
+	switch (rate) {
+	case 1620:
+		clk_sel_val = 0x0f01;
+		hsclk_div_val = 2;
+		break;
+	case 2160:
+	case 2430:
+	case 2700:
+		clk_sel_val = 0x0701;
+		hsclk_div_val = 1;
+		break;
+	case 3240:
+		clk_sel_val = 0x0b00;
+		hsclk_div_val = 2;
+		break;
+	case 4320:
+	case 5400:
+		clk_sel_val = 0x0301;
+		hsclk_div_val = 0;
+		break;
+	case 8100:
+		clk_sel_val = 0x0200;
+		hsclk_div_val = 0;
+		break;
+	}
+
+	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
+			       CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
+	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
+			       CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
+
+	/* PMA lane configuration to deal with multi-link operation */
+	for (i = 0; i < num_lanes; i++)
+		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
+				       XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
+}
+
 /*
  * Perform register operations related to setting link rate, once powerstate is
  * set and PLL disable request was processed.
@@ -984,6 +1106,56 @@ static int cdns_torrent_dp_configure(struct phy *phy,
 	return ret;
 }
 
+static int cdns_torrent_phy_on(struct phy *phy)
+{
+	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
+	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
+	u32 read_val;
+	int ret;
+
+	if (cdns_phy->nsubnodes == 1) {
+		/* Take the PHY lane group out of reset */
+		reset_control_deassert(inst->lnk_rst);
+
+		/* Take the PHY out of reset */
+		ret = reset_control_deassert(cdns_phy->phy_rst);
+		if (ret)
+			return ret;
+	}
+
+	/*
+	 * Wait for cmn_ready assertion
+	 * PHY_PMA_CMN_CTRL1[0] == 1
+	 */
+	ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
+					     read_val, read_val, 1000,
+					     PLL_LOCK_TIMEOUT);
+	if (ret) {
+		dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
+		return ret;
+	}
+
+	mdelay(10);
+
+	return 0;
+}
+
+static int cdns_torrent_phy_off(struct phy *phy)
+{
+	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
+	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
+	int ret;
+
+	if (cdns_phy->nsubnodes != 1)
+		return 0;
+
+	ret = reset_control_assert(cdns_phy->phy_rst);
+	if (ret)
+		return ret;
+
+	return reset_control_assert(inst->lnk_rst);
+}
+
 static int cdns_torrent_dp_init(struct phy *phy)
 {
 	unsigned char lane_bits;
@@ -1051,24 +1223,6 @@ static int cdns_torrent_dp_init(struct phy *phy)
 	return ret;
 }
 
-static
-int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
-{
-	unsigned int reg;
-	int ret;
-	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
-
-	ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
-				       reg & 1, 0, POLL_TIMEOUT_US);
-	if (ret == -ETIMEDOUT) {
-		dev_err(cdns_phy->dev,
-			"timeout waiting for PMA common ready\n");
-		return -ETIMEDOUT;
-	}
-
-	return 0;
-}
-
 static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
 				    struct cdns_torrent_inst *inst)
 {
@@ -1478,53 +1632,6 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
 	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
 }
 
-static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
-					 u32 rate, u32 num_lanes)
-{
-	unsigned int clk_sel_val = 0;
-	unsigned int hsclk_div_val = 0;
-	unsigned int i;
-
-	/* 16'h0000 for single DP link configuration */
-	regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
-
-	switch (rate) {
-	case 1620:
-		clk_sel_val = 0x0f01;
-		hsclk_div_val = 2;
-		break;
-	case 2160:
-	case 2430:
-	case 2700:
-		clk_sel_val = 0x0701;
-		hsclk_div_val = 1;
-		break;
-	case 3240:
-		clk_sel_val = 0x0b00;
-		hsclk_div_val = 2;
-		break;
-	case 4320:
-	case 5400:
-		clk_sel_val = 0x0301;
-		hsclk_div_val = 0;
-		break;
-	case 8100:
-		clk_sel_val = 0x0200;
-		hsclk_div_val = 0;
-		break;
-	}
-
-	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
-			       CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
-	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
-			       CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
-
-	/* PMA lane configuration to deal with multi-link operation */
-	for (i = 0; i < num_lanes; i++)
-		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
-				       XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
-}
-
 static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
 					 unsigned int lane)
 {
@@ -1568,100 +1675,6 @@ static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
 			       XCVR_DIAG_HSCLK_SEL, 0x0000);
 }
 
-static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
-					   u32 num_lanes,
-					   enum phy_powerstate powerstate)
-{
-	/* Register value for power state for a single byte. */
-	u32 value_part;
-	u32 value;
-	u32 mask;
-	u32 read_val;
-	u32 ret;
-	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
-
-	switch (powerstate) {
-	case (POWERSTATE_A0):
-		value_part = 0x01U;
-		break;
-	case (POWERSTATE_A2):
-		value_part = 0x04U;
-		break;
-	default:
-		/* Powerstate A3 */
-		value_part = 0x08U;
-		break;
-	}
-
-	/* Select values of registers and mask, depending on enabled
-	 * lane count.
-	 */
-	switch (num_lanes) {
-	/* lane 0 */
-	case (1):
-		value = value_part;
-		mask = 0x0000003FU;
-		break;
-	/* lanes 0-1 */
-	case (2):
-		value = (value_part
-			 | (value_part << 8));
-		mask = 0x00003F3FU;
-		break;
-	/* lanes 0-3, all */
-	default:
-		value = (value_part
-			 | (value_part << 8)
-			 | (value_part << 16)
-			 | (value_part << 24));
-		mask = 0x3F3F3F3FU;
-		break;
-	}
-
-	/* Set power state A<n>. */
-	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
-	/* Wait, until PHY acknowledges power state completion. */
-	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
-				       read_val, (read_val & mask) == value, 0,
-				       POLL_TIMEOUT_US);
-	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
-	ndelay(100);
-
-	return ret;
-}
-
-static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
-{
-	unsigned int read_val;
-	int ret;
-	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
-
-	/*
-	 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
-	 * master lane
-	 */
-	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
-				       read_val, read_val & 1,
-				       0, POLL_TIMEOUT_US);
-	if (ret == -ETIMEDOUT) {
-		dev_err(cdns_phy->dev,
-			"timeout waiting for link PLL clock enable ack\n");
-		return ret;
-	}
-
-	ndelay(100);
-
-	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
-					      POWERSTATE_A2);
-	if (ret)
-		return ret;
-
-	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
-					      POWERSTATE_A0);
-
-	return ret;
-}
-
 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
 {
 	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
@@ -1764,56 +1777,6 @@ static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_ph
 	return 0;
 }
 
-static int cdns_torrent_phy_on(struct phy *phy)
-{
-	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
-	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
-	u32 read_val;
-	int ret;
-
-	if (cdns_phy->nsubnodes == 1) {
-		/* Take the PHY lane group out of reset */
-		reset_control_deassert(inst->lnk_rst);
-
-		/* Take the PHY out of reset */
-		ret = reset_control_deassert(cdns_phy->phy_rst);
-		if (ret)
-			return ret;
-	}
-
-	/*
-	 * Wait for cmn_ready assertion
-	 * PHY_PMA_CMN_CTRL1[0] == 1
-	 */
-	ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
-					     read_val, read_val, 1000,
-					     PLL_LOCK_TIMEOUT);
-	if (ret) {
-		dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
-		return ret;
-	}
-
-	mdelay(10);
-
-	return 0;
-}
-
-static int cdns_torrent_phy_off(struct phy *phy)
-{
-	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
-	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
-	int ret;
-
-	if (cdns_phy->nsubnodes != 1)
-		return 0;
-
-	ret = reset_control_assert(cdns_phy->phy_rst);
-	if (ret)
-		return ret;
-
-	return reset_control_assert(inst->lnk_rst);
-}
-
 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
 				       u32 block_offset,
 				       u8 reg_offset_shift,
@@ -2091,6 +2054,27 @@ static int cdns_torrent_phy_init(struct phy *phy)
 	return 0;
 }
 
+static const struct phy_ops cdns_torrent_phy_ops = {
+	.init		= cdns_torrent_phy_init,
+	.configure	= cdns_torrent_dp_configure,
+	.power_on	= cdns_torrent_phy_on,
+	.power_off	= cdns_torrent_phy_off,
+	.owner		= THIS_MODULE,
+};
+
+static int cdns_torrent_noop_phy_on(struct phy *phy)
+{
+	/* Give 5ms to 10ms delay for the PIPE clock to be stable */
+	usleep_range(5000, 10000);
+
+	return 0;
+}
+
+static const struct phy_ops noop_ops = {
+	.power_on	= cdns_torrent_noop_phy_on,
+	.owner		= THIS_MODULE,
+};
+
 static
 int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
 {
-- 
2.26.1

Re: [PATCH 02/14] phy: cadence-torrent: Reorder few functions to remove function declarations

[Kishon Vijay Abraham I]

Hi Swapnil,

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Reorder some functions to avoid function declarations.
> No functional change.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>

Please squash patches 2, 6 and 7 together unless you have a specific
reason to keep them separate.

Thanks
Kishon

> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 474 +++++++++++-----------
>  1 file changed, 229 insertions(+), 245 deletions(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index ff647669f1a3..6eeb753fbb78 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -333,12 +333,6 @@ struct cdns_torrent_derived_refclk {
>  #define to_cdns_torrent_derived_refclk(_hw)	\
>  			container_of(_hw, struct cdns_torrent_derived_refclk, hw)
>  
> -static int cdns_torrent_phy_init(struct phy *phy);
> -static int cdns_torrent_dp_init(struct phy *phy);
> -static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
> -			       u32 num_lanes);
> -static
> -int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
>  static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
>  				    struct cdns_torrent_inst *inst);
>  static
> @@ -353,36 +347,6 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
>  					   u32 rate, bool ssc);
>  static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
>  					 unsigned int lane);
> -static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
> -					 u32 rate, u32 num_lanes);
> -static int cdns_torrent_dp_configure(struct phy *phy,
> -				     union phy_configure_opts *opts);
> -static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
> -					   u32 num_lanes,
> -					   enum phy_powerstate powerstate);
> -static int cdns_torrent_phy_on(struct phy *phy);
> -static int cdns_torrent_phy_off(struct phy *phy);
> -
> -static const struct phy_ops cdns_torrent_phy_ops = {
> -	.init		= cdns_torrent_phy_init,
> -	.configure	= cdns_torrent_dp_configure,
> -	.power_on	= cdns_torrent_phy_on,
> -	.power_off	= cdns_torrent_phy_off,
> -	.owner		= THIS_MODULE,
> -};
> -
> -static int cdns_torrent_noop_phy_on(struct phy *phy)
> -{
> -	/* Give 5ms to 10ms delay for the PIPE clock to be stable */
> -	usleep_range(5000, 10000);
> -
> -	return 0;
> -}
> -
> -static const struct phy_ops noop_ops = {
> -	.power_on	= cdns_torrent_noop_phy_on,
> -	.owner		= THIS_MODULE,
> -};
>  
>  struct cdns_reg_pairs {
>  	u32 val;
> @@ -669,6 +633,164 @@ static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
>  	return ret;
>  }
>  
> +static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
> +					   u32 num_lanes,
> +					   enum phy_powerstate powerstate)
> +{
> +	/* Register value for power state for a single byte. */
> +	u32 value_part;
> +	u32 value;
> +	u32 mask;
> +	u32 read_val;
> +	u32 ret;
> +	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
> +
> +	switch (powerstate) {
> +	case (POWERSTATE_A0):
> +		value_part = 0x01U;
> +		break;
> +	case (POWERSTATE_A2):
> +		value_part = 0x04U;
> +		break;
> +	default:
> +		/* Powerstate A3 */
> +		value_part = 0x08U;
> +		break;
> +	}
> +
> +	/* Select values of registers and mask, depending on enabled
> +	 * lane count.
> +	 */
> +	switch (num_lanes) {
> +	/* lane 0 */
> +	case (1):
> +		value = value_part;
> +		mask = 0x0000003FU;
> +		break;
> +	/* lanes 0-1 */
> +	case (2):
> +		value = (value_part
> +			 | (value_part << 8));
> +		mask = 0x00003F3FU;
> +		break;
> +	/* lanes 0-3, all */
> +	default:
> +		value = (value_part
> +			 | (value_part << 8)
> +			 | (value_part << 16)
> +			 | (value_part << 24));
> +		mask = 0x3F3F3F3FU;
> +		break;
> +	}
> +
> +	/* Set power state A<n>. */
> +	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
> +	/* Wait, until PHY acknowledges power state completion. */
> +	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
> +				       read_val, (read_val & mask) == value, 0,
> +				       POLL_TIMEOUT_US);
> +	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
> +	ndelay(100);
> +
> +	return ret;
> +}
> +
> +static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
> +{
> +	unsigned int read_val;
> +	int ret;
> +	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
> +
> +	/*
> +	 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
> +	 * master lane
> +	 */
> +	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
> +				       read_val, read_val & 1,
> +				       0, POLL_TIMEOUT_US);
> +	if (ret == -ETIMEDOUT) {
> +		dev_err(cdns_phy->dev,
> +			"timeout waiting for link PLL clock enable ack\n");
> +		return ret;
> +	}
> +
> +	ndelay(100);
> +
> +	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
> +					      POWERSTATE_A2);
> +	if (ret)
> +		return ret;
> +
> +	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
> +					      POWERSTATE_A0);
> +
> +	return ret;
> +}
> +
> +static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
> +{
> +	unsigned int reg;
> +	int ret;
> +	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
> +
> +	ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
> +				       reg & 1, 0, POLL_TIMEOUT_US);
> +	if (ret == -ETIMEDOUT) {
> +		dev_err(cdns_phy->dev,
> +			"timeout waiting for PMA common ready\n");
> +		return -ETIMEDOUT;
> +	}
> +
> +	return 0;
> +}
> +
> +static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
> +					 u32 rate, u32 num_lanes)
> +{
> +	unsigned int clk_sel_val = 0;
> +	unsigned int hsclk_div_val = 0;
> +	unsigned int i;
> +
> +	/* 16'h0000 for single DP link configuration */
> +	regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
> +
> +	switch (rate) {
> +	case 1620:
> +		clk_sel_val = 0x0f01;
> +		hsclk_div_val = 2;
> +		break;
> +	case 2160:
> +	case 2430:
> +	case 2700:
> +		clk_sel_val = 0x0701;
> +		hsclk_div_val = 1;
> +		break;
> +	case 3240:
> +		clk_sel_val = 0x0b00;
> +		hsclk_div_val = 2;
> +		break;
> +	case 4320:
> +	case 5400:
> +		clk_sel_val = 0x0301;
> +		hsclk_div_val = 0;
> +		break;
> +	case 8100:
> +		clk_sel_val = 0x0200;
> +		hsclk_div_val = 0;
> +		break;
> +	}
> +
> +	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
> +			       CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
> +	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
> +			       CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
> +
> +	/* PMA lane configuration to deal with multi-link operation */
> +	for (i = 0; i < num_lanes; i++)
> +		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
> +				       XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
> +}
> +
>  /*
>   * Perform register operations related to setting link rate, once powerstate is
>   * set and PLL disable request was processed.
> @@ -984,6 +1106,56 @@ static int cdns_torrent_dp_configure(struct phy *phy,
>  	return ret;
>  }
>  
> +static int cdns_torrent_phy_on(struct phy *phy)
> +{
> +	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
> +	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
> +	u32 read_val;
> +	int ret;
> +
> +	if (cdns_phy->nsubnodes == 1) {
> +		/* Take the PHY lane group out of reset */
> +		reset_control_deassert(inst->lnk_rst);
> +
> +		/* Take the PHY out of reset */
> +		ret = reset_control_deassert(cdns_phy->phy_rst);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	/*
> +	 * Wait for cmn_ready assertion
> +	 * PHY_PMA_CMN_CTRL1[0] == 1
> +	 */
> +	ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
> +					     read_val, read_val, 1000,
> +					     PLL_LOCK_TIMEOUT);
> +	if (ret) {
> +		dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
> +		return ret;
> +	}
> +
> +	mdelay(10);
> +
> +	return 0;
> +}
> +
> +static int cdns_torrent_phy_off(struct phy *phy)
> +{
> +	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
> +	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
> +	int ret;
> +
> +	if (cdns_phy->nsubnodes != 1)
> +		return 0;
> +
> +	ret = reset_control_assert(cdns_phy->phy_rst);
> +	if (ret)
> +		return ret;
> +
> +	return reset_control_assert(inst->lnk_rst);
> +}
> +
>  static int cdns_torrent_dp_init(struct phy *phy)
>  {
>  	unsigned char lane_bits;
> @@ -1051,24 +1223,6 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  	return ret;
>  }
>  
> -static
> -int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
> -{
> -	unsigned int reg;
> -	int ret;
> -	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
> -
> -	ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
> -				       reg & 1, 0, POLL_TIMEOUT_US);
> -	if (ret == -ETIMEDOUT) {
> -		dev_err(cdns_phy->dev,
> -			"timeout waiting for PMA common ready\n");
> -		return -ETIMEDOUT;
> -	}
> -
> -	return 0;
> -}
> -
>  static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
>  				    struct cdns_torrent_inst *inst)
>  {
> @@ -1478,53 +1632,6 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
>  	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
>  }
>  
> -static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
> -					 u32 rate, u32 num_lanes)
> -{
> -	unsigned int clk_sel_val = 0;
> -	unsigned int hsclk_div_val = 0;
> -	unsigned int i;
> -
> -	/* 16'h0000 for single DP link configuration */
> -	regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
> -
> -	switch (rate) {
> -	case 1620:
> -		clk_sel_val = 0x0f01;
> -		hsclk_div_val = 2;
> -		break;
> -	case 2160:
> -	case 2430:
> -	case 2700:
> -		clk_sel_val = 0x0701;
> -		hsclk_div_val = 1;
> -		break;
> -	case 3240:
> -		clk_sel_val = 0x0b00;
> -		hsclk_div_val = 2;
> -		break;
> -	case 4320:
> -	case 5400:
> -		clk_sel_val = 0x0301;
> -		hsclk_div_val = 0;
> -		break;
> -	case 8100:
> -		clk_sel_val = 0x0200;
> -		hsclk_div_val = 0;
> -		break;
> -	}
> -
> -	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
> -			       CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
> -	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
> -			       CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
> -
> -	/* PMA lane configuration to deal with multi-link operation */
> -	for (i = 0; i < num_lanes; i++)
> -		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
> -				       XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
> -}
> -
>  static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
>  					 unsigned int lane)
>  {
> @@ -1568,100 +1675,6 @@ static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
>  			       XCVR_DIAG_HSCLK_SEL, 0x0000);
>  }
>  
> -static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
> -					   u32 num_lanes,
> -					   enum phy_powerstate powerstate)
> -{
> -	/* Register value for power state for a single byte. */
> -	u32 value_part;
> -	u32 value;
> -	u32 mask;
> -	u32 read_val;
> -	u32 ret;
> -	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
> -
> -	switch (powerstate) {
> -	case (POWERSTATE_A0):
> -		value_part = 0x01U;
> -		break;
> -	case (POWERSTATE_A2):
> -		value_part = 0x04U;
> -		break;
> -	default:
> -		/* Powerstate A3 */
> -		value_part = 0x08U;
> -		break;
> -	}
> -
> -	/* Select values of registers and mask, depending on enabled
> -	 * lane count.
> -	 */
> -	switch (num_lanes) {
> -	/* lane 0 */
> -	case (1):
> -		value = value_part;
> -		mask = 0x0000003FU;
> -		break;
> -	/* lanes 0-1 */
> -	case (2):
> -		value = (value_part
> -			 | (value_part << 8));
> -		mask = 0x00003F3FU;
> -		break;
> -	/* lanes 0-3, all */
> -	default:
> -		value = (value_part
> -			 | (value_part << 8)
> -			 | (value_part << 16)
> -			 | (value_part << 24));
> -		mask = 0x3F3F3F3FU;
> -		break;
> -	}
> -
> -	/* Set power state A<n>. */
> -	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
> -	/* Wait, until PHY acknowledges power state completion. */
> -	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
> -				       read_val, (read_val & mask) == value, 0,
> -				       POLL_TIMEOUT_US);
> -	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
> -	ndelay(100);
> -
> -	return ret;
> -}
> -
> -static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
> -{
> -	unsigned int read_val;
> -	int ret;
> -	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
> -
> -	/*
> -	 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
> -	 * master lane
> -	 */
> -	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
> -				       read_val, read_val & 1,
> -				       0, POLL_TIMEOUT_US);
> -	if (ret == -ETIMEDOUT) {
> -		dev_err(cdns_phy->dev,
> -			"timeout waiting for link PLL clock enable ack\n");
> -		return ret;
> -	}
> -
> -	ndelay(100);
> -
> -	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
> -					      POWERSTATE_A2);
> -	if (ret)
> -		return ret;
> -
> -	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
> -					      POWERSTATE_A0);
> -
> -	return ret;
> -}
> -
>  static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
>  {
>  	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
> @@ -1764,56 +1777,6 @@ static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_ph
>  	return 0;
>  }
>  
> -static int cdns_torrent_phy_on(struct phy *phy)
> -{
> -	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
> -	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
> -	u32 read_val;
> -	int ret;
> -
> -	if (cdns_phy->nsubnodes == 1) {
> -		/* Take the PHY lane group out of reset */
> -		reset_control_deassert(inst->lnk_rst);
> -
> -		/* Take the PHY out of reset */
> -		ret = reset_control_deassert(cdns_phy->phy_rst);
> -		if (ret)
> -			return ret;
> -	}
> -
> -	/*
> -	 * Wait for cmn_ready assertion
> -	 * PHY_PMA_CMN_CTRL1[0] == 1
> -	 */
> -	ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
> -					     read_val, read_val, 1000,
> -					     PLL_LOCK_TIMEOUT);
> -	if (ret) {
> -		dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
> -		return ret;
> -	}
> -
> -	mdelay(10);
> -
> -	return 0;
> -}
> -
> -static int cdns_torrent_phy_off(struct phy *phy)
> -{
> -	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
> -	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
> -	int ret;
> -
> -	if (cdns_phy->nsubnodes != 1)
> -		return 0;
> -
> -	ret = reset_control_assert(cdns_phy->phy_rst);
> -	if (ret)
> -		return ret;
> -
> -	return reset_control_assert(inst->lnk_rst);
> -}
> -
>  static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
>  				       u32 block_offset,
>  				       u8 reg_offset_shift,
> @@ -2091,6 +2054,27 @@ static int cdns_torrent_phy_init(struct phy *phy)
>  	return 0;
>  }
>  
> +static const struct phy_ops cdns_torrent_phy_ops = {
> +	.init		= cdns_torrent_phy_init,
> +	.configure	= cdns_torrent_dp_configure,
> +	.power_on	= cdns_torrent_phy_on,
> +	.power_off	= cdns_torrent_phy_off,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int cdns_torrent_noop_phy_on(struct phy *phy)
> +{
> +	/* Give 5ms to 10ms delay for the PIPE clock to be stable */
> +	usleep_range(5000, 10000);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops noop_ops = {
> +	.power_on	= cdns_torrent_noop_phy_on,
> +	.owner		= THIS_MODULE,
> +};
> +
>  static
>  int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
>  {
> 

[PATCH 03/14] phy: cadence-torrent: Add enum to support different input reference clocks

[Swapnil Jakhade]

Torrent PHY supports different input reference clock frequencies.
Register configurations will be different based on reference clock value.
Prepare driver to support register configs for multiple reference clocks.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 51 +++++++++++++++++------
 1 file changed, 38 insertions(+), 13 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 6eeb753fbb78..252920ea7fdf 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -26,11 +26,13 @@
 
 #define REF_CLK_19_2MHZ		19200000
 #define REF_CLK_25MHZ		25000000
+#define REF_CLK_100MHZ		100000000
 
 #define MAX_NUM_LANES		4
 #define DEFAULT_MAX_BIT_RATE	8100 /* in Mbps */
 
 #define NUM_SSC_MODE		3
+#define NUM_REF_CLK		3
 #define NUM_PHY_TYPE		6
 
 #define POLL_TIMEOUT_US		5000
@@ -273,6 +275,12 @@ enum cdns_torrent_phy_type {
 	TYPE_USB,
 };
 
+enum cdns_torrent_ref_clk {
+	CLK_19_2_MHZ,
+	CLK_25_MHZ,
+	CLK_100_MHZ
+};
+
 enum cdns_torrent_ssc_mode {
 	NO_SSC,
 	EXTERNAL_SSC,
@@ -296,7 +304,7 @@ struct cdns_torrent_phy {
 	struct reset_control *apb_rst;
 	struct device *dev;
 	struct clk *clk;
-	unsigned long ref_clk_rate;
+	enum cdns_torrent_ref_clk ref_clk_rate;
 	struct cdns_torrent_inst phys[MAX_NUM_LANES];
 	int nsubnodes;
 	const struct cdns_torrent_data *init_data;
@@ -817,12 +825,12 @@ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
 	ndelay(200);
 
 	/* DP Rate Change - VCO Output settings. */
-	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ) {
+	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) {
 		/* PMA common configuration 19.2MHz */
 		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
 							dp->ssc);
 		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
-	} else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ) {
+	} else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) {
 		/* PMA common configuration 25MHz */
 		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
 						      dp->ssc);
@@ -1165,8 +1173,8 @@ static int cdns_torrent_dp_init(struct phy *phy)
 	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
 
 	switch (cdns_phy->ref_clk_rate) {
-	case REF_CLK_19_2MHZ:
-	case REF_CLK_25MHZ:
+	case CLK_19_2_MHZ:
+	case CLK_25_MHZ:
 		/* Valid Ref Clock Rate */
 		break;
 	default:
@@ -1198,11 +1206,11 @@ static int cdns_torrent_dp_init(struct phy *phy)
 
 	/* PHY PMA registers configuration functions */
 	/* Initialize PHY with max supported link rate, without SSC. */
-	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
+	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
 		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
 							cdns_phy->max_bit_rate,
 							false);
-	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
+	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
 		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
 						      cdns_phy->max_bit_rate,
 						      false);
@@ -1228,10 +1236,10 @@ static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
 {
 	unsigned int i;
 
-	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
+	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
 		/* PMA common configuration 19.2MHz */
 		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
-	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
+	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
 		/* PMA common configuration 25MHz */
 		cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
 
@@ -1636,10 +1644,10 @@ static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
 					 unsigned int lane)
 {
 	/* Per lane, refclock-dependent receiver detection setting */
-	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
+	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
 		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
 				       TX_RCVDET_ST_TMR, 0x0780);
-	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
+	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
 		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
 				       TX_RCVDET_ST_TMR, 0x09C4);
 
@@ -2270,6 +2278,7 @@ static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy)
 static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
 {
 	struct device *dev = cdns_phy->dev;
+	unsigned long ref_clk_rate;
 	int ret;
 
 	cdns_phy->clk = devm_clk_get(dev, "refclk");
@@ -2284,13 +2293,29 @@ static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
 		return ret;
 	}
 
-	cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk);
-	if (!(cdns_phy->ref_clk_rate)) {
+	ref_clk_rate = clk_get_rate(cdns_phy->clk);
+	if (!ref_clk_rate) {
 		dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
 		clk_disable_unprepare(cdns_phy->clk);
 		return -EINVAL;
 	}
 
+	switch (ref_clk_rate) {
+	case REF_CLK_19_2MHZ:
+		cdns_phy->ref_clk_rate = CLK_19_2_MHZ;
+		break;
+	case REF_CLK_25MHZ:
+		cdns_phy->ref_clk_rate = CLK_25_MHZ;
+		break;
+	case REF_CLK_100MHZ:
+		cdns_phy->ref_clk_rate = CLK_100_MHZ;
+		break;
+	default:
+		dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n");
+		clk_disable_unprepare(cdns_phy->clk);
+		return -EINVAL;
+	}
+
 	return 0;
 }
 
-- 
2.26.1

Re: [PATCH 03/14] phy: cadence-torrent: Add enum to support different input reference clocks

[Kishon Vijay Abraham I]

Hi Swapnil,

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Torrent PHY supports different input reference clock frequencies.
> Register configurations will be different based on reference clock value.
> Prepare driver to support register configs for multiple reference clocks.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>

$subject can be changed to something like "Add enum for supported input
reference clocks frequencies"

With that fixed
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 51 +++++++++++++++++------
>  1 file changed, 38 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index 6eeb753fbb78..252920ea7fdf 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -26,11 +26,13 @@
>  
>  #define REF_CLK_19_2MHZ		19200000
>  #define REF_CLK_25MHZ		25000000
> +#define REF_CLK_100MHZ		100000000
>  
>  #define MAX_NUM_LANES		4
>  #define DEFAULT_MAX_BIT_RATE	8100 /* in Mbps */
>  
>  #define NUM_SSC_MODE		3
> +#define NUM_REF_CLK		3
>  #define NUM_PHY_TYPE		6
>  
>  #define POLL_TIMEOUT_US		5000
> @@ -273,6 +275,12 @@ enum cdns_torrent_phy_type {
>  	TYPE_USB,
>  };
>  
> +enum cdns_torrent_ref_clk {
> +	CLK_19_2_MHZ,
> +	CLK_25_MHZ,
> +	CLK_100_MHZ
> +};
> +
>  enum cdns_torrent_ssc_mode {
>  	NO_SSC,
>  	EXTERNAL_SSC,
> @@ -296,7 +304,7 @@ struct cdns_torrent_phy {
>  	struct reset_control *apb_rst;
>  	struct device *dev;
>  	struct clk *clk;
> -	unsigned long ref_clk_rate;
> +	enum cdns_torrent_ref_clk ref_clk_rate;
>  	struct cdns_torrent_inst phys[MAX_NUM_LANES];
>  	int nsubnodes;
>  	const struct cdns_torrent_data *init_data;
> @@ -817,12 +825,12 @@ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
>  	ndelay(200);
>  
>  	/* DP Rate Change - VCO Output settings. */
> -	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ) {
> +	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) {
>  		/* PMA common configuration 19.2MHz */
>  		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
>  							dp->ssc);
>  		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
> -	} else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ) {
> +	} else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) {
>  		/* PMA common configuration 25MHz */
>  		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
>  						      dp->ssc);
> @@ -1165,8 +1173,8 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
>  
>  	switch (cdns_phy->ref_clk_rate) {
> -	case REF_CLK_19_2MHZ:
> -	case REF_CLK_25MHZ:
> +	case CLK_19_2_MHZ:
> +	case CLK_25_MHZ:
>  		/* Valid Ref Clock Rate */
>  		break;
>  	default:
> @@ -1198,11 +1206,11 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  
>  	/* PHY PMA registers configuration functions */
>  	/* Initialize PHY with max supported link rate, without SSC. */
> -	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
> +	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
>  		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
>  							cdns_phy->max_bit_rate,
>  							false);
> -	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
> +	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
>  		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
>  						      cdns_phy->max_bit_rate,
>  						      false);
> @@ -1228,10 +1236,10 @@ static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
>  {
>  	unsigned int i;
>  
> -	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
> +	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
>  		/* PMA common configuration 19.2MHz */
>  		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
> -	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
> +	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
>  		/* PMA common configuration 25MHz */
>  		cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
>  
> @@ -1636,10 +1644,10 @@ static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
>  					 unsigned int lane)
>  {
>  	/* Per lane, refclock-dependent receiver detection setting */
> -	if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHZ)
> +	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
>  		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
>  				       TX_RCVDET_ST_TMR, 0x0780);
> -	else if (cdns_phy->ref_clk_rate == REF_CLK_25MHZ)
> +	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
>  		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
>  				       TX_RCVDET_ST_TMR, 0x09C4);
>  
> @@ -2270,6 +2278,7 @@ static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy)
>  static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
>  {
>  	struct device *dev = cdns_phy->dev;
> +	unsigned long ref_clk_rate;
>  	int ret;
>  
>  	cdns_phy->clk = devm_clk_get(dev, "refclk");
> @@ -2284,13 +2293,29 @@ static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
>  		return ret;
>  	}
>  
> -	cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk);
> -	if (!(cdns_phy->ref_clk_rate)) {
> +	ref_clk_rate = clk_get_rate(cdns_phy->clk);
> +	if (!ref_clk_rate) {
>  		dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
>  		clk_disable_unprepare(cdns_phy->clk);
>  		return -EINVAL;
>  	}
>  
> +	switch (ref_clk_rate) {
> +	case REF_CLK_19_2MHZ:
> +		cdns_phy->ref_clk_rate = CLK_19_2_MHZ;
> +		break;
> +	case REF_CLK_25MHZ:
> +		cdns_phy->ref_clk_rate = CLK_25_MHZ;
> +		break;
> +	case REF_CLK_100MHZ:
> +		cdns_phy->ref_clk_rate = CLK_100_MHZ;
> +		break;
> +	default:
> +		dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n");
> +		clk_disable_unprepare(cdns_phy->clk);
> +		return -EINVAL;
> +	}
> +
>  	return 0;
>  }
>  
> 

[PATCH 04/14] phy: cadence-torrent: Select register configuration based on PHY reference clock

[Swapnil Jakhade]

Add PHY input reference clock frequency as a new dimension to select proper
register configuration.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 830 +++++++++++-----------
 1 file changed, 422 insertions(+), 408 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 252920ea7fdf..39a26a1a4c51 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -375,12 +375,12 @@ struct cdns_torrent_data {
 						[NUM_SSC_MODE];
 	struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 					      [NUM_SSC_MODE];
-	struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
-					  [NUM_SSC_MODE];
-	struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
-					    [NUM_SSC_MODE];
-	struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
-					    [NUM_SSC_MODE];
+	struct cdns_torrent_vals *cmn_vals[NUM_REF_CLK][NUM_PHY_TYPE]
+					  [NUM_PHY_TYPE][NUM_SSC_MODE];
+	struct cdns_torrent_vals *tx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
+					    [NUM_PHY_TYPE][NUM_SSC_MODE];
+	struct cdns_torrent_vals *rx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
+					    [NUM_PHY_TYPE][NUM_SSC_MODE];
 };
 
 struct cdns_regmap_cdb_context {
@@ -1958,6 +1958,7 @@ static int cdns_torrent_phy_init(struct phy *phy)
 	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
 	const struct cdns_torrent_data *init_data = cdns_phy->init_data;
 	struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
+	enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
 	struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
 	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
 	enum cdns_torrent_phy_type phy_type = inst->phy_type;
@@ -2023,7 +2024,7 @@ static int cdns_torrent_phy_init(struct phy *phy)
 	}
 
 	/* PMA common registers configurations */
-	cmn_vals = init_data->cmn_vals[phy_type][TYPE_NONE][ssc];
+	cmn_vals = init_data->cmn_vals[ref_clk][phy_type][TYPE_NONE][ssc];
 	if (cmn_vals) {
 		reg_pairs = cmn_vals->reg_pairs;
 		num_regs = cmn_vals->num_regs;
@@ -2034,7 +2035,7 @@ static int cdns_torrent_phy_init(struct phy *phy)
 	}
 
 	/* PMA TX lane registers configurations */
-	tx_ln_vals = init_data->tx_ln_vals[phy_type][TYPE_NONE][ssc];
+	tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
 	if (tx_ln_vals) {
 		reg_pairs = tx_ln_vals->reg_pairs;
 		num_regs = tx_ln_vals->num_regs;
@@ -2047,7 +2048,7 @@ static int cdns_torrent_phy_init(struct phy *phy)
 	}
 
 	/* PMA RX lane registers configurations */
-	rx_ln_vals = init_data->rx_ln_vals[phy_type][TYPE_NONE][ssc];
+	rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
 	if (rx_ln_vals) {
 		reg_pairs = rx_ln_vals->reg_pairs;
 		num_regs = rx_ln_vals->num_regs;
@@ -2088,6 +2089,7 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
 {
 	const struct cdns_torrent_data *init_data = cdns_phy->init_data;
 	struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
+	enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
 	struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
 	enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type;
 	struct cdns_torrent_vals *pcs_cmn_vals;
@@ -2176,7 +2178,7 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
 		}
 
 		/* PMA common registers configurations */
-		cmn_vals = init_data->cmn_vals[phy_t1][phy_t2][ssc];
+		cmn_vals = init_data->cmn_vals[ref_clk][phy_t1][phy_t2][ssc];
 		if (cmn_vals) {
 			reg_pairs = cmn_vals->reg_pairs;
 			num_regs = cmn_vals->num_regs;
@@ -2187,7 +2189,7 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
 		}
 
 		/* PMA TX lane registers configurations */
-		tx_ln_vals = init_data->tx_ln_vals[phy_t1][phy_t2][ssc];
+		tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
 		if (tx_ln_vals) {
 			reg_pairs = tx_ln_vals->reg_pairs;
 			num_regs = tx_ln_vals->num_regs;
@@ -2200,7 +2202,7 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
 		}
 
 		/* PMA RX lane registers configurations */
-		rx_ln_vals = init_data->rx_ln_vals[phy_t1][phy_t2][ssc];
+		rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
 		if (rx_ln_vals) {
 			reg_pairs = rx_ln_vals->reg_pairs;
 			num_regs = rx_ln_vals->num_regs;
@@ -3496,230 +3498,236 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 		},
 	},
 	.cmn_vals = {
-		[TYPE_PCIE] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = NULL,
-				[EXTERNAL_SSC] = NULL,
-				[INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
+		[CLK_100_MHZ] = {
+			[TYPE_PCIE] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = NULL,
+					[EXTERNAL_SSC] = NULL,
+					[INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
+				},
 			},
 			[TYPE_SGMII] = {
-				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
+				},
 			},
 			[TYPE_QSGMII] = {
-				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
-			},
-		},
-		[TYPE_SGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+				},
 			},
 			[TYPE_USB] = {
-				[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
-			},
-		},
-		[TYPE_QSGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
-			},
-		},
-		[TYPE_USB] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &usb_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
-			},
-			[TYPE_SGMII] = {
-				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
-			},
-			[TYPE_QSGMII] = {
-				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &usb_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
+				},
 			},
 		},
 	},
 	.tx_ln_vals = {
-		[TYPE_PCIE] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = NULL,
-				[EXTERNAL_SSC] = NULL,
-				[INTERNAL_SSC] = NULL,
+		[CLK_100_MHZ] = {
+			[TYPE_PCIE] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = NULL,
+					[EXTERNAL_SSC] = NULL,
+					[INTERNAL_SSC] = NULL,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = NULL,
+					[EXTERNAL_SSC] = NULL,
+					[INTERNAL_SSC] = NULL,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = NULL,
+					[EXTERNAL_SSC] = NULL,
+					[INTERNAL_SSC] = NULL,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = NULL,
+					[EXTERNAL_SSC] = NULL,
+					[INTERNAL_SSC] = NULL,
+				},
 			},
 			[TYPE_SGMII] = {
-				[NO_SSC] = NULL,
-				[EXTERNAL_SSC] = NULL,
-				[INTERNAL_SSC] = NULL,
+				[TYPE_NONE] = {
+					[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+				},
 			},
 			[TYPE_QSGMII] = {
-				[NO_SSC] = NULL,
-				[EXTERNAL_SSC] = NULL,
-				[INTERNAL_SSC] = NULL,
+				[TYPE_NONE] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+				},
 			},
 			[TYPE_USB] = {
-				[NO_SSC] = NULL,
-				[EXTERNAL_SSC] = NULL,
-				[INTERNAL_SSC] = NULL,
-			},
-		},
-		[TYPE_SGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
-			},
-		},
-		[TYPE_QSGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
-			},
-		},
-		[TYPE_USB] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_SGMII] = {
-				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_QSGMII] = {
-				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+				},
 			},
 		},
 	},
 	.rx_ln_vals = {
-		[TYPE_PCIE] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+		[CLK_100_MHZ] = {
+			[TYPE_PCIE] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				},
 			},
 			[TYPE_SGMII] = {
-				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+				},
 			},
 			[TYPE_QSGMII] = {
-				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-			},
-		},
-		[TYPE_SGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+				},
 			},
 			[TYPE_USB] = {
-				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-			},
-		},
-		[TYPE_QSGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-			},
-		},
-		[TYPE_USB] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_SGMII] = {
-				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_QSGMII] = {
-				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+				},
 			},
 		},
 	},
@@ -3905,230 +3913,236 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 		},
 	},
 	.cmn_vals = {
-		[TYPE_PCIE] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = NULL,
-				[EXTERNAL_SSC] = NULL,
-				[INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
+		[CLK_100_MHZ] = {
+			[TYPE_PCIE] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = NULL,
+					[EXTERNAL_SSC] = NULL,
+					[INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
+				},
 			},
 			[TYPE_SGMII] = {
-				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
+				},
 			},
 			[TYPE_QSGMII] = {
-				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
-			},
-		},
-		[TYPE_SGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+				},
 			},
 			[TYPE_USB] = {
-				[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
-			},
-		},
-		[TYPE_QSGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
-			},
-		},
-		[TYPE_USB] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &usb_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
-			},
-			[TYPE_SGMII] = {
-				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
-			},
-			[TYPE_QSGMII] = {
-				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
-				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &usb_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
+					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
+				},
 			},
 		},
 	},
 	.tx_ln_vals = {
-		[TYPE_PCIE] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = NULL,
-				[EXTERNAL_SSC] = NULL,
-				[INTERNAL_SSC] = NULL,
+		[CLK_100_MHZ] = {
+			[TYPE_PCIE] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = NULL,
+					[EXTERNAL_SSC] = NULL,
+					[INTERNAL_SSC] = NULL,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = NULL,
+					[EXTERNAL_SSC] = NULL,
+					[INTERNAL_SSC] = NULL,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = NULL,
+					[EXTERNAL_SSC] = NULL,
+					[INTERNAL_SSC] = NULL,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = NULL,
+					[EXTERNAL_SSC] = NULL,
+					[INTERNAL_SSC] = NULL,
+				},
 			},
 			[TYPE_SGMII] = {
-				[NO_SSC] = NULL,
-				[EXTERNAL_SSC] = NULL,
-				[INTERNAL_SSC] = NULL,
+				[TYPE_NONE] = {
+					[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
+				},
 			},
 			[TYPE_QSGMII] = {
-				[NO_SSC] = NULL,
-				[EXTERNAL_SSC] = NULL,
-				[INTERNAL_SSC] = NULL,
+				[TYPE_NONE] = {
+					[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
+				},
 			},
 			[TYPE_USB] = {
-				[NO_SSC] = NULL,
-				[EXTERNAL_SSC] = NULL,
-				[INTERNAL_SSC] = NULL,
-			},
-		},
-		[TYPE_SGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
-			},
-		},
-		[TYPE_QSGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
-			},
-		},
-		[TYPE_USB] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_SGMII] = {
-				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-			},
-			[TYPE_QSGMII] = {
-				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
+				},
 			},
 		},
 	},
 	.rx_ln_vals = {
-		[TYPE_PCIE] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+		[CLK_100_MHZ] = {
+			[TYPE_PCIE] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				},
 			},
 			[TYPE_SGMII] = {
-				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+				},
 			},
 			[TYPE_QSGMII] = {
-				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-			},
-		},
-		[TYPE_SGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_USB] = {
+					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+				},
 			},
 			[TYPE_USB] = {
-				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
-			},
-		},
-		[TYPE_QSGMII] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_USB] = {
-				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
-			},
-		},
-		[TYPE_USB] = {
-			[TYPE_NONE] = {
-				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_PCIE] = {
-				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_SGMII] = {
-				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-			},
-			[TYPE_QSGMII] = {
-				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
-				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+				[TYPE_NONE] = {
+					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_SGMII] = {
+					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+				},
+				[TYPE_QSGMII] = {
+					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
+				},
 			},
 		},
 	},
-- 
2.26.1

Re: [PATCH 04/14] phy: cadence-torrent: Select register configuration based on PHY reference clock

[Kishon Vijay Abraham I]

Hi Swapnil,

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Add PHY input reference clock frequency as a new dimension to select proper
> register configuration.

Please add additional details in the commit message here as to why you
are doing this change and also mention you don't expect any functional
change with this patch.

Thanks
Kishon
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 830 +++++++++++-----------
>  1 file changed, 422 insertions(+), 408 deletions(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index 252920ea7fdf..39a26a1a4c51 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -375,12 +375,12 @@ struct cdns_torrent_data {
>  						[NUM_SSC_MODE];
>  	struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
>  					      [NUM_SSC_MODE];
> -	struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
> -					  [NUM_SSC_MODE];
> -	struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
> -					    [NUM_SSC_MODE];
> -	struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
> -					    [NUM_SSC_MODE];
> +	struct cdns_torrent_vals *cmn_vals[NUM_REF_CLK][NUM_PHY_TYPE]
> +					  [NUM_PHY_TYPE][NUM_SSC_MODE];
> +	struct cdns_torrent_vals *tx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
> +					    [NUM_PHY_TYPE][NUM_SSC_MODE];
> +	struct cdns_torrent_vals *rx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
> +					    [NUM_PHY_TYPE][NUM_SSC_MODE];
>  };
>  
>  struct cdns_regmap_cdb_context {
> @@ -1958,6 +1958,7 @@ static int cdns_torrent_phy_init(struct phy *phy)
>  	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
>  	const struct cdns_torrent_data *init_data = cdns_phy->init_data;
>  	struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
> +	enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
>  	struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
>  	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
>  	enum cdns_torrent_phy_type phy_type = inst->phy_type;
> @@ -2023,7 +2024,7 @@ static int cdns_torrent_phy_init(struct phy *phy)
>  	}
>  
>  	/* PMA common registers configurations */
> -	cmn_vals = init_data->cmn_vals[phy_type][TYPE_NONE][ssc];
> +	cmn_vals = init_data->cmn_vals[ref_clk][phy_type][TYPE_NONE][ssc];
>  	if (cmn_vals) {
>  		reg_pairs = cmn_vals->reg_pairs;
>  		num_regs = cmn_vals->num_regs;
> @@ -2034,7 +2035,7 @@ static int cdns_torrent_phy_init(struct phy *phy)
>  	}
>  
>  	/* PMA TX lane registers configurations */
> -	tx_ln_vals = init_data->tx_ln_vals[phy_type][TYPE_NONE][ssc];
> +	tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
>  	if (tx_ln_vals) {
>  		reg_pairs = tx_ln_vals->reg_pairs;
>  		num_regs = tx_ln_vals->num_regs;
> @@ -2047,7 +2048,7 @@ static int cdns_torrent_phy_init(struct phy *phy)
>  	}
>  
>  	/* PMA RX lane registers configurations */
> -	rx_ln_vals = init_data->rx_ln_vals[phy_type][TYPE_NONE][ssc];
> +	rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
>  	if (rx_ln_vals) {
>  		reg_pairs = rx_ln_vals->reg_pairs;
>  		num_regs = rx_ln_vals->num_regs;
> @@ -2088,6 +2089,7 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
>  {
>  	const struct cdns_torrent_data *init_data = cdns_phy->init_data;
>  	struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
> +	enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
>  	struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
>  	enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type;
>  	struct cdns_torrent_vals *pcs_cmn_vals;
> @@ -2176,7 +2178,7 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
>  		}
>  
>  		/* PMA common registers configurations */
> -		cmn_vals = init_data->cmn_vals[phy_t1][phy_t2][ssc];
> +		cmn_vals = init_data->cmn_vals[ref_clk][phy_t1][phy_t2][ssc];
>  		if (cmn_vals) {
>  			reg_pairs = cmn_vals->reg_pairs;
>  			num_regs = cmn_vals->num_regs;
> @@ -2187,7 +2189,7 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
>  		}
>  
>  		/* PMA TX lane registers configurations */
> -		tx_ln_vals = init_data->tx_ln_vals[phy_t1][phy_t2][ssc];
> +		tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
>  		if (tx_ln_vals) {
>  			reg_pairs = tx_ln_vals->reg_pairs;
>  			num_regs = tx_ln_vals->num_regs;
> @@ -2200,7 +2202,7 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
>  		}
>  
>  		/* PMA RX lane registers configurations */
> -		rx_ln_vals = init_data->rx_ln_vals[phy_t1][phy_t2][ssc];
> +		rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
>  		if (rx_ln_vals) {
>  			reg_pairs = rx_ln_vals->reg_pairs;
>  			num_regs = rx_ln_vals->num_regs;
> @@ -3496,230 +3498,236 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  		},
>  	},
>  	.cmn_vals = {
> -		[TYPE_PCIE] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = NULL,
> -				[EXTERNAL_SSC] = NULL,
> -				[INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
> +		[CLK_100_MHZ] = {
> +			[TYPE_PCIE] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = NULL,
> +					[EXTERNAL_SSC] = NULL,
> +					[INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> +				},
>  			},
>  			[TYPE_SGMII] = {
> -				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> +				},
>  			},
>  			[TYPE_QSGMII] = {
> -				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> -			},
> -		},
> -		[TYPE_SGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> +				},
>  			},
>  			[TYPE_USB] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> -			},
> -		},
> -		[TYPE_QSGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> -			},
> -		},
> -		[TYPE_USB] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &usb_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
> -			},
> -			[TYPE_SGMII] = {
> -				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> -			},
> -			[TYPE_QSGMII] = {
> -				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &usb_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> +				},
>  			},
>  		},
>  	},
>  	.tx_ln_vals = {
> -		[TYPE_PCIE] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = NULL,
> -				[EXTERNAL_SSC] = NULL,
> -				[INTERNAL_SSC] = NULL,
> +		[CLK_100_MHZ] = {
> +			[TYPE_PCIE] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = NULL,
> +					[EXTERNAL_SSC] = NULL,
> +					[INTERNAL_SSC] = NULL,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = NULL,
> +					[EXTERNAL_SSC] = NULL,
> +					[INTERNAL_SSC] = NULL,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = NULL,
> +					[EXTERNAL_SSC] = NULL,
> +					[INTERNAL_SSC] = NULL,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = NULL,
> +					[EXTERNAL_SSC] = NULL,
> +					[INTERNAL_SSC] = NULL,
> +				},
>  			},
>  			[TYPE_SGMII] = {
> -				[NO_SSC] = NULL,
> -				[EXTERNAL_SSC] = NULL,
> -				[INTERNAL_SSC] = NULL,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> +				},
>  			},
>  			[TYPE_QSGMII] = {
> -				[NO_SSC] = NULL,
> -				[EXTERNAL_SSC] = NULL,
> -				[INTERNAL_SSC] = NULL,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> +				},
>  			},
>  			[TYPE_USB] = {
> -				[NO_SSC] = NULL,
> -				[EXTERNAL_SSC] = NULL,
> -				[INTERNAL_SSC] = NULL,
> -			},
> -		},
> -		[TYPE_SGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
> -			},
> -		},
> -		[TYPE_QSGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
> -			},
> -		},
> -		[TYPE_USB] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_SGMII] = {
> -				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_QSGMII] = {
> -				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +				},
>  			},
>  		},
>  	},
>  	.rx_ln_vals = {
> -		[TYPE_PCIE] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +		[CLK_100_MHZ] = {
> +			[TYPE_PCIE] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  			[TYPE_SGMII] = {
> -				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  			[TYPE_QSGMII] = {
> -				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -			},
> -		},
> -		[TYPE_SGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  			[TYPE_USB] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -			},
> -		},
> -		[TYPE_QSGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -			},
> -		},
> -		[TYPE_USB] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_SGMII] = {
> -				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_QSGMII] = {
> -				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  		},
>  	},
> @@ -3905,230 +3913,236 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  		},
>  	},
>  	.cmn_vals = {
> -		[TYPE_PCIE] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = NULL,
> -				[EXTERNAL_SSC] = NULL,
> -				[INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
> +		[CLK_100_MHZ] = {
> +			[TYPE_PCIE] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = NULL,
> +					[EXTERNAL_SSC] = NULL,
> +					[INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> +				},
>  			},
>  			[TYPE_SGMII] = {
> -				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> +				},
>  			},
>  			[TYPE_QSGMII] = {
> -				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
> -			},
> -		},
> -		[TYPE_SGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> +				},
>  			},
>  			[TYPE_USB] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
> -			},
> -		},
> -		[TYPE_QSGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
> -			},
> -		},
> -		[TYPE_USB] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &usb_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
> -			},
> -			[TYPE_SGMII] = {
> -				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> -			},
> -			[TYPE_QSGMII] = {
> -				[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> -				[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &usb_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
> +					[INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
> +				},
>  			},
>  		},
>  	},
>  	.tx_ln_vals = {
> -		[TYPE_PCIE] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = NULL,
> -				[EXTERNAL_SSC] = NULL,
> -				[INTERNAL_SSC] = NULL,
> +		[CLK_100_MHZ] = {
> +			[TYPE_PCIE] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = NULL,
> +					[EXTERNAL_SSC] = NULL,
> +					[INTERNAL_SSC] = NULL,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = NULL,
> +					[EXTERNAL_SSC] = NULL,
> +					[INTERNAL_SSC] = NULL,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = NULL,
> +					[EXTERNAL_SSC] = NULL,
> +					[INTERNAL_SSC] = NULL,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = NULL,
> +					[EXTERNAL_SSC] = NULL,
> +					[INTERNAL_SSC] = NULL,
> +				},
>  			},
>  			[TYPE_SGMII] = {
> -				[NO_SSC] = NULL,
> -				[EXTERNAL_SSC] = NULL,
> -				[INTERNAL_SSC] = NULL,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> +				},
>  			},
>  			[TYPE_QSGMII] = {
> -				[NO_SSC] = NULL,
> -				[EXTERNAL_SSC] = NULL,
> -				[INTERNAL_SSC] = NULL,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> +				},
>  			},
>  			[TYPE_USB] = {
> -				[NO_SSC] = NULL,
> -				[EXTERNAL_SSC] = NULL,
> -				[INTERNAL_SSC] = NULL,
> -			},
> -		},
> -		[TYPE_SGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
> -			},
> -		},
> -		[TYPE_QSGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
> -			},
> -		},
> -		[TYPE_USB] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_SGMII] = {
> -				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -			},
> -			[TYPE_QSGMII] = {
> -				[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
> +				},
>  			},
>  		},
>  	},
>  	.rx_ln_vals = {
> -		[TYPE_PCIE] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +		[CLK_100_MHZ] = {
> +			[TYPE_PCIE] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  			[TYPE_SGMII] = {
> -				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  			[TYPE_QSGMII] = {
> -				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> -			},
> -		},
> -		[TYPE_SGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_USB] = {
> +					[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  			[TYPE_USB] = {
> -				[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
> -			},
> -		},
> -		[TYPE_QSGMII] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_USB] = {
> -				[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
> -			},
> -		},
> -		[TYPE_USB] = {
> -			[TYPE_NONE] = {
> -				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_PCIE] = {
> -				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_SGMII] = {
> -				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -			},
> -			[TYPE_QSGMII] = {
> -				[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> -				[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_SGMII] = {
> +					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +				},
> +				[TYPE_QSGMII] = {
> +					[NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +					[INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  		},
>  	},
> 

[PATCH 05/14] phy: cadence-torrent: Add PHY registers for DP in array format

[Swapnil Jakhade]

Add PHY registers for single link DP in array format to simplify
code and to improve readability.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 450 +++++++++++++---------
 1 file changed, 274 insertions(+), 176 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 39a26a1a4c51..4ec5909f192c 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -341,20 +341,12 @@ struct cdns_torrent_derived_refclk {
 #define to_cdns_torrent_derived_refclk(_hw)	\
 			container_of(_hw, struct cdns_torrent_derived_refclk, hw)
 
-static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
-				    struct cdns_torrent_inst *inst);
-static
-void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy);
 static
 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
 					     u32 rate, bool ssc);
 static
-void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
-static
 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
 					   u32 rate, bool ssc);
-static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
-					 unsigned int lane);
 
 struct cdns_reg_pairs {
 	u32 val;
@@ -759,9 +751,6 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
 	unsigned int hsclk_div_val = 0;
 	unsigned int i;
 
-	/* 16'h0000 for single DP link configuration */
-	regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
-
 	switch (rate) {
 	case 1620:
 		clk_sel_val = 0x0f01;
@@ -806,8 +795,7 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
 static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
 					  struct phy_configure_opts_dp *dp)
 {
-	u32 ret;
-	u32 read_val;
+	u32 read_val, ret;
 
 	/* Disable the cmn_pll0_en before re-programming the new data rate. */
 	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
@@ -825,17 +813,12 @@ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
 	ndelay(200);
 
 	/* DP Rate Change - VCO Output settings. */
-	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) {
+	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
 		/* PMA common configuration 19.2MHz */
-		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
-							dp->ssc);
-		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
-	} else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) {
+		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
+	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
 		/* PMA common configuration 25MHz */
-		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
-						      dp->ssc);
-		cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
-	}
+		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
 	cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
 
 	/* Enable the cmn_pll0_en. */
@@ -1184,9 +1167,6 @@ static int cdns_torrent_dp_init(struct phy *phy)
 
 	cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
 
-	/* PHY PMA registers configuration function */
-	cdns_torrent_dp_pma_cfg(cdns_phy, inst);
-
 	/*
 	 * Set lines power state to A0
 	 * Set lines pll clk enable to 0
@@ -1231,67 +1211,6 @@ static int cdns_torrent_dp_init(struct phy *phy)
 	return ret;
 }
 
-static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
-				    struct cdns_torrent_inst *inst)
-{
-	unsigned int i;
-
-	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
-		/* PMA common configuration 19.2MHz */
-		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
-	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
-		/* PMA common configuration 25MHz */
-		cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
-
-	/* PMA lane configuration to deal with multi-link operation */
-	for (i = 0; i < inst->num_lanes; i++)
-		cdns_torrent_dp_pma_lane_cfg(cdns_phy, i);
-}
-
-static
-void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy)
-{
-	struct regmap *regmap = cdns_phy->regmap_common_cdb;
-
-	/* refclock registers - assumes 19.2 MHz refclock */
-	cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0014);
-	cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0027);
-	cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1);
-	cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0027);
-	cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1);
-	cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x0060);
-	cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x0060);
-	cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0014);
-	cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x0018);
-	cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0005);
-	cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x0018);
-	cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0005);
-	cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x0240);
-	cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0005);
-	cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
-	cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
-	cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000B);
-	cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x0137);
-
-	/* PLL registers */
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
-}
-
 /*
  * Set registers responsible for enabling and configuring SSC, with second and
  * third register values provided by parameters.
@@ -1473,50 +1392,6 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
 	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
 }
 
-static
-void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy)
-{
-	struct regmap *regmap = cdns_phy->regmap_common_cdb;
-
-	/* refclock registers - assumes 25 MHz refclock */
-	cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0019);
-	cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0032);
-	cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1);
-	cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0032);
-	cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1);
-	cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x007D);
-	cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x007D);
-	cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0019);
-	cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x001E);
-	cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0006);
-	cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x001E);
-	cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0006);
-	cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x02EE);
-	cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0006);
-	cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
-	cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
-	cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000E);
-	cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x012B);
-
-	/* PLL registers */
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
-}
-
 /*
  * Set registers responsible for enabling and configuring SSC, with second
  * register value provided by a parameter.
@@ -1640,49 +1515,6 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
 	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
 }
 
-static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
-					 unsigned int lane)
-{
-	/* Per lane, refclock-dependent receiver detection setting */
-	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
-		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
-				       TX_RCVDET_ST_TMR, 0x0780);
-	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
-		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
-				       TX_RCVDET_ST_TMR, 0x09C4);
-
-	/* Writing Tx/Rx Power State Controllers registers */
-	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
-			       TX_PSC_A0, 0x00FB);
-	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
-			       TX_PSC_A2, 0x04AA);
-	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
-			       TX_PSC_A3, 0x04AA);
-	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
-			       RX_PSC_A0, 0x0000);
-	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
-			       RX_PSC_A2, 0x0000);
-	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
-			       RX_PSC_A3, 0x0000);
-
-	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
-			       RX_PSC_CAL, 0x0000);
-
-	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
-			       RX_REE_GCSM1_CTRL, 0x0000);
-	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
-			       RX_REE_GCSM2_CTRL, 0x0000);
-	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
-			       RX_REE_PERGCSM_CTRL, 0x0000);
-
-	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
-			       XCVR_DIAG_BIDI_CTRL, 0x000F);
-	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
-			       XCVR_DIAG_PLLDRC_CTRL, 0x0001);
-	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
-			       XCVR_DIAG_HSCLK_SEL, 0x0000);
-}
-
 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
 {
 	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
@@ -1972,9 +1804,6 @@ static int cdns_torrent_phy_init(struct phy *phy)
 	if (cdns_phy->nsubnodes > 1)
 		return 0;
 
-	if (phy_type == TYPE_DP)
-		return cdns_torrent_dp_init(phy);
-
 	/**
 	 * Spread spectrum generation is not required or supported
 	 * for SGMII/QSGMII
@@ -2060,6 +1889,9 @@ static int cdns_torrent_phy_init(struct phy *phy)
 		}
 	}
 
+	if (phy_type == TYPE_DP)
+		return cdns_torrent_dp_init(phy);
+
 	return 0;
 }
 
@@ -2584,6 +2416,168 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev)
 	return 0;
 }
 
+/* Single DisplayPort(DP) link configuration */
+static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {
+	{0x0000, PHY_PLL_CFG},
+};
+
+static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = {
+	{0x0000, XCVR_DIAG_HSCLK_SEL},
+	{0x0001, XCVR_DIAG_PLLDRC_CTRL}
+};
+
+static struct cdns_torrent_vals sl_dp_link_cmn_vals = {
+	.reg_pairs = sl_dp_link_cmn_regs,
+	.num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs),
+};
+
+static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = {
+	.reg_pairs = sl_dp_xcvr_diag_ln_regs,
+	.num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs),
+};
+
+/* Single DP, 19.2 MHz Ref clk, no SSC */
+static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = {
+	{0x0014, CMN_SSM_BIAS_TMR},
+	{0x0027, CMN_PLLSM0_PLLPRE_TMR},
+	{0x00A1, CMN_PLLSM0_PLLLOCK_TMR},
+	{0x0027, CMN_PLLSM1_PLLPRE_TMR},
+	{0x00A1, CMN_PLLSM1_PLLLOCK_TMR},
+	{0x0060, CMN_BGCAL_INIT_TMR},
+	{0x0060, CMN_BGCAL_ITER_TMR},
+	{0x0014, CMN_IBCAL_INIT_TMR},
+	{0x0018, CMN_TXPUCAL_INIT_TMR},
+	{0x0005, CMN_TXPUCAL_ITER_TMR},
+	{0x0018, CMN_TXPDCAL_INIT_TMR},
+	{0x0005, CMN_TXPDCAL_ITER_TMR},
+	{0x0240, CMN_RXCAL_INIT_TMR},
+	{0x0005, CMN_RXCAL_ITER_TMR},
+	{0x0002, CMN_SD_CAL_INIT_TMR},
+	{0x0002, CMN_SD_CAL_ITER_TMR},
+	{0x000B, CMN_SD_CAL_REFTIM_START},
+	{0x0137, CMN_SD_CAL_PLLCNT_START},
+	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
+	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
+	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
+	{0x0004, CMN_PLL0_DSM_DIAG_M0},
+	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
+	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
+	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
+	{0x0004, CMN_PLL1_DSM_DIAG_M0},
+	{0x00C0, CMN_PLL0_VCOCAL_INIT_TMR},
+	{0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
+	{0x00C0, CMN_PLL1_VCOCAL_INIT_TMR},
+	{0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
+	{0x0260, CMN_PLL0_VCOCAL_REFTIM_START},
+	{0x0003, CMN_PLL0_VCOCAL_TCTRL},
+	{0x0260, CMN_PLL1_VCOCAL_REFTIM_START},
+	{0x0003, CMN_PLL1_VCOCAL_TCTRL}
+};
+
+static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = {
+	{0x0780, TX_RCVDET_ST_TMR},
+	{0x00FB, TX_PSC_A0},
+	{0x04AA, TX_PSC_A2},
+	{0x04AA, TX_PSC_A3},
+	{0x000F, XCVR_DIAG_BIDI_CTRL}
+};
+
+static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = {
+	{0x0000, RX_PSC_A0},
+	{0x0000, RX_PSC_A2},
+	{0x0000, RX_PSC_A3},
+	{0x0000, RX_PSC_CAL},
+	{0x0000, RX_REE_GCSM1_CTRL},
+	{0x0000, RX_REE_GCSM2_CTRL},
+	{0x0000, RX_REE_PERGCSM_CTRL}
+};
+
+static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = {
+	.reg_pairs = sl_dp_19_2_no_ssc_cmn_regs,
+	.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs),
+};
+
+static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = {
+	.reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs,
+	.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs),
+};
+
+static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = {
+	.reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs,
+	.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs),
+};
+
+/* Single DP, 25 MHz Ref clk, no SSC */
+static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = {
+	{0x0019, CMN_SSM_BIAS_TMR},
+	{0x0032, CMN_PLLSM0_PLLPRE_TMR},
+	{0x00D1, CMN_PLLSM0_PLLLOCK_TMR},
+	{0x0032, CMN_PLLSM1_PLLPRE_TMR},
+	{0x00D1, CMN_PLLSM1_PLLLOCK_TMR},
+	{0x007D, CMN_BGCAL_INIT_TMR},
+	{0x007D, CMN_BGCAL_ITER_TMR},
+	{0x0019, CMN_IBCAL_INIT_TMR},
+	{0x001E, CMN_TXPUCAL_INIT_TMR},
+	{0x0006, CMN_TXPUCAL_ITER_TMR},
+	{0x001E, CMN_TXPDCAL_INIT_TMR},
+	{0x0006, CMN_TXPDCAL_ITER_TMR},
+	{0x02EE, CMN_RXCAL_INIT_TMR},
+	{0x0006, CMN_RXCAL_ITER_TMR},
+	{0x0002, CMN_SD_CAL_INIT_TMR},
+	{0x0002, CMN_SD_CAL_ITER_TMR},
+	{0x000E, CMN_SD_CAL_REFTIM_START},
+	{0x012B, CMN_SD_CAL_PLLCNT_START},
+	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
+	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
+	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
+	{0x0004, CMN_PLL0_DSM_DIAG_M0},
+	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
+	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
+	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
+	{0x0004, CMN_PLL1_DSM_DIAG_M0},
+	{0x00FA, CMN_PLL0_VCOCAL_INIT_TMR},
+	{0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
+	{0x00FA, CMN_PLL1_VCOCAL_INIT_TMR},
+	{0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
+	{0x0317, CMN_PLL0_VCOCAL_REFTIM_START},
+	{0x0003, CMN_PLL0_VCOCAL_TCTRL},
+	{0x0317, CMN_PLL1_VCOCAL_REFTIM_START},
+	{0x0003, CMN_PLL1_VCOCAL_TCTRL}
+};
+
+static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = {
+	{0x09C4, TX_RCVDET_ST_TMR},
+	{0x00FB, TX_PSC_A0},
+	{0x04AA, TX_PSC_A2},
+	{0x04AA, TX_PSC_A3},
+	{0x000F, XCVR_DIAG_BIDI_CTRL}
+};
+
+static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = {
+	{0x0000, RX_PSC_A0},
+	{0x0000, RX_PSC_A2},
+	{0x0000, RX_PSC_A3},
+	{0x0000, RX_PSC_CAL},
+	{0x0000, RX_REE_GCSM1_CTRL},
+	{0x0000, RX_REE_GCSM2_CTRL},
+	{0x0000, RX_REE_PERGCSM_CTRL}
+};
+
+static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = {
+	.reg_pairs = sl_dp_25_no_ssc_cmn_regs,
+	.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs),
+};
+
+static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = {
+	.reg_pairs = sl_dp_25_no_ssc_tx_ln_regs,
+	.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs),
+};
+
+static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {
+	.reg_pairs = sl_dp_25_no_ssc_rx_ln_regs,
+	.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),
+};
+
 /* USB and SGMII/QSGMII link configuration */
 static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
 	{0x0002, PHY_PLL_CFG},
@@ -3322,6 +3316,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 	.block_offset_shift = 0x2,
 	.reg_offset_shift = 0x2,
 	.link_cmn_vals = {
+		[TYPE_DP] = {
+			[TYPE_NONE] = {
+				[NO_SSC] = &sl_dp_link_cmn_vals,
+			},
+		},
 		[TYPE_PCIE] = {
 			[TYPE_NONE] = {
 				[NO_SSC] = NULL,
@@ -3398,6 +3397,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 		},
 	},
 	.xcvr_diag_vals = {
+		[TYPE_DP] = {
+			[TYPE_NONE] = {
+				[NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
+			},
+		},
 		[TYPE_PCIE] = {
 			[TYPE_NONE] = {
 				[NO_SSC] = NULL,
@@ -3498,6 +3502,20 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 		},
 	},
 	.cmn_vals = {
+		[CLK_19_2_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
+				},
+			},
+		},
+		[CLK_25_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
+				},
+			},
+		},
 		[CLK_100_MHZ] = {
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
@@ -3576,6 +3594,20 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 		},
 	},
 	.tx_ln_vals = {
+		[CLK_19_2_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
+				},
+			},
+		},
+		[CLK_25_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
+				},
+			},
+		},
 		[CLK_100_MHZ] = {
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
@@ -3654,6 +3686,20 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 		},
 	},
 	.rx_ln_vals = {
+		[CLK_19_2_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
+				},
+			},
+		},
+		[CLK_25_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
+				},
+			},
+		},
 		[CLK_100_MHZ] = {
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
@@ -3737,6 +3783,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 	.block_offset_shift = 0x0,
 	.reg_offset_shift = 0x1,
 	.link_cmn_vals = {
+		[TYPE_DP] = {
+			[TYPE_NONE] = {
+				[NO_SSC] = &sl_dp_link_cmn_vals,
+			},
+		},
 		[TYPE_PCIE] = {
 			[TYPE_NONE] = {
 				[NO_SSC] = NULL,
@@ -3813,6 +3864,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 		},
 	},
 	.xcvr_diag_vals = {
+		[TYPE_DP] = {
+			[TYPE_NONE] = {
+				[NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
+			},
+		},
 		[TYPE_PCIE] = {
 			[TYPE_NONE] = {
 				[NO_SSC] = NULL,
@@ -3913,6 +3969,20 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 		},
 	},
 	.cmn_vals = {
+		[CLK_19_2_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
+				},
+			},
+		},
+		[CLK_25_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
+				},
+			},
+		},
 		[CLK_100_MHZ] = {
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
@@ -3991,6 +4061,20 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 		},
 	},
 	.tx_ln_vals = {
+		[CLK_19_2_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
+				},
+			},
+		},
+		[CLK_25_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
+				},
+			},
+		},
 		[CLK_100_MHZ] = {
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
@@ -4069,6 +4153,20 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 		},
 	},
 	.rx_ln_vals = {
+		[CLK_19_2_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
+				},
+			},
+		},
+		[CLK_25_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
+				},
+			},
+		},
 		[CLK_100_MHZ] = {
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
-- 
2.26.1

Re: [PATCH 05/14] phy: cadence-torrent: Add PHY registers for DP in array format

[Kishon Vijay Abraham I]

Hi Swapnil,

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Add PHY registers for single link DP in array format to simplify
> code and to improve readability.

Please mention this supports already supported frequencies of 19.2MHz
and 25MHz.

Was this tested both with 19.2MHz and 25MHz?

Thanks
Kishon

> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 450 +++++++++++++---------
>  1 file changed, 274 insertions(+), 176 deletions(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index 39a26a1a4c51..4ec5909f192c 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -341,20 +341,12 @@ struct cdns_torrent_derived_refclk {
>  #define to_cdns_torrent_derived_refclk(_hw)	\
>  			container_of(_hw, struct cdns_torrent_derived_refclk, hw)
>  
> -static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
> -				    struct cdns_torrent_inst *inst);
> -static
> -void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy);
>  static
>  void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
>  					     u32 rate, bool ssc);
>  static
> -void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
> -static
>  void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
>  					   u32 rate, bool ssc);
> -static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
> -					 unsigned int lane);
>  
>  struct cdns_reg_pairs {
>  	u32 val;
> @@ -759,9 +751,6 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
>  	unsigned int hsclk_div_val = 0;
>  	unsigned int i;
>  
> -	/* 16'h0000 for single DP link configuration */
> -	regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
> -
>  	switch (rate) {
>  	case 1620:
>  		clk_sel_val = 0x0f01;
> @@ -806,8 +795,7 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
>  static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
>  					  struct phy_configure_opts_dp *dp)
>  {
> -	u32 ret;
> -	u32 read_val;
> +	u32 read_val, ret;
>  
>  	/* Disable the cmn_pll0_en before re-programming the new data rate. */
>  	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
> @@ -825,17 +813,12 @@ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
>  	ndelay(200);
>  
>  	/* DP Rate Change - VCO Output settings. */
> -	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) {
> +	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
>  		/* PMA common configuration 19.2MHz */
> -		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
> -							dp->ssc);
> -		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
> -	} else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) {
> +		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
> +	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
>  		/* PMA common configuration 25MHz */
> -		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
> -						      dp->ssc);
> -		cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
> -	}
> +		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
>  	cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
>  
>  	/* Enable the cmn_pll0_en. */
> @@ -1184,9 +1167,6 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  
>  	cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
>  
> -	/* PHY PMA registers configuration function */
> -	cdns_torrent_dp_pma_cfg(cdns_phy, inst);
> -
>  	/*
>  	 * Set lines power state to A0
>  	 * Set lines pll clk enable to 0
> @@ -1231,67 +1211,6 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  	return ret;
>  }
>  
> -static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
> -				    struct cdns_torrent_inst *inst)
> -{
> -	unsigned int i;
> -
> -	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
> -		/* PMA common configuration 19.2MHz */
> -		cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
> -	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
> -		/* PMA common configuration 25MHz */
> -		cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
> -
> -	/* PMA lane configuration to deal with multi-link operation */
> -	for (i = 0; i < inst->num_lanes; i++)
> -		cdns_torrent_dp_pma_lane_cfg(cdns_phy, i);
> -}
> -
> -static
> -void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy)
> -{
> -	struct regmap *regmap = cdns_phy->regmap_common_cdb;
> -
> -	/* refclock registers - assumes 19.2 MHz refclock */
> -	cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0014);
> -	cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0027);
> -	cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1);
> -	cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0027);
> -	cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1);
> -	cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x0060);
> -	cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x0060);
> -	cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0014);
> -	cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x0018);
> -	cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0005);
> -	cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x0018);
> -	cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0005);
> -	cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x0240);
> -	cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0005);
> -	cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
> -	cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
> -	cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000B);
> -	cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x0137);
> -
> -	/* PLL registers */
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
> -	cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
> -	cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
> -	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0);
> -	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
> -	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0);
> -	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
> -	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260);
> -	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
> -	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260);
> -	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
> -}
> -
>  /*
>   * Set registers responsible for enabling and configuring SSC, with second and
>   * third register values provided by parameters.
> @@ -1473,50 +1392,6 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
>  	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
>  }
>  
> -static
> -void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy)
> -{
> -	struct regmap *regmap = cdns_phy->regmap_common_cdb;
> -
> -	/* refclock registers - assumes 25 MHz refclock */
> -	cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0019);
> -	cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0032);
> -	cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1);
> -	cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0032);
> -	cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1);
> -	cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x007D);
> -	cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x007D);
> -	cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0019);
> -	cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x001E);
> -	cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0006);
> -	cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x001E);
> -	cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0006);
> -	cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x02EE);
> -	cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0006);
> -	cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
> -	cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
> -	cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000E);
> -	cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x012B);
> -
> -	/* PLL registers */
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
> -	cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
> -	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
> -	cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
> -	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA);
> -	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
> -	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA);
> -	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
> -	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317);
> -	cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
> -	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317);
> -	cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
> -}
> -
>  /*
>   * Set registers responsible for enabling and configuring SSC, with second
>   * register value provided by a parameter.
> @@ -1640,49 +1515,6 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
>  	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
>  }
>  
> -static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
> -					 unsigned int lane)
> -{
> -	/* Per lane, refclock-dependent receiver detection setting */
> -	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
> -		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> -				       TX_RCVDET_ST_TMR, 0x0780);
> -	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
> -		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> -				       TX_RCVDET_ST_TMR, 0x09C4);
> -
> -	/* Writing Tx/Rx Power State Controllers registers */
> -	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> -			       TX_PSC_A0, 0x00FB);
> -	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> -			       TX_PSC_A2, 0x04AA);
> -	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> -			       TX_PSC_A3, 0x04AA);
> -	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
> -			       RX_PSC_A0, 0x0000);
> -	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
> -			       RX_PSC_A2, 0x0000);
> -	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
> -			       RX_PSC_A3, 0x0000);
> -
> -	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
> -			       RX_PSC_CAL, 0x0000);
> -
> -	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
> -			       RX_REE_GCSM1_CTRL, 0x0000);
> -	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
> -			       RX_REE_GCSM2_CTRL, 0x0000);
> -	cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
> -			       RX_REE_PERGCSM_CTRL, 0x0000);
> -
> -	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> -			       XCVR_DIAG_BIDI_CTRL, 0x000F);
> -	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> -			       XCVR_DIAG_PLLDRC_CTRL, 0x0001);
> -	cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> -			       XCVR_DIAG_HSCLK_SEL, 0x0000);
> -}
> -
>  static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
>  {
>  	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
> @@ -1972,9 +1804,6 @@ static int cdns_torrent_phy_init(struct phy *phy)
>  	if (cdns_phy->nsubnodes > 1)
>  		return 0;
>  
> -	if (phy_type == TYPE_DP)
> -		return cdns_torrent_dp_init(phy);
> -
>  	/**
>  	 * Spread spectrum generation is not required or supported
>  	 * for SGMII/QSGMII
> @@ -2060,6 +1889,9 @@ static int cdns_torrent_phy_init(struct phy *phy)
>  		}
>  	}
>  
> +	if (phy_type == TYPE_DP)
> +		return cdns_torrent_dp_init(phy);
> +
>  	return 0;
>  }
>  
> @@ -2584,6 +2416,168 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +/* Single DisplayPort(DP) link configuration */
> +static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {
> +	{0x0000, PHY_PLL_CFG},
> +};
> +
> +static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = {
> +	{0x0000, XCVR_DIAG_HSCLK_SEL},
> +	{0x0001, XCVR_DIAG_PLLDRC_CTRL}
> +};
> +
> +static struct cdns_torrent_vals sl_dp_link_cmn_vals = {
> +	.reg_pairs = sl_dp_link_cmn_regs,
> +	.num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs),
> +};
> +
> +static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = {
> +	.reg_pairs = sl_dp_xcvr_diag_ln_regs,
> +	.num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs),
> +};
> +
> +/* Single DP, 19.2 MHz Ref clk, no SSC */
> +static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = {
> +	{0x0014, CMN_SSM_BIAS_TMR},
> +	{0x0027, CMN_PLLSM0_PLLPRE_TMR},
> +	{0x00A1, CMN_PLLSM0_PLLLOCK_TMR},
> +	{0x0027, CMN_PLLSM1_PLLPRE_TMR},
> +	{0x00A1, CMN_PLLSM1_PLLLOCK_TMR},
> +	{0x0060, CMN_BGCAL_INIT_TMR},
> +	{0x0060, CMN_BGCAL_ITER_TMR},
> +	{0x0014, CMN_IBCAL_INIT_TMR},
> +	{0x0018, CMN_TXPUCAL_INIT_TMR},
> +	{0x0005, CMN_TXPUCAL_ITER_TMR},
> +	{0x0018, CMN_TXPDCAL_INIT_TMR},
> +	{0x0005, CMN_TXPDCAL_ITER_TMR},
> +	{0x0240, CMN_RXCAL_INIT_TMR},
> +	{0x0005, CMN_RXCAL_ITER_TMR},
> +	{0x0002, CMN_SD_CAL_INIT_TMR},
> +	{0x0002, CMN_SD_CAL_ITER_TMR},
> +	{0x000B, CMN_SD_CAL_REFTIM_START},
> +	{0x0137, CMN_SD_CAL_PLLCNT_START},
> +	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
> +	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
> +	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
> +	{0x0004, CMN_PLL0_DSM_DIAG_M0},
> +	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
> +	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
> +	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
> +	{0x0004, CMN_PLL1_DSM_DIAG_M0},
> +	{0x00C0, CMN_PLL0_VCOCAL_INIT_TMR},
> +	{0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
> +	{0x00C0, CMN_PLL1_VCOCAL_INIT_TMR},
> +	{0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
> +	{0x0260, CMN_PLL0_VCOCAL_REFTIM_START},
> +	{0x0003, CMN_PLL0_VCOCAL_TCTRL},
> +	{0x0260, CMN_PLL1_VCOCAL_REFTIM_START},
> +	{0x0003, CMN_PLL1_VCOCAL_TCTRL}
> +};
> +
> +static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = {
> +	{0x0780, TX_RCVDET_ST_TMR},
> +	{0x00FB, TX_PSC_A0},
> +	{0x04AA, TX_PSC_A2},
> +	{0x04AA, TX_PSC_A3},
> +	{0x000F, XCVR_DIAG_BIDI_CTRL}
> +};
> +
> +static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = {
> +	{0x0000, RX_PSC_A0},
> +	{0x0000, RX_PSC_A2},
> +	{0x0000, RX_PSC_A3},
> +	{0x0000, RX_PSC_CAL},
> +	{0x0000, RX_REE_GCSM1_CTRL},
> +	{0x0000, RX_REE_GCSM2_CTRL},
> +	{0x0000, RX_REE_PERGCSM_CTRL}
> +};
> +
> +static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = {
> +	.reg_pairs = sl_dp_19_2_no_ssc_cmn_regs,
> +	.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs),
> +};
> +
> +static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = {
> +	.reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs,
> +	.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs),
> +};
> +
> +static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = {
> +	.reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs,
> +	.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs),
> +};
> +
> +/* Single DP, 25 MHz Ref clk, no SSC */
> +static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = {
> +	{0x0019, CMN_SSM_BIAS_TMR},
> +	{0x0032, CMN_PLLSM0_PLLPRE_TMR},
> +	{0x00D1, CMN_PLLSM0_PLLLOCK_TMR},
> +	{0x0032, CMN_PLLSM1_PLLPRE_TMR},
> +	{0x00D1, CMN_PLLSM1_PLLLOCK_TMR},
> +	{0x007D, CMN_BGCAL_INIT_TMR},
> +	{0x007D, CMN_BGCAL_ITER_TMR},
> +	{0x0019, CMN_IBCAL_INIT_TMR},
> +	{0x001E, CMN_TXPUCAL_INIT_TMR},
> +	{0x0006, CMN_TXPUCAL_ITER_TMR},
> +	{0x001E, CMN_TXPDCAL_INIT_TMR},
> +	{0x0006, CMN_TXPDCAL_ITER_TMR},
> +	{0x02EE, CMN_RXCAL_INIT_TMR},
> +	{0x0006, CMN_RXCAL_ITER_TMR},
> +	{0x0002, CMN_SD_CAL_INIT_TMR},
> +	{0x0002, CMN_SD_CAL_ITER_TMR},
> +	{0x000E, CMN_SD_CAL_REFTIM_START},
> +	{0x012B, CMN_SD_CAL_PLLCNT_START},
> +	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
> +	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
> +	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
> +	{0x0004, CMN_PLL0_DSM_DIAG_M0},
> +	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
> +	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
> +	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
> +	{0x0004, CMN_PLL1_DSM_DIAG_M0},
> +	{0x00FA, CMN_PLL0_VCOCAL_INIT_TMR},
> +	{0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
> +	{0x00FA, CMN_PLL1_VCOCAL_INIT_TMR},
> +	{0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
> +	{0x0317, CMN_PLL0_VCOCAL_REFTIM_START},
> +	{0x0003, CMN_PLL0_VCOCAL_TCTRL},
> +	{0x0317, CMN_PLL1_VCOCAL_REFTIM_START},
> +	{0x0003, CMN_PLL1_VCOCAL_TCTRL}
> +};
> +
> +static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = {
> +	{0x09C4, TX_RCVDET_ST_TMR},
> +	{0x00FB, TX_PSC_A0},
> +	{0x04AA, TX_PSC_A2},
> +	{0x04AA, TX_PSC_A3},
> +	{0x000F, XCVR_DIAG_BIDI_CTRL}
> +};
> +
> +static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = {
> +	{0x0000, RX_PSC_A0},
> +	{0x0000, RX_PSC_A2},
> +	{0x0000, RX_PSC_A3},
> +	{0x0000, RX_PSC_CAL},
> +	{0x0000, RX_REE_GCSM1_CTRL},
> +	{0x0000, RX_REE_GCSM2_CTRL},
> +	{0x0000, RX_REE_PERGCSM_CTRL}
> +};
> +
> +static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = {
> +	.reg_pairs = sl_dp_25_no_ssc_cmn_regs,
> +	.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs),
> +};
> +
> +static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = {
> +	.reg_pairs = sl_dp_25_no_ssc_tx_ln_regs,
> +	.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs),
> +};
> +
> +static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {
> +	.reg_pairs = sl_dp_25_no_ssc_rx_ln_regs,
> +	.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),
> +};
> +
>  /* USB and SGMII/QSGMII link configuration */
>  static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
>  	{0x0002, PHY_PLL_CFG},
> @@ -3322,6 +3316,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  	.block_offset_shift = 0x2,
>  	.reg_offset_shift = 0x2,
>  	.link_cmn_vals = {
> +		[TYPE_DP] = {
> +			[TYPE_NONE] = {
> +				[NO_SSC] = &sl_dp_link_cmn_vals,
> +			},
> +		},
>  		[TYPE_PCIE] = {
>  			[TYPE_NONE] = {
>  				[NO_SSC] = NULL,
> @@ -3398,6 +3397,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  		},
>  	},
>  	.xcvr_diag_vals = {
> +		[TYPE_DP] = {
> +			[TYPE_NONE] = {
> +				[NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
> +			},
> +		},
>  		[TYPE_PCIE] = {
>  			[TYPE_NONE] = {
>  				[NO_SSC] = NULL,
> @@ -3498,6 +3502,20 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  		},
>  	},
>  	.cmn_vals = {
> +		[CLK_19_2_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
> +				},
> +			},
> +		},
> +		[CLK_25_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
> +				},
> +			},
> +		},
>  		[CLK_100_MHZ] = {
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> @@ -3576,6 +3594,20 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  		},
>  	},
>  	.tx_ln_vals = {
> +		[CLK_19_2_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
> +				},
> +			},
> +		},
> +		[CLK_25_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
> +				},
> +			},
> +		},
>  		[CLK_100_MHZ] = {
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> @@ -3654,6 +3686,20 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  		},
>  	},
>  	.rx_ln_vals = {
> +		[CLK_19_2_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
> +				},
> +			},
> +		},
> +		[CLK_25_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
> +				},
> +			},
> +		},
>  		[CLK_100_MHZ] = {
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> @@ -3737,6 +3783,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  	.block_offset_shift = 0x0,
>  	.reg_offset_shift = 0x1,
>  	.link_cmn_vals = {
> +		[TYPE_DP] = {
> +			[TYPE_NONE] = {
> +				[NO_SSC] = &sl_dp_link_cmn_vals,
> +			},
> +		},
>  		[TYPE_PCIE] = {
>  			[TYPE_NONE] = {
>  				[NO_SSC] = NULL,
> @@ -3813,6 +3864,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  		},
>  	},
>  	.xcvr_diag_vals = {
> +		[TYPE_DP] = {
> +			[TYPE_NONE] = {
> +				[NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
> +			},
> +		},
>  		[TYPE_PCIE] = {
>  			[TYPE_NONE] = {
>  				[NO_SSC] = NULL,
> @@ -3913,6 +3969,20 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  		},
>  	},
>  	.cmn_vals = {
> +		[CLK_19_2_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
> +				},
> +			},
> +		},
> +		[CLK_25_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
> +				},
> +			},
> +		},
>  		[CLK_100_MHZ] = {
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> @@ -3991,6 +4061,20 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  		},
>  	},
>  	.tx_ln_vals = {
> +		[CLK_19_2_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
> +				},
> +			},
> +		},
> +		[CLK_25_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
> +				},
> +			},
> +		},
>  		[CLK_100_MHZ] = {
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> @@ -4069,6 +4153,20 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  		},
>  	},
>  	.rx_ln_vals = {
> +		[CLK_19_2_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
> +				},
> +			},
> +		},
> +		[CLK_25_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
> +				},
> +			},
> +		},
>  		[CLK_100_MHZ] = {
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> 

[PATCH 06/14] phy: cadence-torrent: Reorder functions to avoid function declarations

[Swapnil Jakhade]

Reorder some functions to avoid function declarations. Also, remove
unnecessary line breaks while moving. No functional change.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 305 +++++++++-------------
 1 file changed, 121 insertions(+), 184 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 4ec5909f192c..396c3810a69d 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -342,9 +342,6 @@ struct cdns_torrent_derived_refclk {
 			container_of(_hw, struct cdns_torrent_derived_refclk, hw)
 
 static
-void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
-					     u32 rate, bool ssc);
-static
 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
 					   u32 rate, bool ssc);
 
@@ -579,6 +576,127 @@ static const struct coefficients vltg_coeff[4][4] = {
 	}
 };
 
+/*
+ * Set registers responsible for enabling and configuring SSC, with second and
+ * third register values provided by parameters.
+ */
+static
+void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
+					u32 ctrl2_val, u32 ctrl3_val)
+{
+	struct regmap *regmap = cdns_phy->regmap_common_cdb;
+
+	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
+	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
+	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
+	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
+}
+
+static
+void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
+					     u32 rate, bool ssc)
+{
+	struct regmap *regmap = cdns_phy->regmap_common_cdb;
+
+	/* Assumes 19.2 MHz refclock */
+	switch (rate) {
+	/* Setting VCO for 10.8GHz */
+	case 2700:
+	case 5400:
+		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
+		if (ssc)
+			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A);
+		break;
+	/* Setting VCO for 9.72GHz */
+	case 1620:
+	case 2430:
+	case 3240:
+		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		if (ssc)
+			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069);
+		break;
+	/* Setting VCO for 8.64GHz */
+	case 2160:
+	case 4320:
+		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		if (ssc)
+			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069);
+		break;
+	/* Setting VCO for 8.1GHz */
+	case 8100:
+		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		if (ssc)
+			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A);
+		break;
+	}
+
+	if (ssc) {
+		cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
+	} else {
+		cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
+		/* Set reset register values to disable SSC */
+		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
+	}
+
+	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
+	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
+}
+
 /*
  * Enable or disable PLL for selected lanes.
  */
@@ -1211,187 +1329,6 @@ static int cdns_torrent_dp_init(struct phy *phy)
 	return ret;
 }
 
-/*
- * Set registers responsible for enabling and configuring SSC, with second and
- * third register values provided by parameters.
- */
-static
-void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
-					u32 ctrl2_val, u32 ctrl3_val)
-{
-	struct regmap *regmap = cdns_phy->regmap_common_cdb;
-
-	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
-}
-
-static
-void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
-					     u32 rate, bool ssc)
-{
-	struct regmap *regmap = cdns_phy->regmap_common_cdb;
-
-	/* Assumes 19.2 MHz refclock */
-	switch (rate) {
-	/* Setting VCO for 10.8GHz */
-	case 2700:
-	case 5400:
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_INTDIV_M0, 0x0119);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_FRACDIVL_M0, 0x4000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_HIGH_THR_M0, 0x00BC);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_INTDIV_M0, 0x0119);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_FRACDIVL_M0, 0x4000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_HIGH_THR_M0, 0x00BC);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
-		if (ssc)
-			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A,
-							   0x006A);
-		break;
-	/* Setting VCO for 9.72GHz */
-	case 1620:
-	case 2430:
-	case 3240:
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_INTDIV_M0, 0x01FA);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_FRACDIVL_M0, 0x4000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_HIGH_THR_M0, 0x0152);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_INTDIV_M0, 0x01FA);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_FRACDIVL_M0, 0x4000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_HIGH_THR_M0, 0x0152);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
-		if (ssc)
-			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD,
-							   0x0069);
-		break;
-	/* Setting VCO for 8.64GHz */
-	case 2160:
-	case 4320:
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_INTDIV_M0, 0x01C2);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_FRACDIVL_M0, 0x0000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_HIGH_THR_M0, 0x012C);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_INTDIV_M0, 0x01C2);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_FRACDIVL_M0, 0x0000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_HIGH_THR_M0, 0x012C);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
-		if (ssc)
-			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536,
-							   0x0069);
-		break;
-	/* Setting VCO for 8.1GHz */
-	case 8100:
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_INTDIV_M0, 0x01A5);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_FRACDIVL_M0, 0xE000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_HIGH_THR_M0, 0x011A);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_INTDIV_M0, 0x01A5);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_FRACDIVL_M0, 0xE000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_HIGH_THR_M0, 0x011A);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
-		if (ssc)
-			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7,
-							   0x006A);
-		break;
-	}
-
-	if (ssc) {
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
-	} else {
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
-		/* Set reset register values to disable SSC */
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_SS_CTRL1_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_SS_CTRL2_M0, 0x0000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_SS_CTRL3_M0, 0x0000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_SS_CTRL4_M0, 0x0000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_SS_CTRL1_M0, 0x0002);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_SS_CTRL2_M0, 0x0000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_SS_CTRL3_M0, 0x0000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_SS_CTRL4_M0, 0x0000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
-	}
-
-	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
-}
-
 /*
  * Set registers responsible for enabling and configuring SSC, with second
  * register value provided by a parameter.
-- 
2.26.1

[PATCH 07/14] phy: cadence-torrent: Reorder functions to avoid function declarations

[Swapnil Jakhade]

Reorder some functions to avoid function declarations.
No functional change.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 250 +++++++++++-----------
 1 file changed, 123 insertions(+), 127 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 396c3810a69d..a6331927d775 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -341,10 +341,6 @@ struct cdns_torrent_derived_refclk {
 #define to_cdns_torrent_derived_refclk(_hw)	\
 			container_of(_hw, struct cdns_torrent_derived_refclk, hw)
 
-static
-void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
-					   u32 rate, bool ssc);
-
 struct cdns_reg_pairs {
 	u32 val;
 	u32 off;
@@ -697,6 +693,129 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
 	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
 }
 
+/*
+ * Set registers responsible for enabling and configuring SSC, with second
+ * register value provided by a parameter.
+ */
+static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
+					     u32 ctrl2_val)
+{
+	struct regmap *regmap = cdns_phy->regmap_common_cdb;
+
+	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
+	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
+	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
+	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
+}
+
+static
+void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
+					   u32 rate, bool ssc)
+{
+	struct regmap *regmap = cdns_phy->regmap_common_cdb;
+
+	/* Assumes 25 MHz refclock */
+	switch (rate) {
+	/* Setting VCO for 10.8GHz */
+	case 2700:
+	case 5400:
+		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
+		if (ssc)
+			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
+		break;
+	/* Setting VCO for 9.72GHz */
+	case 1620:
+	case 2430:
+	case 3240:
+		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
+		if (ssc)
+			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
+		break;
+	/* Setting VCO for 8.64GHz */
+	case 2160:
+	case 4320:
+		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
+		if (ssc)
+			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
+		break;
+	/* Setting VCO for 8.1GHz */
+	case 8100:
+		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
+		if (ssc)
+			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
+		break;
+	}
+
+	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+
+	if (ssc) {
+		cdns_torrent_phy_write(regmap,
+				       CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
+		cdns_torrent_phy_write(regmap,
+				       CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
+		cdns_torrent_phy_write(regmap,
+				       CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
+		cdns_torrent_phy_write(regmap,
+				       CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
+	} else {
+		cdns_torrent_phy_write(regmap,
+				       CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
+		cdns_torrent_phy_write(regmap,
+				       CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
+		/* Set reset register values to disable SSC */
+		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
+		cdns_torrent_phy_write(regmap,
+				       CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
+		cdns_torrent_phy_write(regmap,
+				       CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
+	}
+
+	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
+	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
+	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
+}
+
 /*
  * Enable or disable PLL for selected lanes.
  */
@@ -1329,129 +1448,6 @@ static int cdns_torrent_dp_init(struct phy *phy)
 	return ret;
 }
 
-/*
- * Set registers responsible for enabling and configuring SSC, with second
- * register value provided by a parameter.
- */
-static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
-					     u32 ctrl2_val)
-{
-	struct regmap *regmap = cdns_phy->regmap_common_cdb;
-
-	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
-}
-
-static
-void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
-					   u32 rate, bool ssc)
-{
-	struct regmap *regmap = cdns_phy->regmap_common_cdb;
-
-	/* Assumes 25 MHz refclock */
-	switch (rate) {
-	/* Setting VCO for 10.8GHz */
-	case 2700:
-	case 5400:
-		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
-		if (ssc)
-			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
-		break;
-	/* Setting VCO for 9.72GHz */
-	case 1620:
-	case 2430:
-	case 3240:
-		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
-		if (ssc)
-			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
-		break;
-	/* Setting VCO for 8.64GHz */
-	case 2160:
-	case 4320:
-		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
-		if (ssc)
-			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
-		break;
-	/* Setting VCO for 8.1GHz */
-	case 8100:
-		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
-		if (ssc)
-			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
-		break;
-	}
-
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
-	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
-
-	if (ssc) {
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
-	} else {
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
-		/* Set reset register values to disable SSC */
-		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
-		cdns_torrent_phy_write(regmap,
-				       CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
-	}
-
-	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
-	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
-	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
-}
-
 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
 {
 	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
-- 
2.26.1

[PATCH 08/14] phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clock

[Swapnil Jakhade]

Add PHY configuration registers for DP with 100MHz ref clock and NO_SSC.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 162 ++++++++++++++++++++++
 1 file changed, 162 insertions(+)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index a6331927d775..69466481af26 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -103,6 +103,7 @@
 #define CMN_PLL0_FRACDIVH_M0		0x0092U
 #define CMN_PLL0_HIGH_THR_M0		0x0093U
 #define CMN_PLL0_DSM_DIAG_M0		0x0094U
+#define CMN_PLL0_DSM_FBH_OVRD_M0	0x0095U
 #define CMN_PLL0_SS_CTRL1_M0		0x0098U
 #define CMN_PLL0_SS_CTRL2_M0            0x0099U
 #define CMN_PLL0_SS_CTRL3_M0            0x009AU
@@ -816,6 +817,89 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
 	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
 }
 
+static
+void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
+					    u32 rate, bool ssc)
+{
+	struct regmap *regmap = cdns_phy->regmap_common_cdb;
+
+	/* Assumes 100 MHz refclock */
+	switch (rate) {
+	/* Setting VCO for 10.8GHz */
+	case 2700:
+	case 5400:
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
+		break;
+	/* Setting VCO for 9.72GHz */
+	case 1620:
+	case 2430:
+	case 3240:
+		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		break;
+	/* Setting VCO for 8.64GHz */
+	case 2160:
+	case 4320:
+		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		break;
+	/* Setting VCO for 8.1GHz */
+	case 8100:
+		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
+		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		break;
+	}
+}
+
 /*
  * Enable or disable PLL for selected lanes.
  */
@@ -1056,6 +1140,10 @@ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
 	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
 		/* PMA common configuration 25MHz */
 		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
+	else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
+		/* PMA common configuration 100MHz */
+		cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc);
+
 	cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
 
 	/* Enable the cmn_pll0_en. */
@@ -1395,6 +1483,7 @@ static int cdns_torrent_dp_init(struct phy *phy)
 	switch (cdns_phy->ref_clk_rate) {
 	case CLK_19_2_MHZ:
 	case CLK_25_MHZ:
+	case CLK_100_MHZ:
 		/* Valid Ref Clock Rate */
 		break;
 	default:
@@ -1431,6 +1520,11 @@ static int cdns_torrent_dp_init(struct phy *phy)
 		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
 						      cdns_phy->max_bit_rate,
 						      false);
+	else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
+		cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy,
+						       cdns_phy->max_bit_rate,
+						       false);
+
 	cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
 				     inst->num_lanes);
 
@@ -2511,6 +2605,44 @@ static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {
 	.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),
 };
 
+/* Single DP, 100 MHz Ref clk, no SSC */
+static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = {
+	{0x0003, CMN_PLL0_VCOCAL_TCTRL},
+	{0x0003, CMN_PLL1_VCOCAL_TCTRL}
+};
+
+static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = {
+	{0x00FB, TX_PSC_A0},
+	{0x04AA, TX_PSC_A2},
+	{0x04AA, TX_PSC_A3},
+	{0x000F, XCVR_DIAG_BIDI_CTRL}
+};
+
+static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = {
+	{0x0000, RX_PSC_A0},
+	{0x0000, RX_PSC_A2},
+	{0x0000, RX_PSC_A3},
+	{0x0000, RX_PSC_CAL},
+	{0x0000, RX_REE_GCSM1_CTRL},
+	{0x0000, RX_REE_GCSM2_CTRL},
+	{0x0000, RX_REE_PERGCSM_CTRL}
+};
+
+static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = {
+	.reg_pairs = sl_dp_100_no_ssc_cmn_regs,
+	.num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs),
+};
+
+static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = {
+	.reg_pairs = sl_dp_100_no_ssc_tx_ln_regs,
+	.num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs),
+};
+
+static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = {
+	.reg_pairs = sl_dp_100_no_ssc_rx_ln_regs,
+	.num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs),
+};
+
 /* USB and SGMII/QSGMII link configuration */
 static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
 	{0x0002, PHY_PLL_CFG},
@@ -3450,6 +3582,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 			},
 		},
 		[CLK_100_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
+				},
+			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
 					[NO_SSC] = NULL,
@@ -3542,6 +3679,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 			},
 		},
 		[CLK_100_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
+				},
+			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
 					[NO_SSC] = NULL,
@@ -3634,6 +3776,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 			},
 		},
 		[CLK_100_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
+				},
+			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
 					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
@@ -3917,6 +4064,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 			},
 		},
 		[CLK_100_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
+				},
+			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
 					[NO_SSC] = NULL,
@@ -4009,6 +4161,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 			},
 		},
 		[CLK_100_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
+				},
+			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
 					[NO_SSC] = NULL,
@@ -4101,6 +4258,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 			},
 		},
 		[CLK_100_MHZ] = {
+			[TYPE_DP] = {
+				[TYPE_NONE] = {
+					[NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
+				},
+			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
 					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
-- 
2.26.1

Re: [PATCH 08/14] phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clock

[Kishon Vijay Abraham I]

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Add PHY configuration registers for DP with 100MHz ref clock and NO_SSC.

Looks neat! Thanks!

> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 162 ++++++++++++++++++++++
>  1 file changed, 162 insertions(+)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index a6331927d775..69466481af26 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -103,6 +103,7 @@
>  #define CMN_PLL0_FRACDIVH_M0		0x0092U
>  #define CMN_PLL0_HIGH_THR_M0		0x0093U
>  #define CMN_PLL0_DSM_DIAG_M0		0x0094U
> +#define CMN_PLL0_DSM_FBH_OVRD_M0	0x0095U
>  #define CMN_PLL0_SS_CTRL1_M0		0x0098U
>  #define CMN_PLL0_SS_CTRL2_M0            0x0099U
>  #define CMN_PLL0_SS_CTRL3_M0            0x009AU
> @@ -816,6 +817,89 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
>  	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
>  }
>  
> +static
> +void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
> +					    u32 rate, bool ssc)
> +{
> +	struct regmap *regmap = cdns_phy->regmap_common_cdb;
> +
> +	/* Assumes 100 MHz refclock */
> +	switch (rate) {
> +	/* Setting VCO for 10.8GHz */
> +	case 2700:
> +	case 5400:
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
> +		break;
> +	/* Setting VCO for 9.72GHz */
> +	case 1620:
> +	case 2430:
> +	case 3240:
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
> +		break;
> +	/* Setting VCO for 8.64GHz */
> +	case 2160:
> +	case 4320:
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
> +		break;
> +	/* Setting VCO for 8.1GHz */
> +	case 8100:
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
> +		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
> +		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
> +		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);


We could think of having DP specific separate arrays for the above
configurations. Might help us to avoid having separate functions for
each of the required frequencies.

Thanks
Kishon

> +		break;
> +	}
> +}
> +
>  /*
>   * Enable or disable PLL for selected lanes.
>   */
> @@ -1056,6 +1140,10 @@ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
>  	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
>  		/* PMA common configuration 25MHz */
>  		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
> +	else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
> +		/* PMA common configuration 100MHz */
> +		cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc);
> +
>  	cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
>  
>  	/* Enable the cmn_pll0_en. */
> @@ -1395,6 +1483,7 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  	switch (cdns_phy->ref_clk_rate) {
>  	case CLK_19_2_MHZ:
>  	case CLK_25_MHZ:
> +	case CLK_100_MHZ:
>  		/* Valid Ref Clock Rate */
>  		break;
>  	default:
> @@ -1431,6 +1520,11 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
>  						      cdns_phy->max_bit_rate,
>  						      false);
> +	else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
> +		cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy,
> +						       cdns_phy->max_bit_rate,
> +						       false);
> +
>  	cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
>  				     inst->num_lanes);
>  
> @@ -2511,6 +2605,44 @@ static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {
>  	.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),
>  };
>  
> +/* Single DP, 100 MHz Ref clk, no SSC */
> +static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = {
> +	{0x0003, CMN_PLL0_VCOCAL_TCTRL},
> +	{0x0003, CMN_PLL1_VCOCAL_TCTRL}
> +};
> +
> +static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = {
> +	{0x00FB, TX_PSC_A0},
> +	{0x04AA, TX_PSC_A2},
> +	{0x04AA, TX_PSC_A3},
> +	{0x000F, XCVR_DIAG_BIDI_CTRL}
> +};
> +
> +static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = {
> +	{0x0000, RX_PSC_A0},
> +	{0x0000, RX_PSC_A2},
> +	{0x0000, RX_PSC_A3},
> +	{0x0000, RX_PSC_CAL},
> +	{0x0000, RX_REE_GCSM1_CTRL},
> +	{0x0000, RX_REE_GCSM2_CTRL},
> +	{0x0000, RX_REE_PERGCSM_CTRL}
> +};
> +
> +static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = {
> +	.reg_pairs = sl_dp_100_no_ssc_cmn_regs,
> +	.num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs),
> +};
> +
> +static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = {
> +	.reg_pairs = sl_dp_100_no_ssc_tx_ln_regs,
> +	.num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs),
> +};
> +
> +static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = {
> +	.reg_pairs = sl_dp_100_no_ssc_rx_ln_regs,
> +	.num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs),
> +};
> +
>  /* USB and SGMII/QSGMII link configuration */
>  static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
>  	{0x0002, PHY_PLL_CFG},
> @@ -3450,6 +3582,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  			},
>  		},
>  		[CLK_100_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
> +				},
> +			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = NULL,
> @@ -3542,6 +3679,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  			},
>  		},
>  		[CLK_100_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
> +				},
> +			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = NULL,
> @@ -3634,6 +3776,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  			},
>  		},
>  		[CLK_100_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
> +				},
> +			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> @@ -3917,6 +4064,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  			},
>  		},
>  		[CLK_100_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
> +				},
> +			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = NULL,
> @@ -4009,6 +4161,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  			},
>  		},
>  		[CLK_100_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
> +				},
> +			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = NULL,
> @@ -4101,6 +4258,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  			},
>  		},
>  		[CLK_100_MHZ] = {
> +			[TYPE_DP] = {
> +				[TYPE_NONE] = {
> +					[NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
> +				},
> +			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> 

[PATCH 09/14] phy: cadence-torrent: Add separate functions for reusable code

[Swapnil Jakhade]

Torrent PHY driver currently supports single link DP configuration.
Prepare driver to support multilink DP configurations by adding
separate functions for common initialization sequence.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 53 +++++++++++++++--------
 1 file changed, 35 insertions(+), 18 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 69466481af26..e4dd8d1711a6 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -1472,24 +1472,11 @@ static int cdns_torrent_phy_off(struct phy *phy)
 	return reset_control_assert(inst->lnk_rst);
 }
 
-static int cdns_torrent_dp_init(struct phy *phy)
+static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
+					struct cdns_torrent_inst *inst)
 {
-	unsigned char lane_bits;
-	int ret;
-	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
-	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
 	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
-
-	switch (cdns_phy->ref_clk_rate) {
-	case CLK_19_2_MHZ:
-	case CLK_25_MHZ:
-	case CLK_100_MHZ:
-		/* Valid Ref Clock Rate */
-		break;
-	default:
-		dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
-		return -EINVAL;
-	}
+	unsigned char lane_bits;
 
 	cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
 
@@ -1510,8 +1497,10 @@ static int cdns_torrent_dp_init(struct phy *phy)
 	/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
 	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
 
-	/* PHY PMA registers configuration functions */
-	/* Initialize PHY with max supported link rate, without SSC. */
+	/*
+	 * PHY PMA registers configuration functions
+	 * Initialize PHY with max supported link rate, without SSC.
+	 */
 	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
 		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
 							cdns_phy->max_bit_rate,
@@ -1530,6 +1519,13 @@ static int cdns_torrent_dp_init(struct phy *phy)
 
 	/* take out of reset */
 	regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
+}
+
+static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy,
+				 struct cdns_torrent_inst *inst,
+				 struct phy *phy)
+{
+	int ret;
 
 	cdns_torrent_phy_on(phy);
 
@@ -1542,6 +1538,27 @@ static int cdns_torrent_dp_init(struct phy *phy)
 	return ret;
 }
 
+static int cdns_torrent_dp_init(struct phy *phy)
+{
+	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
+	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
+
+	switch (cdns_phy->ref_clk_rate) {
+	case CLK_19_2_MHZ:
+	case CLK_25_MHZ:
+	case CLK_100_MHZ:
+		/* Valid Ref Clock Rate */
+		break;
+	default:
+		dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
+		return -EINVAL;
+	}
+
+	cdns_torrent_dp_common_init(cdns_phy, inst);
+
+	return cdns_torrent_dp_start(cdns_phy, inst, phy);
+}
+
 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
 {
 	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
-- 
2.26.1

Re: [PATCH 09/14] phy: cadence-torrent: Add separate functions for reusable code

[Kishon Vijay Abraham I]

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Torrent PHY driver currently supports single link DP configuration.
> Prepare driver to support multilink DP configurations by adding
> separate functions for common initialization sequence.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>

Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 53 +++++++++++++++--------
>  1 file changed, 35 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index 69466481af26..e4dd8d1711a6 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -1472,24 +1472,11 @@ static int cdns_torrent_phy_off(struct phy *phy)
>  	return reset_control_assert(inst->lnk_rst);
>  }
>  
> -static int cdns_torrent_dp_init(struct phy *phy)
> +static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
> +					struct cdns_torrent_inst *inst)
>  {
> -	unsigned char lane_bits;
> -	int ret;
> -	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
> -	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
>  	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
> -
> -	switch (cdns_phy->ref_clk_rate) {
> -	case CLK_19_2_MHZ:
> -	case CLK_25_MHZ:
> -	case CLK_100_MHZ:
> -		/* Valid Ref Clock Rate */
> -		break;
> -	default:
> -		dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
> -		return -EINVAL;
> -	}
> +	unsigned char lane_bits;
>  
>  	cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
>  
> @@ -1510,8 +1497,10 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  	/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
>  	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
>  
> -	/* PHY PMA registers configuration functions */
> -	/* Initialize PHY with max supported link rate, without SSC. */
> +	/*
> +	 * PHY PMA registers configuration functions
> +	 * Initialize PHY with max supported link rate, without SSC.
> +	 */
>  	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
>  		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
>  							cdns_phy->max_bit_rate,
> @@ -1530,6 +1519,13 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  
>  	/* take out of reset */
>  	regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
> +}
> +
> +static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy,
> +				 struct cdns_torrent_inst *inst,
> +				 struct phy *phy)
> +{
> +	int ret;
>  
>  	cdns_torrent_phy_on(phy);
>  
> @@ -1542,6 +1538,27 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  	return ret;
>  }
>  
> +static int cdns_torrent_dp_init(struct phy *phy)
> +{
> +	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
> +	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
> +
> +	switch (cdns_phy->ref_clk_rate) {
> +	case CLK_19_2_MHZ:
> +	case CLK_25_MHZ:
> +	case CLK_100_MHZ:
> +		/* Valid Ref Clock Rate */
> +		break;
> +	default:
> +		dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
> +		return -EINVAL;
> +	}
> +
> +	cdns_torrent_dp_common_init(cdns_phy, inst);
> +
> +	return cdns_torrent_dp_start(cdns_phy, inst, phy);
> +}
> +
>  static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
>  {
>  	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
> 

[PATCH 10/14] phy: cadence-torrent: Add function to get PLL to be configured for DP

[Swapnil Jakhade]

Torrent PHY PLL0 or PLL1 is used for DP depending on the single link or
multilink protocol configuration for which PHY is configured. In multilink
configurations with other protocols, either PLL0 or PLL1 will be used
for DP. For single link DP, both PLLs need to be configured at POR.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index e4dd8d1711a6..44e28ea8ffa7 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -288,6 +288,11 @@ enum cdns_torrent_ssc_mode {
 	INTERNAL_SSC
 };
 
+enum cdns_torrent_dp_pll {
+	DP_PLL0 = 0x1,
+	DP_PLL1 = 0x2
+};
+
 struct cdns_torrent_inst {
 	struct phy *phy;
 	u32 mlane;
@@ -301,6 +306,7 @@ struct cdns_torrent_phy {
 	void __iomem *base;	/* DPTX registers base */
 	void __iomem *sd_base; /* SD0801 registers base */
 	u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
+	u32 dp_pll;
 	struct reset_control *phy_rst;
 	struct reset_control *apb_rst;
 	struct device *dev;
@@ -900,6 +906,30 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
 	}
 }
 
+/* Set PLL used for DP configuration */
+static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy,
+				   enum cdns_torrent_phy_type phy_t2)
+{
+	switch (phy_t2) {
+	case TYPE_PCIE:
+	case TYPE_USB:
+		cdns_phy->dp_pll = DP_PLL1;
+		break;
+	case TYPE_SGMII:
+	case TYPE_QSGMII:
+		cdns_phy->dp_pll = DP_PLL0;
+		break;
+	case TYPE_NONE:
+		cdns_phy->dp_pll = DP_PLL0 | DP_PLL1;
+		break;
+	default:
+		dev_err(cdns_phy->dev, "Unsupported PHY configuration\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 /*
  * Enable or disable PLL for selected lanes.
  */
@@ -1554,6 +1584,8 @@ static int cdns_torrent_dp_init(struct phy *phy)
 		return -EINVAL;
 	}
 
+	cdns_torrent_dp_get_pll(cdns_phy, TYPE_NONE);
+
 	cdns_torrent_dp_common_init(cdns_phy, inst);
 
 	return cdns_torrent_dp_start(cdns_phy, inst, phy);
-- 
2.26.1

Re: [PATCH 10/14] phy: cadence-torrent: Add function to get PLL to be configured for DP

[Kishon Vijay Abraham I]

Hi Swapnil,

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Torrent PHY PLL0 or PLL1 is used for DP depending on the single link or
> multilink protocol configuration for which PHY is configured. In multilink
> configurations with other protocols, either PLL0 or PLL1 will be used
> for DP. For single link DP, both PLLs need to be configured at POR.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 32 +++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index e4dd8d1711a6..44e28ea8ffa7 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -288,6 +288,11 @@ enum cdns_torrent_ssc_mode {
>  	INTERNAL_SSC
>  };
>  
> +enum cdns_torrent_dp_pll {
> +	DP_PLL0 = 0x1,
> +	DP_PLL1 = 0x2

Using BIT() macro might be better since you are using this as bitfield.
> +};
> +
>  struct cdns_torrent_inst {
>  	struct phy *phy;
>  	u32 mlane;
> @@ -301,6 +306,7 @@ struct cdns_torrent_phy {
>  	void __iomem *base;	/* DPTX registers base */
>  	void __iomem *sd_base; /* SD0801 registers base */
>  	u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
> +	u32 dp_pll;

enum cdns_torrent_dp_pll?

Thanks
Kishon

>  	struct reset_control *phy_rst;
>  	struct reset_control *apb_rst;
>  	struct device *dev;
> @@ -900,6 +906,30 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
>  	}
>  }
>  
> +/* Set PLL used for DP configuration */
> +static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy,
> +				   enum cdns_torrent_phy_type phy_t2)
> +{
> +	switch (phy_t2) {
> +	case TYPE_PCIE:
> +	case TYPE_USB:
> +		cdns_phy->dp_pll = DP_PLL1;
> +		break;
> +	case TYPE_SGMII:
> +	case TYPE_QSGMII:
> +		cdns_phy->dp_pll = DP_PLL0;
> +		break;
> +	case TYPE_NONE:
> +		cdns_phy->dp_pll = DP_PLL0 | DP_PLL1;
> +		break;
> +	default:
> +		dev_err(cdns_phy->dev, "Unsupported PHY configuration\n");
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  /*
>   * Enable or disable PLL for selected lanes.
>   */
> @@ -1554,6 +1584,8 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  		return -EINVAL;
>  	}
>  
> +	cdns_torrent_dp_get_pll(cdns_phy, TYPE_NONE);
> +
>  	cdns_torrent_dp_common_init(cdns_phy, inst);
>  
>  	return cdns_torrent_dp_start(cdns_phy, inst, phy);
> 

[PATCH 11/14] phy: cadence-torrent: Add multilink DP support

[Swapnil Jakhade]

Add multilink support for DP. This needs changes in functions
configuring default single link DP with master lane 0 to support
non-zero master lane values and associated PLL configurations.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 498 +++++++++++++---------
 1 file changed, 289 insertions(+), 209 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 44e28ea8ffa7..becbf8456b2d 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -62,16 +62,11 @@
  */
 #define PHY_AUX_CTRL			0x04
 #define PHY_RESET			0x20
-#define PMA_TX_ELEC_IDLE_MASK		0xF0U
 #define PMA_TX_ELEC_IDLE_SHIFT		4
-#define PHY_L00_RESET_N_MASK		0x01U
 #define PHY_PMA_XCVR_PLLCLK_EN		0x24
 #define PHY_PMA_XCVR_PLLCLK_EN_ACK	0x28
 #define PHY_PMA_XCVR_POWER_STATE_REQ	0x2c
-#define PHY_POWER_STATE_LN_0	0x0000
-#define PHY_POWER_STATE_LN_1	0x0008
-#define PHY_POWER_STATE_LN_2	0x0010
-#define PHY_POWER_STATE_LN_3	0x0018
+#define PHY_POWER_STATE_LN(ln)		((ln) * 8)
 #define PMA_XCVR_POWER_STATE_REQ_LN_MASK	0x3FU
 #define PHY_PMA_XCVR_POWER_STATE_ACK	0x30
 #define PHY_PMA_CMN_READY		0x34
@@ -834,74 +829,90 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
 	/* Setting VCO for 10.8GHz */
 	case 2700:
 	case 5400:
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
+		if (cdns_phy->dp_pll & DP_PLL0)
+			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
+
+		if (cdns_phy->dp_pll & DP_PLL1) {
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
+		}
 		break;
 	/* Setting VCO for 9.72GHz */
 	case 1620:
 	case 2430:
 	case 3240:
-		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		if (cdns_phy->dp_pll & DP_PLL0) {
+			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
+			cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
+			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
+			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+			cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+		}
+		if (cdns_phy->dp_pll & DP_PLL1) {
+			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		}
 		break;
 	/* Setting VCO for 8.64GHz */
 	case 2160:
 	case 4320:
-		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		if (cdns_phy->dp_pll & DP_PLL0) {
+			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
+			cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
+			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
+			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+			cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+		}
+		if (cdns_phy->dp_pll & DP_PLL1) {
+			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		}
 		break;
 	/* Setting VCO for 8.1GHz */
 	case 8100:
-		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
-		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
-		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		if (cdns_phy->dp_pll & DP_PLL0) {
+			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
+			cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
+			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
+			cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+		}
+		if (cdns_phy->dp_pll & DP_PLL1) {
+			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
+			cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
+			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+		}
 		break;
 	}
 }
@@ -934,43 +945,36 @@ static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy,
  * Enable or disable PLL for selected lanes.
  */
 static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
+				      struct cdns_torrent_inst *inst,
 				      struct phy_configure_opts_dp *dp,
 				      bool enable)
 {
-	u32 rd_val;
-	u32 ret;
 	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
+	u32 rd_val, i, pll_ack_val;
+	int ret;
 
 	/*
 	 * Used to determine, which bits to check for or enable in
 	 * PHY_PMA_XCVR_PLLCLK_EN register.
 	 */
-	u32 pll_bits;
+	u32 pll_bits = 0;
 	/* Used to enable or disable lanes. */
 	u32 pll_val;
 
-	/* Select values of registers and mask, depending on enabled lane
-	 * count.
-	 */
-	switch (dp->lanes) {
-	/* lane 0 */
-	case (1):
-		pll_bits = 0x00000001;
-		break;
-	/* lanes 0-1 */
-	case (2):
-		pll_bits = 0x00000003;
-		break;
-	/* lanes 0-3, all */
-	default:
-		pll_bits = 0x0000000F;
-		break;
-	}
+	/* Select values of registers and mask, depending on enabled lane count. */
+	pll_val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
 
-	if (enable)
-		pll_val = pll_bits;
-	else
-		pll_val = 0x00000000;
+	if (enable) {
+		for (i = 0; i < dp->lanes; i++)
+			pll_bits |= (0x01U << (inst->mlane + i));
+		pll_val |= pll_bits;
+		pll_ack_val = pll_bits;
+	} else {
+		for (i = 0; i < inst->num_lanes; i++)
+			pll_bits |= (0x01U << (inst->mlane + i));
+		pll_val &= (~pll_bits);
+		pll_ack_val = 0;
+	}
 
 	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
 
@@ -978,22 +982,24 @@ static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
 	ret = regmap_read_poll_timeout(regmap,
 				       PHY_PMA_XCVR_PLLCLK_EN_ACK,
 				       rd_val,
-				       (rd_val & pll_bits) == pll_val,
+				       (rd_val & pll_bits) == pll_ack_val,
 				       0, POLL_TIMEOUT_US);
 	ndelay(100);
 	return ret;
 }
 
 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
+					   struct cdns_torrent_inst *inst,
 					   u32 num_lanes,
 					   enum phy_powerstate powerstate)
 {
 	/* Register value for power state for a single byte. */
 	u32 value_part;
 	u32 value;
-	u32 mask;
+	u32 mask = 0;
 	u32 read_val;
-	u32 ret;
+	int ret;
+	u32 i;
 	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
 
 	switch (powerstate) {
@@ -1009,29 +1015,12 @@ static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
 		break;
 	}
 
-	/* Select values of registers and mask, depending on enabled
-	 * lane count.
-	 */
-	switch (num_lanes) {
-	/* lane 0 */
-	case (1):
-		value = value_part;
-		mask = 0x0000003FU;
-		break;
-	/* lanes 0-1 */
-	case (2):
-		value = (value_part
-			 | (value_part << 8));
-		mask = 0x00003F3FU;
-		break;
-	/* lanes 0-3, all */
-	default:
-		value = (value_part
-			 | (value_part << 8)
-			 | (value_part << 16)
-			 | (value_part << 24));
-		mask = 0x3F3F3F3FU;
-		break;
+	/* Select values of registers and mask, depending on enabled lane count. */
+	value = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_POWER_STATE_REQ);
+
+	for (i = 0; i < num_lanes; i++) {
+		value |= (value_part << PHY_POWER_STATE_LN(inst->mlane + i));
+		mask |= (PMA_XCVR_POWER_STATE_REQ_LN_MASK << PHY_POWER_STATE_LN(inst->mlane + i));
 	}
 
 	/* Set power state A<n>. */
@@ -1046,7 +1035,8 @@ static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
 	return ret;
 }
 
-static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
+static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
+			       struct cdns_torrent_inst *inst, u32 num_lanes)
 {
 	unsigned int read_val;
 	int ret;
@@ -1057,7 +1047,7 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
 	 * master lane
 	 */
 	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
-				       read_val, read_val & 1,
+				       read_val, (read_val & (1 << inst->mlane)),
 				       0, POLL_TIMEOUT_US);
 	if (ret == -ETIMEDOUT) {
 		dev_err(cdns_phy->dev,
@@ -1067,12 +1057,12 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
 
 	ndelay(100);
 
-	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
+	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
 					      POWERSTATE_A2);
 	if (ret)
 		return ret;
 
-	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
+	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
 					      POWERSTATE_A0);
 
 	return ret;
@@ -1096,6 +1086,7 @@ static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
 }
 
 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
+					 struct cdns_torrent_inst *inst,
 					 u32 rate, u32 num_lanes)
 {
 	unsigned int clk_sel_val = 0;
@@ -1128,14 +1119,17 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
 		break;
 	}
 
-	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
-			       CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
-	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
-			       CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
+	if (cdns_phy->dp_pll & DP_PLL0)
+		cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
+				       CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
+
+	if (cdns_phy->dp_pll & DP_PLL1)
+		cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
+				       CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
 
 	/* PMA lane configuration to deal with multi-link operation */
 	for (i = 0; i < num_lanes; i++)
-		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
+		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + i],
 				       XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
 }
 
@@ -1144,49 +1138,89 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
  * set and PLL disable request was processed.
  */
 static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
+					  struct cdns_torrent_inst *inst,
 					  struct phy_configure_opts_dp *dp)
 {
-	u32 read_val, ret;
+	u32 read_val, field_val;
+	int ret;
 
-	/* Disable the cmn_pll0_en before re-programming the new data rate. */
-	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
+	/*
+	 * Disable the associated PLL (cmn_pll0_en or cmn_pll1_en) before
+	 * re-programming the new data rate.
+	 */
+	ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);
+	if (ret)
+		return ret;
+	field_val &= ~(cdns_phy->dp_pll);
+	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);
 
 	/*
 	 * Wait for PLL ready de-assertion.
 	 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
+	 * For PLL1 - PHY_PMA_CMN_CTRL2[3] == 1
 	 */
-	ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
-					     read_val,
-					     ((read_val >> 2) & 0x01) != 0,
-					     0, POLL_TIMEOUT_US);
-	if (ret)
-		return ret;
+	if (cdns_phy->dp_pll & DP_PLL0) {
+		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
+						     read_val,
+						     ((read_val >> 2) & 0x01) != 0,
+						     0, POLL_TIMEOUT_US);
+		if (ret)
+			return ret;
+	}
+
+	if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1) {
+		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
+						     read_val,
+						     ((read_val >> 3) & 0x01) != 0,
+						     0, POLL_TIMEOUT_US);
+		if (ret)
+			return ret;
+	}
 	ndelay(200);
 
 	/* DP Rate Change - VCO Output settings. */
-	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
-		/* PMA common configuration 19.2MHz */
-		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
-	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
-		/* PMA common configuration 25MHz */
-		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
-	else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
+	if (cdns_phy->nsubnodes == 1) {
+		if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
+			/* PMA common configuration 19.2MHz */
+			cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
+		else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
+			/* PMA common configuration 25MHz */
+			cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
+	}
+
+	if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
 		/* PMA common configuration 100MHz */
 		cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc);
 
-	cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
+	cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, dp->link_rate, dp->lanes);
 
-	/* Enable the cmn_pll0_en. */
-	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3);
+	/* Enable the associated PLL (cmn_pll0_en or cmn_pll1_en) */
+	ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);
+	if (ret)
+		return ret;
+	field_val |= cdns_phy->dp_pll;
+	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);
 
 	/*
 	 * Wait for PLL ready assertion.
 	 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
+	 * For PLL1 - PHY_PMA_CMN_CTRL2[1] == 1
 	 */
-	ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
-					     read_val,
-					     (read_val & 0x01) != 0,
-					     0, POLL_TIMEOUT_US);
+	if (cdns_phy->dp_pll & DP_PLL0) {
+		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
+						     read_val,
+						     (read_val & 0x01) != 0,
+						     0, POLL_TIMEOUT_US);
+		if (ret)
+			return ret;
+	}
+
+	if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1)
+		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
+						     read_val,
+						     ((read_val >> 1) & 0x01) != 0,
+						     0, POLL_TIMEOUT_US);
+
 	return ret;
 }
 
@@ -1254,6 +1288,7 @@ static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
 
 /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
 static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
+				       struct cdns_torrent_inst *inst,
 				       u32 num_lanes)
 {
 	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
@@ -1261,27 +1296,13 @@ static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
 					     PHY_PMA_XCVR_POWER_STATE_REQ);
 	u32 pll_clk_en = cdns_torrent_dp_read(regmap,
 					      PHY_PMA_XCVR_PLLCLK_EN);
+	u32 i;
 
-	/* Lane 0 is always enabled. */
-	pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
-		       PHY_POWER_STATE_LN_0);
-	pll_clk_en &= ~0x01U;
-
-	if (num_lanes > 1) {
-		/* lane 1 */
-		pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
-			       PHY_POWER_STATE_LN_1);
-		pll_clk_en &= ~(0x01U << 1);
-	}
+	for (i = 0; i < num_lanes; i++) {
+		pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK
+			     << PHY_POWER_STATE_LN(inst->mlane + i));
 
-	if (num_lanes > 2) {
-		/* lanes 2 and 3 */
-		pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
-			       PHY_POWER_STATE_LN_2);
-		pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
-			       PHY_POWER_STATE_LN_3);
-		pll_clk_en &= ~(0x01U << 2);
-		pll_clk_en &= ~(0x01U << 3);
+		pll_clk_en &= ~(0x01U << (inst->mlane + i));
 	}
 
 	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
@@ -1290,36 +1311,58 @@ static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
 
 /* Configure lane count as required. */
 static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
+				     struct cdns_torrent_inst *inst,
 				     struct phy_configure_opts_dp *dp)
 {
-	u32 value;
-	u32 ret;
 	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
 	u8 lane_mask = (1 << dp->lanes) - 1;
+	u8 pma_tx_elec_idle_mask = 0;
+	u32 value, i;
+	int ret;
+
+	lane_mask <<= inst->mlane;
 
 	value = cdns_torrent_dp_read(regmap, PHY_RESET);
+
 	/* clear pma_tx_elec_idle_ln_* bits. */
-	value &= ~PMA_TX_ELEC_IDLE_MASK;
+	for (i = 0; i < inst->num_lanes; i++)
+		pma_tx_elec_idle_mask |= 1 << (inst->mlane + i);
+
+	pma_tx_elec_idle_mask <<= PMA_TX_ELEC_IDLE_SHIFT;
+
+	value &= ~pma_tx_elec_idle_mask;
+
 	/* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
 	value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
-		 PMA_TX_ELEC_IDLE_MASK;
+		 pma_tx_elec_idle_mask;
+
 	cdns_torrent_dp_write(regmap, PHY_RESET, value);
 
-	/* reset the link by asserting phy_l00_reset_n low */
+	/* reset the link by asserting master lane phy_l0*_reset_n low */
 	cdns_torrent_dp_write(regmap, PHY_RESET,
-			      value & (~PHY_L00_RESET_N_MASK));
+			      value & (~(1 << inst->mlane)));
 
 	/*
-	 * Assert lane reset on unused lanes and lane 0 so they remain in reset
+	 * Assert lane reset on unused lanes and master lane so they remain in reset
 	 * and powered down when re-enabling the link
 	 */
-	value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
+	for (i = 0; i < inst->num_lanes; i++)
+		value &= (~(1 << (inst->mlane + i)));
+
+	for (i = 1; i < inst->num_lanes; i++)
+		value |= ((1 << (inst->mlane + i)) & lane_mask);
+
 	cdns_torrent_dp_write(regmap, PHY_RESET, value);
 
-	cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);
+	cdns_torrent_dp_set_a0_pll(cdns_phy, inst, inst->num_lanes);
 
 	/* release phy_l0*_reset_n based on used laneCount */
-	value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
+	for (i = 0; i < inst->num_lanes; i++)
+		value &= (~(1 << (inst->mlane + i)));
+
+	for (i = 0; i < inst->num_lanes; i++)
+		value |= ((1 << (inst->mlane + i)) & lane_mask);
+
 	cdns_torrent_dp_write(regmap, PHY_RESET, value);
 
 	/* Wait, until PHY gets ready after releasing PHY reset signal. */
@@ -1330,41 +1373,44 @@ static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
 	ndelay(100);
 
 	/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
-	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
+	value = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
+	value |= (1 << inst->mlane);
+	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, value);
 
-	ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);
+	ret = cdns_torrent_dp_run(cdns_phy, inst, dp->lanes);
 
 	return ret;
 }
 
 /* Configure link rate as required. */
 static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
+				    struct cdns_torrent_inst *inst,
 				    struct phy_configure_opts_dp *dp)
 {
-	u32 ret;
+	int ret;
 
-	ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
+	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
 					      POWERSTATE_A3);
 	if (ret)
 		return ret;
-	ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false);
+	ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, false);
 	if (ret)
 		return ret;
 	ndelay(200);
 
-	ret = cdns_torrent_dp_configure_rate(cdns_phy, dp);
+	ret = cdns_torrent_dp_configure_rate(cdns_phy, inst, dp);
 	if (ret)
 		return ret;
 	ndelay(200);
 
-	ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true);
+	ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, true);
 	if (ret)
 		return ret;
-	ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
+	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
 					      POWERSTATE_A2);
 	if (ret)
 		return ret;
-	ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
+	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
 					      POWERSTATE_A0);
 	if (ret)
 		return ret;
@@ -1375,44 +1421,45 @@ static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
 
 /* Configure voltage swing and pre-emphasis for all enabled lanes. */
 static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
+					 struct cdns_torrent_inst *inst,
 					 struct phy_configure_opts_dp *dp)
 {
 	u8 lane;
 	u16 val;
 
 	for (lane = 0; lane < dp->lanes; lane++) {
-		val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
+		val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
 					    TX_DIAG_ACYA);
 		/*
 		 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
 		 * current state of the analog TX driver.
 		 */
 		val |= TX_DIAG_ACYA_HBDC_MASK;
-		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
+		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
 				       TX_DIAG_ACYA, val);
 
-		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
+		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
 				       TX_TXCC_CTRL, 0x08A4);
 		val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
-		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
+		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
 				       DRV_DIAG_TX_DRV, val);
 		val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
-		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
+		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
 				       TX_TXCC_MGNFS_MULT_000,
 				       val);
 		val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
-		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
+		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
 				       TX_TXCC_CPOST_MULT_00,
 				       val);
 
-		val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
+		val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
 					    TX_DIAG_ACYA);
 		/*
 		 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
 		 * analog TX driver to reflect the new programmed one.
 		 */
 		val &= ~TX_DIAG_ACYA_HBDC_MASK;
-		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
+		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
 				       TX_DIAG_ACYA, val);
 	}
 };
@@ -1431,7 +1478,7 @@ static int cdns_torrent_dp_configure(struct phy *phy,
 	}
 
 	if (opts->dp.set_lanes) {
-		ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp);
+		ret = cdns_torrent_dp_set_lanes(cdns_phy, inst, &opts->dp);
 		if (ret) {
 			dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
 			return ret;
@@ -1439,7 +1486,7 @@ static int cdns_torrent_dp_configure(struct phy *phy,
 	}
 
 	if (opts->dp.set_rate) {
-		ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp);
+		ret = cdns_torrent_dp_set_rate(cdns_phy, inst, &opts->dp);
 		if (ret) {
 			dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
 			return ret;
@@ -1447,7 +1494,7 @@ static int cdns_torrent_dp_configure(struct phy *phy,
 	}
 
 	if (opts->dp.set_voltages)
-		cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp);
+		cdns_torrent_dp_set_voltages(cdns_phy, inst, &opts->dp);
 
 	return ret;
 }
@@ -1507,6 +1554,7 @@ static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
 {
 	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
 	unsigned char lane_bits;
+	u32 val;
 
 	cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
 
@@ -1514,37 +1562,46 @@ static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
 	 * Set lines power state to A0
 	 * Set lines pll clk enable to 0
 	 */
-	cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes);
+	cdns_torrent_dp_set_a0_pll(cdns_phy, inst, inst->num_lanes);
 
 	/*
 	 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
 	 * used lanes
 	 */
 	lane_bits = (1 << inst->num_lanes) - 1;
-	cdns_torrent_dp_write(regmap, PHY_RESET,
-			      ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
+	lane_bits <<= inst->mlane;
+
+	val = cdns_torrent_dp_read(regmap, PHY_RESET);
+	val |= (0xF & lane_bits);
+	val &= ~(lane_bits << 4);
+	cdns_torrent_dp_write(regmap, PHY_RESET, val);
 
 	/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
-	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
+	val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
+	val |= (1 << inst->mlane);
+	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, val);
 
 	/*
 	 * PHY PMA registers configuration functions
 	 * Initialize PHY with max supported link rate, without SSC.
 	 */
-	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
-		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
-							cdns_phy->max_bit_rate,
-							false);
-	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
-		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
-						      cdns_phy->max_bit_rate,
-						      false);
-	else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
+	if (cdns_phy->nsubnodes == 1) {
+		if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
+			cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
+								cdns_phy->max_bit_rate,
+								false);
+		else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
+			cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
+							      cdns_phy->max_bit_rate,
+							      false);
+	}
+
+	if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
 		cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy,
 						       cdns_phy->max_bit_rate,
 						       false);
 
-	cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
+	cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, cdns_phy->max_bit_rate,
 				     inst->num_lanes);
 
 	/* take out of reset */
@@ -1563,7 +1620,7 @@ static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy,
 	if (ret)
 		return ret;
 
-	ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes);
+	ret = cdns_torrent_dp_run(cdns_phy, inst, inst->num_lanes);
 
 	return ret;
 }
@@ -1591,6 +1648,20 @@ static int cdns_torrent_dp_init(struct phy *phy)
 	return cdns_torrent_dp_start(cdns_phy, inst, phy);
 }
 
+static int cdns_torrent_dp_multilink_init(struct cdns_torrent_phy *cdns_phy,
+					  struct cdns_torrent_inst *inst,
+					  struct phy *phy)
+{
+	if (cdns_phy->ref_clk_rate != CLK_100_MHZ) {
+		dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
+		return -EINVAL;
+	}
+
+	cdns_torrent_dp_common_init(cdns_phy, inst);
+
+	return cdns_torrent_dp_start(cdns_phy, inst, phy);
+}
+
 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
 {
 	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
@@ -1877,8 +1948,11 @@ static int cdns_torrent_phy_init(struct phy *phy)
 	u32 num_regs;
 	int i, j;
 
-	if (cdns_phy->nsubnodes > 1)
+	if (cdns_phy->nsubnodes > 1) {
+		if (phy_type == TYPE_DP)
+			return cdns_torrent_dp_multilink_init(cdns_phy, inst, phy);
 		return 0;
+	}
 
 	/**
 	 * Spread spectrum generation is not required or supported
@@ -2122,6 +2196,12 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
 			}
 		}
 
+		if (phy_t1 == TYPE_DP) {
+			ret = cdns_torrent_dp_get_pll(cdns_phy, phy_t2);
+			if (ret)
+				return ret;
+		}
+
 		reset_control_deassert(cdns_phy->phys[node].lnk_rst);
 	}
 
-- 
2.26.1

Re: [PATCH 11/14] phy: cadence-torrent: Add multilink DP support

[Kishon Vijay Abraham I]

Hi Swapnil,

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Add multilink support for DP. This needs changes in functions
> configuring default single link DP with master lane 0 to support
> non-zero master lane values and associated PLL configurations.
>

It's better to mention here you are adding multi-link DP support only
for 100MHz reference clock.

> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 498 +++++++++++++---------
>  1 file changed, 289 insertions(+), 209 deletions(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index 44e28ea8ffa7..becbf8456b2d 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -62,16 +62,11 @@
>   */
>  #define PHY_AUX_CTRL			0x04
>  #define PHY_RESET			0x20
> -#define PMA_TX_ELEC_IDLE_MASK		0xF0U
>  #define PMA_TX_ELEC_IDLE_SHIFT		4
> -#define PHY_L00_RESET_N_MASK		0x01U
>  #define PHY_PMA_XCVR_PLLCLK_EN		0x24
>  #define PHY_PMA_XCVR_PLLCLK_EN_ACK	0x28
>  #define PHY_PMA_XCVR_POWER_STATE_REQ	0x2c
> -#define PHY_POWER_STATE_LN_0	0x0000
> -#define PHY_POWER_STATE_LN_1	0x0008
> -#define PHY_POWER_STATE_LN_2	0x0010
> -#define PHY_POWER_STATE_LN_3	0x0018
> +#define PHY_POWER_STATE_LN(ln)		((ln) * 8)
>  #define PMA_XCVR_POWER_STATE_REQ_LN_MASK	0x3FU
>  #define PHY_PMA_XCVR_POWER_STATE_ACK	0x30
>  #define PHY_PMA_CMN_READY		0x34
> @@ -834,74 +829,90 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
>  	/* Setting VCO for 10.8GHz */
>  	case 2700:
>  	case 5400:
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
> +		if (cdns_phy->dp_pll & DP_PLL0)
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
> +
> +		if (cdns_phy->dp_pll & DP_PLL1) {
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
> +		}
>  		break;
>  	/* Setting VCO for 9.72GHz */
>  	case 1620:
>  	case 2430:
>  	case 3240:
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
> +		if (cdns_phy->dp_pll & DP_PLL0) {
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
> +		}
> +		if (cdns_phy->dp_pll & DP_PLL1) {
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
> +		}
>  		break;
>  	/* Setting VCO for 8.64GHz */
>  	case 2160:
>  	case 4320:
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
> +		if (cdns_phy->dp_pll & DP_PLL0) {
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
> +		}
> +		if (cdns_phy->dp_pll & DP_PLL1) {
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
> +		}
>  		break;
>  	/* Setting VCO for 8.1GHz */
>  	case 8100:
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
> -		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
> -		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
> -		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
> +		if (cdns_phy->dp_pll & DP_PLL0) {
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
> +			cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
> +		}
> +		if (cdns_phy->dp_pll & DP_PLL1) {
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
> +			cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
> +			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
> +		}
>  		break;
>  	}
>  }
> @@ -934,43 +945,36 @@ static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy,
>   * Enable or disable PLL for selected lanes.
>   */
>  static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
> +				      struct cdns_torrent_inst *inst,
>  				      struct phy_configure_opts_dp *dp,
>  				      bool enable)
>  {
> -	u32 rd_val;
> -	u32 ret;
>  	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
> +	u32 rd_val, i, pll_ack_val;
> +	int ret;
>  
>  	/*
>  	 * Used to determine, which bits to check for or enable in
>  	 * PHY_PMA_XCVR_PLLCLK_EN register.
>  	 */
> -	u32 pll_bits;
> +	u32 pll_bits = 0;
>  	/* Used to enable or disable lanes. */
>  	u32 pll_val;
>  
> -	/* Select values of registers and mask, depending on enabled lane
> -	 * count.
> -	 */
> -	switch (dp->lanes) {
> -	/* lane 0 */
> -	case (1):
> -		pll_bits = 0x00000001;
> -		break;
> -	/* lanes 0-1 */
> -	case (2):
> -		pll_bits = 0x00000003;
> -		break;
> -	/* lanes 0-3, all */
> -	default:
> -		pll_bits = 0x0000000F;
> -		break;
> -	}
> +	/* Select values of registers and mask, depending on enabled lane count. */
> +	pll_val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
>  
> -	if (enable)
> -		pll_val = pll_bits;
> -	else
> -		pll_val = 0x00000000;
> +	if (enable) {
> +		for (i = 0; i < dp->lanes; i++)
> +			pll_bits |= (0x01U << (inst->mlane + i));
> +		pll_val |= pll_bits;
> +		pll_ack_val = pll_bits;
> +	} else {
> +		for (i = 0; i < inst->num_lanes; i++)
> +			pll_bits |= (0x01U << (inst->mlane + i));
> +		pll_val &= (~pll_bits);
> +		pll_ack_val = 0;
> +	}
>  
>  	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
>  
> @@ -978,22 +982,24 @@ static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
>  	ret = regmap_read_poll_timeout(regmap,
>  				       PHY_PMA_XCVR_PLLCLK_EN_ACK,
>  				       rd_val,
> -				       (rd_val & pll_bits) == pll_val,
> +				       (rd_val & pll_bits) == pll_ack_val,
>  				       0, POLL_TIMEOUT_US);
>  	ndelay(100);
>  	return ret;
>  }
>  
>  static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
> +					   struct cdns_torrent_inst *inst,
>  					   u32 num_lanes,
>  					   enum phy_powerstate powerstate)
>  {
>  	/* Register value for power state for a single byte. */
>  	u32 value_part;
>  	u32 value;
> -	u32 mask;
> +	u32 mask = 0;
>  	u32 read_val;
> -	u32 ret;
> +	int ret;
> +	u32 i;
>  	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
>  
>  	switch (powerstate) {
> @@ -1009,29 +1015,12 @@ static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
>  		break;
>  	}
>  
> -	/* Select values of registers and mask, depending on enabled
> -	 * lane count.
> -	 */
> -	switch (num_lanes) {
> -	/* lane 0 */
> -	case (1):
> -		value = value_part;
> -		mask = 0x0000003FU;
> -		break;
> -	/* lanes 0-1 */
> -	case (2):
> -		value = (value_part
> -			 | (value_part << 8));
> -		mask = 0x00003F3FU;
> -		break;
> -	/* lanes 0-3, all */
> -	default:
> -		value = (value_part
> -			 | (value_part << 8)
> -			 | (value_part << 16)
> -			 | (value_part << 24));
> -		mask = 0x3F3F3F3FU;
> -		break;
> +	/* Select values of registers and mask, depending on enabled lane count. */
> +	value = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_POWER_STATE_REQ);
> +
> +	for (i = 0; i < num_lanes; i++) {
> +		value |= (value_part << PHY_POWER_STATE_LN(inst->mlane + i));
> +		mask |= (PMA_XCVR_POWER_STATE_REQ_LN_MASK << PHY_POWER_STATE_LN(inst->mlane + i));
>  	}
>  
>  	/* Set power state A<n>. */
> @@ -1046,7 +1035,8 @@ static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
>  	return ret;
>  }
>  
> -static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
> +static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
> +			       struct cdns_torrent_inst *inst, u32 num_lanes)
>  {
>  	unsigned int read_val;
>  	int ret;
> @@ -1057,7 +1047,7 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
>  	 * master lane
>  	 */
>  	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
> -				       read_val, read_val & 1,
> +				       read_val, (read_val & (1 << inst->mlane)),
>  				       0, POLL_TIMEOUT_US);
>  	if (ret == -ETIMEDOUT) {
>  		dev_err(cdns_phy->dev,
> @@ -1067,12 +1057,12 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
>  
>  	ndelay(100);
>  
> -	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
> +	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
>  					      POWERSTATE_A2);
>  	if (ret)
>  		return ret;
>  
> -	ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
> +	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
>  					      POWERSTATE_A0);
>  
>  	return ret;
> @@ -1096,6 +1086,7 @@ static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
>  }
>  
>  static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
> +					 struct cdns_torrent_inst *inst,
>  					 u32 rate, u32 num_lanes)
>  {
>  	unsigned int clk_sel_val = 0;
> @@ -1128,14 +1119,17 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
>  		break;
>  	}
>  
> -	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
> -			       CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
> -	cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
> -			       CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
> +	if (cdns_phy->dp_pll & DP_PLL0)
> +		cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
> +				       CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
> +
> +	if (cdns_phy->dp_pll & DP_PLL1)
> +		cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
> +				       CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
>  
>  	/* PMA lane configuration to deal with multi-link operation */
>  	for (i = 0; i < num_lanes; i++)
> -		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
> +		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + i],
>  				       XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
>  }
>  
> @@ -1144,49 +1138,89 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
>   * set and PLL disable request was processed.
>   */
>  static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
> +					  struct cdns_torrent_inst *inst,
>  					  struct phy_configure_opts_dp *dp)
>  {
> -	u32 read_val, ret;
> +	u32 read_val, field_val;
> +	int ret;
>  
> -	/* Disable the cmn_pll0_en before re-programming the new data rate. */
> -	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
> +	/*
> +	 * Disable the associated PLL (cmn_pll0_en or cmn_pll1_en) before
> +	 * re-programming the new data rate.
> +	 */
> +	ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);
> +	if (ret)
> +		return ret;
> +	field_val &= ~(cdns_phy->dp_pll);
> +	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);
>  
>  	/*
>  	 * Wait for PLL ready de-assertion.
>  	 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
> +	 * For PLL1 - PHY_PMA_CMN_CTRL2[3] == 1
>  	 */
> -	ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
> -					     read_val,
> -					     ((read_val >> 2) & 0x01) != 0,
> -					     0, POLL_TIMEOUT_US);
> -	if (ret)
> -		return ret;
> +	if (cdns_phy->dp_pll & DP_PLL0) {
> +		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
> +						     read_val,
> +						     ((read_val >> 2) & 0x01) != 0,
> +						     0, POLL_TIMEOUT_US);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1) {
> +		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
> +						     read_val,
> +						     ((read_val >> 3) & 0x01) != 0,
> +						     0, POLL_TIMEOUT_US);
> +		if (ret)
> +			return ret;
> +	}
>  	ndelay(200);
>  
>  	/* DP Rate Change - VCO Output settings. */
> -	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
> -		/* PMA common configuration 19.2MHz */
> -		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
> -	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
> -		/* PMA common configuration 25MHz */
> -		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
> -	else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
> +	if (cdns_phy->nsubnodes == 1) {

I think this condition is not required here. You are adding this since
you are not adding multi-link support except for 100MHz.

Ideally all this chech should be done somewhere during the initialization.
> +		if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
> +			/* PMA common configuration 19.2MHz */
> +			cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
> +		else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
> +			/* PMA common configuration 25MHz */
> +			cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
> +	}
> +
> +	if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
>  		/* PMA common configuration 100MHz */
>  		cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc);
>  
> -	cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
> +	cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, dp->link_rate, dp->lanes);
>  
> -	/* Enable the cmn_pll0_en. */
> -	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3);
> +	/* Enable the associated PLL (cmn_pll0_en or cmn_pll1_en) */
> +	ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);
> +	if (ret)
> +		return ret;
> +	field_val |= cdns_phy->dp_pll;
> +	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);
>  
>  	/*
>  	 * Wait for PLL ready assertion.
>  	 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
> +	 * For PLL1 - PHY_PMA_CMN_CTRL2[1] == 1
>  	 */
> -	ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
> -					     read_val,
> -					     (read_val & 0x01) != 0,
> -					     0, POLL_TIMEOUT_US);
> +	if (cdns_phy->dp_pll & DP_PLL0) {
> +		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
> +						     read_val,
> +						     (read_val & 0x01) != 0,
> +						     0, POLL_TIMEOUT_US);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1)
> +		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
> +						     read_val,
> +						     ((read_val >> 1) & 0x01) != 0,
> +						     0, POLL_TIMEOUT_US);
> +
>  	return ret;
>  }
>  
> @@ -1254,6 +1288,7 @@ static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
>  
>  /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
>  static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
> +				       struct cdns_torrent_inst *inst,
>  				       u32 num_lanes)
>  {
>  	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
> @@ -1261,27 +1296,13 @@ static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
>  					     PHY_PMA_XCVR_POWER_STATE_REQ);
>  	u32 pll_clk_en = cdns_torrent_dp_read(regmap,
>  					      PHY_PMA_XCVR_PLLCLK_EN);
> +	u32 i;
>  
> -	/* Lane 0 is always enabled. */
> -	pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
> -		       PHY_POWER_STATE_LN_0);
> -	pll_clk_en &= ~0x01U;
> -
> -	if (num_lanes > 1) {
> -		/* lane 1 */
> -		pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
> -			       PHY_POWER_STATE_LN_1);
> -		pll_clk_en &= ~(0x01U << 1);
> -	}
> +	for (i = 0; i < num_lanes; i++) {
> +		pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK
> +			     << PHY_POWER_STATE_LN(inst->mlane + i));
>  
> -	if (num_lanes > 2) {
> -		/* lanes 2 and 3 */
> -		pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
> -			       PHY_POWER_STATE_LN_2);
> -		pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
> -			       PHY_POWER_STATE_LN_3);
> -		pll_clk_en &= ~(0x01U << 2);
> -		pll_clk_en &= ~(0x01U << 3);
> +		pll_clk_en &= ~(0x01U << (inst->mlane + i));
>  	}
>  
>  	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
> @@ -1290,36 +1311,58 @@ static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
>  
>  /* Configure lane count as required. */
>  static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
> +				     struct cdns_torrent_inst *inst,
>  				     struct phy_configure_opts_dp *dp)
>  {
> -	u32 value;
> -	u32 ret;
>  	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
>  	u8 lane_mask = (1 << dp->lanes) - 1;
> +	u8 pma_tx_elec_idle_mask = 0;
> +	u32 value, i;
> +	int ret;
> +
> +	lane_mask <<= inst->mlane;
>  
>  	value = cdns_torrent_dp_read(regmap, PHY_RESET);
> +
>  	/* clear pma_tx_elec_idle_ln_* bits. */
> -	value &= ~PMA_TX_ELEC_IDLE_MASK;
> +	for (i = 0; i < inst->num_lanes; i++)
> +		pma_tx_elec_idle_mask |= 1 << (inst->mlane + i);
> +
> +	pma_tx_elec_idle_mask <<= PMA_TX_ELEC_IDLE_SHIFT;
> +
> +	value &= ~pma_tx_elec_idle_mask;
> +
>  	/* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
>  	value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
> -		 PMA_TX_ELEC_IDLE_MASK;
> +		 pma_tx_elec_idle_mask;
> +
>  	cdns_torrent_dp_write(regmap, PHY_RESET, value);
>  
> -	/* reset the link by asserting phy_l00_reset_n low */
> +	/* reset the link by asserting master lane phy_l0*_reset_n low */
>  	cdns_torrent_dp_write(regmap, PHY_RESET,
> -			      value & (~PHY_L00_RESET_N_MASK));
> +			      value & (~(1 << inst->mlane)));
>  
>  	/*
> -	 * Assert lane reset on unused lanes and lane 0 so they remain in reset
> +	 * Assert lane reset on unused lanes and master lane so they remain in reset
>  	 * and powered down when re-enabling the link
>  	 */
> -	value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
> +	for (i = 0; i < inst->num_lanes; i++)
> +		value &= (~(1 << (inst->mlane + i)));
> +
> +	for (i = 1; i < inst->num_lanes; i++)
> +		value |= ((1 << (inst->mlane + i)) & lane_mask);
> +
>  	cdns_torrent_dp_write(regmap, PHY_RESET, value);
>  
> -	cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);
> +	cdns_torrent_dp_set_a0_pll(cdns_phy, inst, inst->num_lanes);
>  
>  	/* release phy_l0*_reset_n based on used laneCount */
> -	value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
> +	for (i = 0; i < inst->num_lanes; i++)
> +		value &= (~(1 << (inst->mlane + i)));
> +
> +	for (i = 0; i < inst->num_lanes; i++)
> +		value |= ((1 << (inst->mlane + i)) & lane_mask);
> +
>  	cdns_torrent_dp_write(regmap, PHY_RESET, value);
>  
>  	/* Wait, until PHY gets ready after releasing PHY reset signal. */
> @@ -1330,41 +1373,44 @@ static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
>  	ndelay(100);
>  
>  	/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
> -	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
> +	value = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
> +	value |= (1 << inst->mlane);
> +	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, value);
>  
> -	ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);
> +	ret = cdns_torrent_dp_run(cdns_phy, inst, dp->lanes);
>  
>  	return ret;
>  }
>  
>  /* Configure link rate as required. */
>  static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
> +				    struct cdns_torrent_inst *inst,
>  				    struct phy_configure_opts_dp *dp)
>  {
> -	u32 ret;
> +	int ret;
>  
> -	ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
> +	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
>  					      POWERSTATE_A3);
>  	if (ret)
>  		return ret;
> -	ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false);
> +	ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, false);
>  	if (ret)
>  		return ret;
>  	ndelay(200);
>  
> -	ret = cdns_torrent_dp_configure_rate(cdns_phy, dp);
> +	ret = cdns_torrent_dp_configure_rate(cdns_phy, inst, dp);
>  	if (ret)
>  		return ret;
>  	ndelay(200);
>  
> -	ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true);
> +	ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, true);
>  	if (ret)
>  		return ret;
> -	ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
> +	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
>  					      POWERSTATE_A2);
>  	if (ret)
>  		return ret;
> -	ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
> +	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
>  					      POWERSTATE_A0);
>  	if (ret)
>  		return ret;
> @@ -1375,44 +1421,45 @@ static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
>  
>  /* Configure voltage swing and pre-emphasis for all enabled lanes. */
>  static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
> +					 struct cdns_torrent_inst *inst,
>  					 struct phy_configure_opts_dp *dp)
>  {
>  	u8 lane;
>  	u16 val;
>  
>  	for (lane = 0; lane < dp->lanes; lane++) {
> -		val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
> +		val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
>  					    TX_DIAG_ACYA);
>  		/*
>  		 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
>  		 * current state of the analog TX driver.
>  		 */
>  		val |= TX_DIAG_ACYA_HBDC_MASK;
> -		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> +		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
>  				       TX_DIAG_ACYA, val);
>  
> -		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> +		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
>  				       TX_TXCC_CTRL, 0x08A4);
>  		val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
> -		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> +		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
>  				       DRV_DIAG_TX_DRV, val);
>  		val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
> -		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> +		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
>  				       TX_TXCC_MGNFS_MULT_000,
>  				       val);
>  		val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
> -		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> +		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
>  				       TX_TXCC_CPOST_MULT_00,
>  				       val);
>  
> -		val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
> +		val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
>  					    TX_DIAG_ACYA);
>  		/*
>  		 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
>  		 * analog TX driver to reflect the new programmed one.
>  		 */
>  		val &= ~TX_DIAG_ACYA_HBDC_MASK;
> -		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
> +		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
>  				       TX_DIAG_ACYA, val);
>  	}
>  };
> @@ -1431,7 +1478,7 @@ static int cdns_torrent_dp_configure(struct phy *phy,
>  	}
>  
>  	if (opts->dp.set_lanes) {
> -		ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp);
> +		ret = cdns_torrent_dp_set_lanes(cdns_phy, inst, &opts->dp);
>  		if (ret) {
>  			dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
>  			return ret;
> @@ -1439,7 +1486,7 @@ static int cdns_torrent_dp_configure(struct phy *phy,
>  	}
>  
>  	if (opts->dp.set_rate) {
> -		ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp);
> +		ret = cdns_torrent_dp_set_rate(cdns_phy, inst, &opts->dp);
>  		if (ret) {
>  			dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
>  			return ret;
> @@ -1447,7 +1494,7 @@ static int cdns_torrent_dp_configure(struct phy *phy,
>  	}
>  
>  	if (opts->dp.set_voltages)
> -		cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp);
> +		cdns_torrent_dp_set_voltages(cdns_phy, inst, &opts->dp);
>  
>  	return ret;
>  }
> @@ -1507,6 +1554,7 @@ static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
>  {
>  	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
>  	unsigned char lane_bits;
> +	u32 val;
>  
>  	cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
>  
> @@ -1514,37 +1562,46 @@ static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
>  	 * Set lines power state to A0
>  	 * Set lines pll clk enable to 0
>  	 */
> -	cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes);
> +	cdns_torrent_dp_set_a0_pll(cdns_phy, inst, inst->num_lanes);
>  
>  	/*
>  	 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
>  	 * used lanes
>  	 */
>  	lane_bits = (1 << inst->num_lanes) - 1;
> -	cdns_torrent_dp_write(regmap, PHY_RESET,
> -			      ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
> +	lane_bits <<= inst->mlane;
> +
> +	val = cdns_torrent_dp_read(regmap, PHY_RESET);
> +	val |= (0xF & lane_bits);
> +	val &= ~(lane_bits << 4);
> +	cdns_torrent_dp_write(regmap, PHY_RESET, val);
>  
>  	/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
> -	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
> +	val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
> +	val |= (1 << inst->mlane);
> +	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, val);
>  
>  	/*
>  	 * PHY PMA registers configuration functions
>  	 * Initialize PHY with max supported link rate, without SSC.
>  	 */
> -	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
> -		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
> -							cdns_phy->max_bit_rate,
> -							false);
> -	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
> -		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
> -						      cdns_phy->max_bit_rate,
> -						      false);
> -	else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
> +	if (cdns_phy->nsubnodes == 1) {

same comment here..
> +		if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
> +			cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
> +								cdns_phy->max_bit_rate,
> +								false);
> +		else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
> +			cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
> +							      cdns_phy->max_bit_rate,
> +							      false);
> +	}
> +
> +	if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
>  		cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy,
>  						       cdns_phy->max_bit_rate,
>  						       false);
>  
> -	cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
> +	cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, cdns_phy->max_bit_rate,
>  				     inst->num_lanes);
>  
>  	/* take out of reset */
> @@ -1563,7 +1620,7 @@ static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy,
>  	if (ret)
>  		return ret;
>  
> -	ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes);
> +	ret = cdns_torrent_dp_run(cdns_phy, inst, inst->num_lanes);
>  
>  	return ret;
>  }
> @@ -1591,6 +1648,20 @@ static int cdns_torrent_dp_init(struct phy *phy)
>  	return cdns_torrent_dp_start(cdns_phy, inst, phy);
>  }
>  
> +static int cdns_torrent_dp_multilink_init(struct cdns_torrent_phy *cdns_phy,
> +					  struct cdns_torrent_inst *inst,
> +					  struct phy *phy)
> +{
> +	if (cdns_phy->ref_clk_rate != CLK_100_MHZ) {
> +		dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
> +		return -EINVAL;
> +	}
> +
> +	cdns_torrent_dp_common_init(cdns_phy, inst);
> +
> +	return cdns_torrent_dp_start(cdns_phy, inst, phy);
> +}
> +
>  static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
>  {
>  	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
> @@ -1877,8 +1948,11 @@ static int cdns_torrent_phy_init(struct phy *phy)
>  	u32 num_regs;
>  	int i, j;
>  
> -	if (cdns_phy->nsubnodes > 1)
> +	if (cdns_phy->nsubnodes > 1) {
> +		if (phy_type == TYPE_DP)
> +			return cdns_torrent_dp_multilink_init(cdns_phy, inst, phy);
>  		return 0;
> +	}
>  
>  	/**
>  	 * Spread spectrum generation is not required or supported
> @@ -2122,6 +2196,12 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
>  			}
>  		}
>  
> +		if (phy_t1 == TYPE_DP) {
> +			ret = cdns_torrent_dp_get_pll(cdns_phy, phy_t2);
> +			if (ret)
> +				return ret;
> +		}
> +
>  		reset_control_deassert(cdns_phy->phys[node].lnk_rst);
>  	}

Swapnil, IMO this patch should be split. one to support non zero master
lane for DP and the other for 100MHz DP multilink.

Later when say 19.2MHz DP multilink support is added, it should look
similar to how it's added for 100MHz DP multilink patch.

Please also provide the details of testing (here or in the cover letter).

Thanks
Kishon

[PATCH 12/14] phy: cadence-torrent: Add PCIe + DP multilink configuration

[Swapnil Jakhade]

Add PCIe + DP no SSC multilink configuration sequences.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 131 ++++++++++++++++++++++
 1 file changed, 131 insertions(+)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index becbf8456b2d..bf37569c6c51 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -2572,6 +2572,77 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev)
 	return 0;
 }
 
+/* PCIe and DP link configuration */
+static struct cdns_reg_pairs pcie_dp_link_cmn_regs[] = {
+	{0x0003, PHY_PLL_CFG},
+	{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
+	{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}
+};
+
+static struct cdns_reg_pairs pcie_dp_xcvr_diag_ln_regs[] = {
+	{0x0000, XCVR_DIAG_HSCLK_SEL},
+	{0x0001, XCVR_DIAG_HSCLK_DIV},
+	{0x0012, XCVR_DIAG_PLLDRC_CTRL}
+};
+
+static struct cdns_reg_pairs dp_pcie_xcvr_diag_ln_regs[] = {
+	{0x0001, XCVR_DIAG_HSCLK_SEL},
+	{0x0009, XCVR_DIAG_PLLDRC_CTRL}
+};
+
+static struct cdns_torrent_vals pcie_dp_link_cmn_vals = {
+	.reg_pairs = pcie_dp_link_cmn_regs,
+	.num_regs = ARRAY_SIZE(pcie_dp_link_cmn_regs),
+};
+
+static struct cdns_torrent_vals pcie_dp_xcvr_diag_ln_vals = {
+	.reg_pairs = pcie_dp_xcvr_diag_ln_regs,
+	.num_regs = ARRAY_SIZE(pcie_dp_xcvr_diag_ln_regs),
+};
+
+static struct cdns_torrent_vals dp_pcie_xcvr_diag_ln_vals = {
+	.reg_pairs = dp_pcie_xcvr_diag_ln_regs,
+	.num_regs = ARRAY_SIZE(dp_pcie_xcvr_diag_ln_regs),
+};
+
+/* DP Multilink, 100 MHz Ref clk, no SSC */
+static struct cdns_reg_pairs dp_100_no_ssc_cmn_regs[] = {
+	{0x007F, CMN_TXPUCAL_TUNE},
+	{0x007F, CMN_TXPDCAL_TUNE}
+};
+
+static struct cdns_reg_pairs dp_100_no_ssc_tx_ln_regs[] = {
+	{0x00FB, TX_PSC_A0},
+	{0x04AA, TX_PSC_A2},
+	{0x04AA, TX_PSC_A3},
+	{0x000F, XCVR_DIAG_BIDI_CTRL}
+};
+
+static struct cdns_reg_pairs dp_100_no_ssc_rx_ln_regs[] = {
+	{0x0000, RX_PSC_A0},
+	{0x0000, RX_PSC_A2},
+	{0x0000, RX_PSC_A3},
+	{0x0000, RX_PSC_CAL},
+	{0x0000, RX_REE_GCSM1_CTRL},
+	{0x0000, RX_REE_GCSM2_CTRL},
+	{0x0000, RX_REE_PERGCSM_CTRL}
+};
+
+static struct cdns_torrent_vals dp_100_no_ssc_cmn_vals = {
+	.reg_pairs = dp_100_no_ssc_cmn_regs,
+	.num_regs = ARRAY_SIZE(dp_100_no_ssc_cmn_regs),
+};
+
+static struct cdns_torrent_vals dp_100_no_ssc_tx_ln_vals = {
+	.reg_pairs = dp_100_no_ssc_tx_ln_regs,
+	.num_regs = ARRAY_SIZE(dp_100_no_ssc_tx_ln_regs),
+};
+
+static struct cdns_torrent_vals dp_100_no_ssc_rx_ln_vals = {
+	.reg_pairs = dp_100_no_ssc_rx_ln_regs,
+	.num_regs = ARRAY_SIZE(dp_100_no_ssc_rx_ln_regs),
+};
+
 /* Single DisplayPort(DP) link configuration */
 static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {
 	{0x0000, PHY_PLL_CFG},
@@ -3514,6 +3585,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 			[TYPE_NONE] = {
 				[NO_SSC] = &sl_dp_link_cmn_vals,
 			},
+			[TYPE_PCIE] = {
+				[NO_SSC] = &pcie_dp_link_cmn_vals,
+			},
 		},
 		[TYPE_PCIE] = {
 			[TYPE_NONE] = {
@@ -3536,6 +3610,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 				[EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
 				[INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
 			},
+			[TYPE_DP] = {
+				[NO_SSC] = &pcie_dp_link_cmn_vals,
+			},
 		},
 		[TYPE_SGMII] = {
 			[TYPE_NONE] = {
@@ -3595,6 +3672,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 			[TYPE_NONE] = {
 				[NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
 			},
+			[TYPE_PCIE] = {
+				[NO_SSC] = &dp_pcie_xcvr_diag_ln_vals,
+			},
 		},
 		[TYPE_PCIE] = {
 			[TYPE_NONE] = {
@@ -3617,6 +3697,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 				[EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
 				[INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
 			},
+			[TYPE_DP] = {
+				[NO_SSC] = &pcie_dp_xcvr_diag_ln_vals,
+			},
 		},
 		[TYPE_SGMII] = {
 			[TYPE_NONE] = {
@@ -3715,6 +3798,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 				[TYPE_NONE] = {
 					[NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
 				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &dp_100_no_ssc_cmn_vals,
+				},
 			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
@@ -3737,6 +3823,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
 					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
 				},
+				[TYPE_DP] = {
+					[NO_SSC] = NULL,
+				},
 			},
 			[TYPE_SGMII] = {
 				[TYPE_NONE] = {
@@ -3812,6 +3901,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 				[TYPE_NONE] = {
 					[NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
 				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &dp_100_no_ssc_tx_ln_vals,
+				},
 			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
@@ -3834,6 +3926,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 					[EXTERNAL_SSC] = NULL,
 					[INTERNAL_SSC] = NULL,
 				},
+				[TYPE_DP] = {
+					[NO_SSC] = NULL,
+				},
 			},
 			[TYPE_SGMII] = {
 				[TYPE_NONE] = {
@@ -3909,6 +4004,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 				[TYPE_NONE] = {
 					[NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
 				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &dp_100_no_ssc_rx_ln_vals,
+				},
 			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
@@ -3931,6 +4029,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
 					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
 					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
 				},
+				[TYPE_DP] = {
+					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				},
 			},
 			[TYPE_SGMII] = {
 				[TYPE_NONE] = {
@@ -3996,6 +4097,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 			[TYPE_NONE] = {
 				[NO_SSC] = &sl_dp_link_cmn_vals,
 			},
+			[TYPE_PCIE] = {
+				[NO_SSC] = &pcie_dp_link_cmn_vals,
+			},
 		},
 		[TYPE_PCIE] = {
 			[TYPE_NONE] = {
@@ -4018,6 +4122,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 				[EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
 				[INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
 			},
+			[TYPE_DP] = {
+				[NO_SSC] = &pcie_dp_link_cmn_vals,
+			},
 		},
 		[TYPE_SGMII] = {
 			[TYPE_NONE] = {
@@ -4077,6 +4184,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 			[TYPE_NONE] = {
 				[NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
 			},
+			[TYPE_PCIE] = {
+				[NO_SSC] = &dp_pcie_xcvr_diag_ln_vals,
+			},
 		},
 		[TYPE_PCIE] = {
 			[TYPE_NONE] = {
@@ -4099,6 +4209,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 				[EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
 				[INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
 			},
+			[TYPE_DP] = {
+				[NO_SSC] = &pcie_dp_xcvr_diag_ln_vals,
+			},
 		},
 		[TYPE_SGMII] = {
 			[TYPE_NONE] = {
@@ -4197,6 +4310,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 				[TYPE_NONE] = {
 					[NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
 				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &dp_100_no_ssc_cmn_vals,
+				},
 			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
@@ -4219,6 +4335,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
 					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
 				},
+				[TYPE_DP] = {
+					[NO_SSC] = NULL,
+				},
 			},
 			[TYPE_SGMII] = {
 				[TYPE_NONE] = {
@@ -4294,6 +4413,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 				[TYPE_NONE] = {
 					[NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
 				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &dp_100_no_ssc_tx_ln_vals,
+				},
 			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
@@ -4316,6 +4438,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 					[EXTERNAL_SSC] = NULL,
 					[INTERNAL_SSC] = NULL,
 				},
+				[TYPE_DP] = {
+					[NO_SSC] = NULL,
+				},
 			},
 			[TYPE_SGMII] = {
 				[TYPE_NONE] = {
@@ -4391,6 +4516,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 				[TYPE_NONE] = {
 					[NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
 				},
+				[TYPE_PCIE] = {
+					[NO_SSC] = &dp_100_no_ssc_rx_ln_vals,
+				},
 			},
 			[TYPE_PCIE] = {
 				[TYPE_NONE] = {
@@ -4413,6 +4541,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
 					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
 					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
 				},
+				[TYPE_DP] = {
+					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
+				},
 			},
 			[TYPE_SGMII] = {
 				[TYPE_NONE] = {
-- 
2.26.1

Re: [PATCH 12/14] phy: cadence-torrent: Add PCIe + DP multilink configuration

[Kishon Vijay Abraham I]

Hi Swapnil,

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Add PCIe + DP no SSC multilink configuration sequences.

Looks neat! Exactly how it was all intended to look like. Thanks!

I would defer merging this till it gets tested in a platform though.

Thanks
Kishon

> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 131 ++++++++++++++++++++++
>  1 file changed, 131 insertions(+)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index becbf8456b2d..bf37569c6c51 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -2572,6 +2572,77 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +/* PCIe and DP link configuration */
> +static struct cdns_reg_pairs pcie_dp_link_cmn_regs[] = {
> +	{0x0003, PHY_PLL_CFG},
> +	{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
> +	{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}
> +};
> +
> +static struct cdns_reg_pairs pcie_dp_xcvr_diag_ln_regs[] = {
> +	{0x0000, XCVR_DIAG_HSCLK_SEL},
> +	{0x0001, XCVR_DIAG_HSCLK_DIV},
> +	{0x0012, XCVR_DIAG_PLLDRC_CTRL}
> +};
> +
> +static struct cdns_reg_pairs dp_pcie_xcvr_diag_ln_regs[] = {
> +	{0x0001, XCVR_DIAG_HSCLK_SEL},
> +	{0x0009, XCVR_DIAG_PLLDRC_CTRL}
> +};
> +
> +static struct cdns_torrent_vals pcie_dp_link_cmn_vals = {
> +	.reg_pairs = pcie_dp_link_cmn_regs,
> +	.num_regs = ARRAY_SIZE(pcie_dp_link_cmn_regs),
> +};
> +
> +static struct cdns_torrent_vals pcie_dp_xcvr_diag_ln_vals = {
> +	.reg_pairs = pcie_dp_xcvr_diag_ln_regs,
> +	.num_regs = ARRAY_SIZE(pcie_dp_xcvr_diag_ln_regs),
> +};
> +
> +static struct cdns_torrent_vals dp_pcie_xcvr_diag_ln_vals = {
> +	.reg_pairs = dp_pcie_xcvr_diag_ln_regs,
> +	.num_regs = ARRAY_SIZE(dp_pcie_xcvr_diag_ln_regs),
> +};
> +
> +/* DP Multilink, 100 MHz Ref clk, no SSC */
> +static struct cdns_reg_pairs dp_100_no_ssc_cmn_regs[] = {
> +	{0x007F, CMN_TXPUCAL_TUNE},
> +	{0x007F, CMN_TXPDCAL_TUNE}
> +};
> +
> +static struct cdns_reg_pairs dp_100_no_ssc_tx_ln_regs[] = {
> +	{0x00FB, TX_PSC_A0},
> +	{0x04AA, TX_PSC_A2},
> +	{0x04AA, TX_PSC_A3},
> +	{0x000F, XCVR_DIAG_BIDI_CTRL}
> +};
> +
> +static struct cdns_reg_pairs dp_100_no_ssc_rx_ln_regs[] = {
> +	{0x0000, RX_PSC_A0},
> +	{0x0000, RX_PSC_A2},
> +	{0x0000, RX_PSC_A3},
> +	{0x0000, RX_PSC_CAL},
> +	{0x0000, RX_REE_GCSM1_CTRL},
> +	{0x0000, RX_REE_GCSM2_CTRL},
> +	{0x0000, RX_REE_PERGCSM_CTRL}
> +};
> +
> +static struct cdns_torrent_vals dp_100_no_ssc_cmn_vals = {
> +	.reg_pairs = dp_100_no_ssc_cmn_regs,
> +	.num_regs = ARRAY_SIZE(dp_100_no_ssc_cmn_regs),
> +};
> +
> +static struct cdns_torrent_vals dp_100_no_ssc_tx_ln_vals = {
> +	.reg_pairs = dp_100_no_ssc_tx_ln_regs,
> +	.num_regs = ARRAY_SIZE(dp_100_no_ssc_tx_ln_regs),
> +};
> +
> +static struct cdns_torrent_vals dp_100_no_ssc_rx_ln_vals = {
> +	.reg_pairs = dp_100_no_ssc_rx_ln_regs,
> +	.num_regs = ARRAY_SIZE(dp_100_no_ssc_rx_ln_regs),
> +};
> +
>  /* Single DisplayPort(DP) link configuration */
>  static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {
>  	{0x0000, PHY_PLL_CFG},
> @@ -3514,6 +3585,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  			[TYPE_NONE] = {
>  				[NO_SSC] = &sl_dp_link_cmn_vals,
>  			},
> +			[TYPE_PCIE] = {
> +				[NO_SSC] = &pcie_dp_link_cmn_vals,
> +			},
>  		},
>  		[TYPE_PCIE] = {
>  			[TYPE_NONE] = {
> @@ -3536,6 +3610,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  				[EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
>  				[INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
>  			},
> +			[TYPE_DP] = {
> +				[NO_SSC] = &pcie_dp_link_cmn_vals,
> +			},
>  		},
>  		[TYPE_SGMII] = {
>  			[TYPE_NONE] = {
> @@ -3595,6 +3672,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  			[TYPE_NONE] = {
>  				[NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
>  			},
> +			[TYPE_PCIE] = {
> +				[NO_SSC] = &dp_pcie_xcvr_diag_ln_vals,
> +			},
>  		},
>  		[TYPE_PCIE] = {
>  			[TYPE_NONE] = {
> @@ -3617,6 +3697,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  				[EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
>  				[INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
>  			},
> +			[TYPE_DP] = {
> +				[NO_SSC] = &pcie_dp_xcvr_diag_ln_vals,
> +			},
>  		},
>  		[TYPE_SGMII] = {
>  			[TYPE_NONE] = {
> @@ -3715,6 +3798,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
>  				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &dp_100_no_ssc_cmn_vals,
> +				},
>  			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> @@ -3737,6 +3823,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
>  					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
>  				},
> +				[TYPE_DP] = {
> +					[NO_SSC] = NULL,
> +				},
>  			},
>  			[TYPE_SGMII] = {
>  				[TYPE_NONE] = {
> @@ -3812,6 +3901,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
>  				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &dp_100_no_ssc_tx_ln_vals,
> +				},
>  			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> @@ -3834,6 +3926,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  					[EXTERNAL_SSC] = NULL,
>  					[INTERNAL_SSC] = NULL,
>  				},
> +				[TYPE_DP] = {
> +					[NO_SSC] = NULL,
> +				},
>  			},
>  			[TYPE_SGMII] = {
>  				[TYPE_NONE] = {
> @@ -3909,6 +4004,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
>  				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &dp_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> @@ -3931,6 +4029,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
>  					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
>  					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
>  				},
> +				[TYPE_DP] = {
> +					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  			[TYPE_SGMII] = {
>  				[TYPE_NONE] = {
> @@ -3996,6 +4097,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  			[TYPE_NONE] = {
>  				[NO_SSC] = &sl_dp_link_cmn_vals,
>  			},
> +			[TYPE_PCIE] = {
> +				[NO_SSC] = &pcie_dp_link_cmn_vals,
> +			},
>  		},
>  		[TYPE_PCIE] = {
>  			[TYPE_NONE] = {
> @@ -4018,6 +4122,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  				[EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
>  				[INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
>  			},
> +			[TYPE_DP] = {
> +				[NO_SSC] = &pcie_dp_link_cmn_vals,
> +			},
>  		},
>  		[TYPE_SGMII] = {
>  			[TYPE_NONE] = {
> @@ -4077,6 +4184,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  			[TYPE_NONE] = {
>  				[NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
>  			},
> +			[TYPE_PCIE] = {
> +				[NO_SSC] = &dp_pcie_xcvr_diag_ln_vals,
> +			},
>  		},
>  		[TYPE_PCIE] = {
>  			[TYPE_NONE] = {
> @@ -4099,6 +4209,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  				[EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
>  				[INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
>  			},
> +			[TYPE_DP] = {
> +				[NO_SSC] = &pcie_dp_xcvr_diag_ln_vals,
> +			},
>  		},
>  		[TYPE_SGMII] = {
>  			[TYPE_NONE] = {
> @@ -4197,6 +4310,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
>  				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &dp_100_no_ssc_cmn_vals,
> +				},
>  			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> @@ -4219,6 +4335,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  					[EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
>  					[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
>  				},
> +				[TYPE_DP] = {
> +					[NO_SSC] = NULL,
> +				},
>  			},
>  			[TYPE_SGMII] = {
>  				[TYPE_NONE] = {
> @@ -4294,6 +4413,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
>  				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &dp_100_no_ssc_tx_ln_vals,
> +				},
>  			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> @@ -4316,6 +4438,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  					[EXTERNAL_SSC] = NULL,
>  					[INTERNAL_SSC] = NULL,
>  				},
> +				[TYPE_DP] = {
> +					[NO_SSC] = NULL,
> +				},
>  			},
>  			[TYPE_SGMII] = {
>  				[TYPE_NONE] = {
> @@ -4391,6 +4516,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  				[TYPE_NONE] = {
>  					[NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
>  				},
> +				[TYPE_PCIE] = {
> +					[NO_SSC] = &dp_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  			[TYPE_PCIE] = {
>  				[TYPE_NONE] = {
> @@ -4413,6 +4541,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
>  					[EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
>  					[INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
>  				},
> +				[TYPE_DP] = {
> +					[NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
> +				},
>  			},
>  			[TYPE_SGMII] = {
>  				[TYPE_NONE] = {
> 

[PATCH 13/14] phy: cadence-torrent: Add debug information for PHY configuration

[Swapnil Jakhade]

Display information in probe regarding PHY configuration parameters like
single link or multilink protocol information along with number of lanes
used for each protocol link.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 32 +++++++++++++++++++++--
 1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index bf37569c6c51..39145e56e061 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -574,6 +574,24 @@ static const struct coefficients vltg_coeff[4][4] = {
 	}
 };
 
+static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type)
+{
+	switch (phy_type) {
+	case TYPE_DP:
+		return "DisplayPort";
+	case TYPE_PCIE:
+		return "PCIe";
+	case TYPE_SGMII:
+		return "SGMII";
+	case TYPE_QSGMII:
+		return "QSGMII";
+	case TYPE_USB:
+		return "USB";
+	default:
+		return "None";
+	}
+}
+
 /*
  * Set registers responsible for enabling and configuring SSC, with second and
  * third register values provided by parameters.
@@ -2504,8 +2522,7 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
 				init_dp_regmap++;
 			}
 
-			dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n",
-				 cdns_phy->phys[node].num_lanes,
+			dev_info(dev, "DP max bit rate %d.%03d Gbps\n",
 				 cdns_phy->max_bit_rate / 1000,
 				 cdns_phy->max_bit_rate % 1000);
 
@@ -2539,6 +2556,17 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
 		goto put_lnk_rst;
 	}
 
+	if (cdns_phy->nsubnodes > 1)
+		dev_info(dev, "%s (%d lanes) & %s (%d lanes)",
+			 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
+			 cdns_phy->phys[0].num_lanes,
+			 cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),
+			 cdns_phy->phys[1].num_lanes);
+	else
+		dev_info(dev, "%s (%d lanes)",
+			 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
+			 cdns_phy->phys[0].num_lanes);
+
 	return 0;
 
 put_child:
-- 
2.26.1

Re: [PATCH 13/14] phy: cadence-torrent: Add debug information for PHY configuration

[Kishon Vijay Abraham I]

Hi Swapnil,

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Display information in probe regarding PHY configuration parameters like
> single link or multilink protocol information along with number of lanes
> used for each protocol link.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 32 +++++++++++++++++++++--
>  1 file changed, 30 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index bf37569c6c51..39145e56e061 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -574,6 +574,24 @@ static const struct coefficients vltg_coeff[4][4] = {
>  	}
>  };
>  
> +static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type)
> +{
> +	switch (phy_type) {
> +	case TYPE_DP:
> +		return "DisplayPort";
> +	case TYPE_PCIE:
> +		return "PCIe";
> +	case TYPE_SGMII:
> +		return "SGMII";
> +	case TYPE_QSGMII:
> +		return "QSGMII";
> +	case TYPE_USB:
> +		return "USB";
> +	default:
> +		return "None";
> +	}
> +}
> +
>  /*
>   * Set registers responsible for enabling and configuring SSC, with second and
>   * third register values provided by parameters.
> @@ -2504,8 +2522,7 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
>  				init_dp_regmap++;
>  			}
>  
> -			dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n",
> -				 cdns_phy->phys[node].num_lanes,
> +			dev_info(dev, "DP max bit rate %d.%03d Gbps\n",
>  				 cdns_phy->max_bit_rate / 1000,
>  				 cdns_phy->max_bit_rate % 1000);
>  
> @@ -2539,6 +2556,17 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
>  		goto put_lnk_rst;
>  	}
>  
> +	if (cdns_phy->nsubnodes > 1)
> +		dev_info(dev, "%s (%d lanes) & %s (%d lanes)",
> +			 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
> +			 cdns_phy->phys[0].num_lanes,
> +			 cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),
> +			 cdns_phy->phys[1].num_lanes);
> +	else
> +		dev_info(dev, "%s (%d lanes)",
> +			 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
> +			 cdns_phy->phys[0].num_lanes);

Make all of this dev_dbg() or dev_vdbg() and avoid noisy boot log.

Thanks
Kishon

[PATCH 14/14] phy: cadence-torrent: Check PIPE mode PHY status to be ready for operation

[Swapnil Jakhade]

PIPE PHY status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 60 +++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 39145e56e061..42a1bdfd18d5 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -51,6 +51,10 @@
 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset)	\
 				(0xC000 << (block_offset))
 
+#define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\
+				((0xD000 << (block_offset)) +		\
+				(((ln) << 9) << (reg_offset)))
+
 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset)	\
 				(0xE000 << (block_offset))
 
@@ -218,6 +222,9 @@
 #define PHY_PIPE_USB3_GEN2_POST_CFG0	0x0022U
 #define PHY_PIPE_USB3_GEN2_POST_CFG1	0x0023U
 
+/* PHY PCS lane registers */
+#define PHY_PCS_ISO_LINK_CTRL		0x000BU
+
 /* PHY PMA common registers */
 #define PHY_PMA_CMN_CTRL1		0x0000U
 #define PHY_PMA_CMN_CTRL2		0x0001U
@@ -242,6 +249,9 @@ static const struct reg_field phy_pma_pll_raw_ctrl =
 static const struct reg_field phy_reset_ctrl =
 				REG_FIELD(PHY_RESET, 8, 8);
 
+static const struct reg_field phy_pcs_iso_link_ctrl_1 =
+				REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1);
+
 static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0);
 
 #define REFCLK_OUT_NUM_CMN_CONFIG	5
@@ -316,12 +326,14 @@ struct cdns_torrent_phy {
 	struct regmap *regmap_phy_pma_common_cdb;
 	struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
 	struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
+	struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES];
 	struct regmap *regmap_dptx_phy_reg;
 	struct regmap_field *phy_pll_cfg;
 	struct regmap_field *phy_pma_cmn_ctrl_1;
 	struct regmap_field *phy_pma_cmn_ctrl_2;
 	struct regmap_field *phy_pma_pll_raw_ctrl;
 	struct regmap_field *phy_reset_ctrl;
+	struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES];
 	struct clk *clks[CDNS_TORRENT_REFCLK_DRIVER + 1];
 	struct clk_onecell_data clk_data;
 };
@@ -456,6 +468,22 @@ static const struct regmap_config cdns_torrent_common_cdb_config = {
 	.reg_read = cdns_regmap_read,
 };
 
+#define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
+{ \
+	.name = "torrent_phy_pcs_lane" n "_cdb", \
+	.reg_stride = 1, \
+	.fast_io = true, \
+	.reg_write = cdns_regmap_write, \
+	.reg_read = cdns_regmap_read, \
+}
+
+static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = {
+	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
+	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
+	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
+	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
+};
+
 static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
 	.name = "torrent_phy_pcs_cmn_cdb",
 	.reg_stride = 1,
@@ -1546,6 +1574,16 @@ static int cdns_torrent_phy_on(struct phy *phy)
 		return ret;
 	}
 
+	if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) {
+		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane],
+						     read_val, !read_val, 1000,
+						     PLL_LOCK_TIMEOUT);
+		if (ret == -ETIMEDOUT) {
+			dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n");
+			return ret;
+		}
+	}
+
 	mdelay(10);
 
 	return 0;
@@ -1822,6 +1860,7 @@ static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
 	struct device *dev = cdns_phy->dev;
 	struct regmap_field *field;
 	struct regmap *regmap;
+	int i;
 
 	regmap = cdns_phy->regmap_phy_pcs_common_cdb;
 	field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
@@ -1855,6 +1894,16 @@ static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
 	}
 	cdns_phy->phy_pma_pll_raw_ctrl = field;
 
+	for (i = 0; i < MAX_NUM_LANES; i++) {
+		regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i];
+		field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1);
+		if (IS_ERR(field)) {
+			dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i);
+			return PTR_ERR(field);
+		}
+		cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field;
+	}
+
 	return 0;
 }
 
@@ -1915,6 +1964,17 @@ static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
 			return PTR_ERR(regmap);
 		}
 		cdns_phy->regmap_rx_lane_cdb[i] = regmap;
+
+		block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,
+							       reg_offset_shift);
+		regmap = cdns_regmap_init(dev, sd_base, block_offset,
+					  reg_offset_shift,
+					  &cdns_torrent_phy_pcs_lane_cdb_config[i]);
+		if (IS_ERR(regmap)) {
+			dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
+			return PTR_ERR(regmap);
+		}
+		cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap;
 	}
 
 	block_offset = TORRENT_COMMON_CDB_OFFSET;
-- 
2.26.1

Re: [PATCH 14/14] phy: cadence-torrent: Check PIPE mode PHY status to be ready for operation

[Kishon Vijay Abraham I]

Hi Swapnil,

On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> PIPE PHY status is used to communicate the completion of several PHY
> functions. Check if PHY is ready for operation while configured for
> PIPE mode during startup.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 60 +++++++++++++++++++++++
>  1 file changed, 60 insertions(+)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index 39145e56e061..42a1bdfd18d5 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -51,6 +51,10 @@
>  #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset)	\
>  				(0xC000 << (block_offset))
>  
> +#define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\
> +				((0xD000 << (block_offset)) +		\
> +				(((ln) << 9) << (reg_offset)))
> +
>  #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset)	\
>  				(0xE000 << (block_offset))
>  
> @@ -218,6 +222,9 @@
>  #define PHY_PIPE_USB3_GEN2_POST_CFG0	0x0022U
>  #define PHY_PIPE_USB3_GEN2_POST_CFG1	0x0023U
>  
> +/* PHY PCS lane registers */
> +#define PHY_PCS_ISO_LINK_CTRL		0x000BU
> +
>  /* PHY PMA common registers */
>  #define PHY_PMA_CMN_CTRL1		0x0000U
>  #define PHY_PMA_CMN_CTRL2		0x0001U
> @@ -242,6 +249,9 @@ static const struct reg_field phy_pma_pll_raw_ctrl =
>  static const struct reg_field phy_reset_ctrl =
>  				REG_FIELD(PHY_RESET, 8, 8);
>  
> +static const struct reg_field phy_pcs_iso_link_ctrl_1 =
> +				REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1);
> +
>  static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0);
>  
>  #define REFCLK_OUT_NUM_CMN_CONFIG	5
> @@ -316,12 +326,14 @@ struct cdns_torrent_phy {
>  	struct regmap *regmap_phy_pma_common_cdb;
>  	struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
>  	struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
> +	struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES];
>  	struct regmap *regmap_dptx_phy_reg;
>  	struct regmap_field *phy_pll_cfg;
>  	struct regmap_field *phy_pma_cmn_ctrl_1;
>  	struct regmap_field *phy_pma_cmn_ctrl_2;
>  	struct regmap_field *phy_pma_pll_raw_ctrl;
>  	struct regmap_field *phy_reset_ctrl;
> +	struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES];
>  	struct clk *clks[CDNS_TORRENT_REFCLK_DRIVER + 1];
>  	struct clk_onecell_data clk_data;
>  };
> @@ -456,6 +468,22 @@ static const struct regmap_config cdns_torrent_common_cdb_config = {
>  	.reg_read = cdns_regmap_read,
>  };
>  
> +#define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
> +{ \
> +	.name = "torrent_phy_pcs_lane" n "_cdb", \
> +	.reg_stride = 1, \
> +	.fast_io = true, \
> +	.reg_write = cdns_regmap_write, \
> +	.reg_read = cdns_regmap_read, \
> +}
> +
> +static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = {
> +	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
> +	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
> +	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
> +	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
> +};
> +
>  static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
>  	.name = "torrent_phy_pcs_cmn_cdb",
>  	.reg_stride = 1,
> @@ -1546,6 +1574,16 @@ static int cdns_torrent_phy_on(struct phy *phy)
>  		return ret;
>  	}
>  
> +	if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) {
> +		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane],
> +						     read_val, !read_val, 1000,
> +						     PLL_LOCK_TIMEOUT);
> +		if (ret == -ETIMEDOUT) {
> +			dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n");
> +			return ret;
> +		}
> +	}
> +
>  	mdelay(10);

With the above polling, this mdelay() shouldn't be required.

Thanks
Kishon