[PATCH v2 0/8] Add support for Renesas RZ/Five SoC

[PATCH v2 0/8] Add support for Renesas RZ/Five SoC

[Lad Prabhakar]

Hi All,

The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
entry-class social infrastructure gateway control and industrial gateway
control.

This patch series adds initial SoC DTSi support for Renesas RZ/Five
(R9A07G043) SoC and updates the bindings for the same. Below is the list
of IP blocks added in the initial SoC DTSI which can be used to boot via
initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC

Useful links:
-------------
[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
[1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/

Patch series depends on:
-----------------------
[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220722141506.20171-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726174929.950-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726175315.1147-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220815111708.22302-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

Below are the logs from RZ/Five SMARC EVK:
------------------------------------------
/ # uname -ra
Linux (none) 5.19.0-next-20220815-00072-ge2dccecbe54f #256 SMP Mon Aug 15 15:12:03 BST 2022 riscv64 GNU/Linux
/ #
/ # cat /proc/cpuinfo
processor       : 0
hart            : 0
isa             : rv64imafdc
mmu             : sv39
uarch           : andestech,ax45mp
mvendorid       : 0x31e
marchid         : 0x8000000000008a45
mimpid          : 0x500

/ # cat /proc/interrupts
           CPU0
  1:          0  SiFive PLIC 412 Level     1004b800.serial:rx err
  2:          1  SiFive PLIC 414 Level     1004b800.serial:rx full
  3:        181  SiFive PLIC 415 Level     1004b800.serial:tx empty
  4:          0  SiFive PLIC 413 Level     1004b800.serial:break
  5:       2435  RISC-V INTC   5 Edge      riscv-timer
  6:         38  SiFive PLIC 416 Level     1004b800.serial:rx ready
IPI0:         0  Rescheduling interrupts
IPI1:         0  Function call interrupts
IPI2:         0  CPU stop interrupts
IPI3:         0  IRQ work interrupts
IPI4:         0  Timer broadcast interrupts
/ # cat /proc/meminfo
MemTotal:         882356 kB
MemFree:          861996 kB
MemAvailable:     859744 kB
Buffers:               0 kB
Cached:             1796 kB
SwapCached:            0 kB
Active:                0 kB
Inactive:             80 kB
Active(anon):          0 kB
Inactive(anon):       80 kB
Active(file):          0 kB
Inactive(file):        0 kB
Unevictable:        1796 kB
Mlocked:               0 kB
SwapTotal:             0 kB
SwapFree:              0 kB
Dirty:                 0 kB
Writeback:             0 kB
AnonPages:           116 kB
Mapped:             1136 kB
Shmem:                 0 kB
KReclaimable:       6732 kB
Slab:              11904 kB
SReclaimable:       6732 kB
SUnreclaim:         5172 kB
KernelStack:         556 kB
PageTables:           32 kB
NFS_Unstable:          0 kB
Bounce:                0 kB
WritebackTmp:          0 kB
CommitLimit:      441176 kB
Committed_AS:        592 kB
VmallocTotal:   67108864 kB
VmallocUsed:         716 kB
VmallocChunk:          0 kB
Percpu:               84 kB
HugePages_Total:       0
HugePages_Free:        0
HugePages_Rsvd:        0
HugePages_Surp:        0
Hugepagesize:       2048 kB
Hugetlb:               0 kB
/ #
/ # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
soc0/$i; done
machine: Renesas SMARC EVK based on r9a07g043f01
family: RZ/Five
soc_id: r9a07g043
revision: 0
/ #

Lad Prabhakar (8):
  dt-bindings: riscv: Sort the CPU core list alphabetically
  dt-bindings: riscv: Add Andes AX45MP core to the list
  dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC
  RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
  riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
  riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
  MAINTAINERS: Add entry for Renesas RISC-V architecture
  RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC

 .../devicetree/bindings/arm/renesas.yaml      |   3 +-
 .../devicetree/bindings/riscv/cpus.yaml       |  11 +-
 MAINTAINERS                                   |  10 ++
 arch/riscv/Kconfig.socs                       |  14 ++
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/renesas/Makefile          |   2 +
 arch/riscv/boot/dts/renesas/r9a07g043.dtsi    | 121 ++++++++++++++++++
 .../boot/dts/renesas/r9a07g043f01-smarc.dts   |  16 +++
 .../boot/dts/renesas/rzfive-smarc-som.dtsi    |  22 ++++
 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi |  32 +++++
 arch/riscv/configs/defconfig                  |   2 +
 11 files changed, 228 insertions(+), 6 deletions(-)
 create mode 100644 arch/riscv/boot/dts/renesas/Makefile
 create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
 create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
 create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
 create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi

-- 
2.25.1

[PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically

[Lad Prabhakar]

Sort the CPU cores list alphabetically for maintenance.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v1->v2
* Included RB tag from Krzysztof
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 873dd12f6e89..2a1c5ae5b0aa 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,17 +27,17 @@ properties:
     oneOf:
       - items:
           - enum:
-              - sifive,rocket0
+              - canaan,k210
               - sifive,bullet0
               - sifive,e5
               - sifive,e7
               - sifive,e71
-              - sifive,u74-mc
-              - sifive,u54
-              - sifive,u74
+              - sifive,rocket0
               - sifive,u5
+              - sifive,u54
               - sifive,u7
-              - canaan,k210
+              - sifive,u74
+              - sifive,u74-mc
           - const: riscv
       - items:
           - enum:
-- 
2.25.1

Re: [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically

[Conor.Dooley]

On 15/08/2022 16:14, Lad Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Sort the CPU cores list alphabetically for maintenance.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Speaking of OCD, I like this sort of cleanup 😍
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> ---
> v1->v2
> * Included RB tag from Krzysztof
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 873dd12f6e89..2a1c5ae5b0aa 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -27,17 +27,17 @@ properties:
>      oneOf:
>        - items:
>            - enum:
> -              - sifive,rocket0
> +              - canaan,k210
>                - sifive,bullet0
>                - sifive,e5
>                - sifive,e7
>                - sifive,e71
> -              - sifive,u74-mc
> -              - sifive,u54
> -              - sifive,u74
> +              - sifive,rocket0
>                - sifive,u5
> +              - sifive,u54
>                - sifive,u7
> -              - canaan,k210
> +              - sifive,u74
> +              - sifive,u74-mc
>            - const: riscv
>        - items:
>            - enum:
> --
> 2.25.1
> 

Re: [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically

[Geert Uytterhoeven]

On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Sort the CPU cores list alphabetically for maintenance.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>



Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically

[Geert Uytterhoeven]

On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Sort the CPU cores list alphabetically for maintenance.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list

[Lad Prabhakar]

The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. In preparation to add support for RZ/Five SoC add
the Andes AX45MP core to the list.

More details about Andes AX45MP core can be found here:
[0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v1->v2
* Included ack from Krzysztof
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 2a1c5ae5b0aa..1681767790c5 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,6 +27,7 @@ properties:
     oneOf:
       - items:
           - enum:
+              - andestech,ax45mp
               - canaan,k210
               - sifive,bullet0
               - sifive,e5
-- 
2.25.1

Re: [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list

[Geert Uytterhoeven]

On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> Single) from Andes. In preparation to add support for RZ/Five SoC add
> the Andes AX45MP core to the list.
>
> More details about Andes AX45MP core can be found here:
> [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC

[Lad Prabhakar]

Document Renesas RZ/Five (R9A07G043) SoC.

More info about RZ/Five SoC:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
* New patch
---
 Documentation/devicetree/bindings/arm/renesas.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index ff80152f092f..233847eb23fd 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -415,11 +415,12 @@ properties:
               - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
           - const: renesas,r9a06g032
 
-      - description: RZ/G2UL (R9A07G043)
+      - description: RZ/Five and RZ/G2UL (R9A07G043)
         items:
           - enum:
               - renesas,smarc-evk # SMARC EVK
           - enum:
+              - renesas,r9a07g043f01 # RZ/Five (RISC-V core)
               - renesas,r9a07g043u11 # RZ/G2UL Type-1
               - renesas,r9a07g043u12 # RZ/G2UL Type-2
           - const: renesas,r9a07g043
-- 
2.25.1

Re: [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC

[Conor.Dooley]

On 15/08/2022 16:14, Lad Prabhakar wrote:
> dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC 

Hey Lad,

Maybe I am missing something on the arm side, but "soc"?
Was the intent to move this to Documentation/devicetree/bindings/soc
but you moved it back to arm by accident?

Thanks,
Conor.


> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Document Renesas RZ/Five (R9A07G043) SoC.
> 
> More info about RZ/Five SoC:
> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> * New patch
> ---
>  Documentation/devicetree/bindings/arm/renesas.yaml | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> index ff80152f092f..233847eb23fd 100644
> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -415,11 +415,12 @@ properties:
>                - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
>            - const: renesas,r9a06g032
> 
> -      - description: RZ/G2UL (R9A07G043)
> +      - description: RZ/Five and RZ/G2UL (R9A07G043)
>          items:
>            - enum:
>                - renesas,smarc-evk # SMARC EVK
>            - enum:
> +              - renesas,r9a07g043f01 # RZ/Five (RISC-V core)
>                - renesas,r9a07g043u11 # RZ/G2UL Type-1
>                - renesas,r9a07g043u12 # RZ/G2UL Type-2
>            - const: renesas,r9a07g043
> --
> 2.25.1
> 

Re: [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Conor,

Thank you for the review.

On Mon, Aug 15, 2022 at 8:14 PM <Conor.Dooley@microchip.com> wrote:
>
> On 15/08/2022 16:14, Lad Prabhakar wrote:
> > dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC
>
> Hey Lad,
>
> Maybe I am missing something on the arm side, but "soc"?
> Was the intent to move this to Documentation/devicetree/bindings/soc
> but you moved it back to arm by accident?
>
Ouch I sent out the older version of my patch for this. I did actually
send out a patch which moves arm renesas.yaml to the soc folder.

Cheers,
Prabhakar

> Thanks,
> Conor.
>
>
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Document Renesas RZ/Five (R9A07G043) SoC.
> >
> > More info about RZ/Five SoC:
> > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * New patch
> > ---
> >  Documentation/devicetree/bindings/arm/renesas.yaml | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > index ff80152f092f..233847eb23fd 100644
> > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > @@ -415,11 +415,12 @@ properties:
> >                - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
> >            - const: renesas,r9a06g032
> >
> > -      - description: RZ/G2UL (R9A07G043)
> > +      - description: RZ/Five and RZ/G2UL (R9A07G043)
> >          items:
> >            - enum:
> >                - renesas,smarc-evk # SMARC EVK
> >            - enum:
> > +              - renesas,r9a07g043f01 # RZ/Five (RISC-V core)
> >                - renesas,r9a07g043u11 # RZ/G2UL Type-1
> >                - renesas,r9a07g043u12 # RZ/G2UL Type-2
> >            - const: renesas,r9a07g043
> > --
> > 2.25.1
> >
>

Re: [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC

[Conor.Dooley]

On 15/08/2022 20:40, Lad, Prabhakar wrote:
> Hi Conor,
> 
> Thank you for the review.
> 
> On Mon, Aug 15, 2022 at 8:14 PM <Conor.Dooley@microchip.com> wrote:
>>
>> On 15/08/2022 16:14, Lad Prabhakar wrote:
>>> dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC
>>
>> Hey Lad,
>>
>> Maybe I am missing something on the arm side, but "soc"?
>> Was the intent to move this to Documentation/devicetree/bindings/soc
>> but you moved it back to arm by accident?
>>
> Ouch I sent out the older version of my patch for this. I did actually
> send out a patch which moves arm renesas.yaml to the soc folder.

Cool thought I saw one of those this morning.

> 
> Cheers,
> Prabhakar
> 
>> Thanks,
>> Conor.
>>
>>
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Document Renesas RZ/Five (R9A07G043) SoC.
>>>
>>> More info about RZ/Five SoC:
>>> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> v1->v2
>>> * New patch
>>> ---
>>>  Documentation/devicetree/bindings/arm/renesas.yaml | 3 ++-
>>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
>>> index ff80152f092f..233847eb23fd 100644
>>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
>>> @@ -415,11 +415,12 @@ properties:
>>>                - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
>>>            - const: renesas,r9a06g032
>>>
>>> -      - description: RZ/G2UL (R9A07G043)
>>> +      - description: RZ/Five and RZ/G2UL (R9A07G043)
>>>          items:
>>>            - enum:
>>>                - renesas,smarc-evk # SMARC EVK
>>>            - enum:
>>> +              - renesas,r9a07g043f01 # RZ/Five (RISC-V core)
>>>                - renesas,r9a07g043u11 # RZ/G2UL Type-1
>>>                - renesas,r9a07g043u12 # RZ/G2UL Type-2
>>>            - const: renesas,r9a07g043
>>> --
>>> 2.25.1
>>>
>>
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC

[Krzysztof Kozlowski]

On 15/08/2022 18:14, Lad Prabhakar wrote:
> Document Renesas RZ/Five (R9A07G043) SoC.
> 
> More info about RZ/Five SoC:
> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Document Renesas RZ/Five (R9A07G043) SoC.
>
> More info about RZ/Five SoC:
> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -415,11 +415,12 @@ properties:
>                - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
>            - const: renesas,r9a06g032
>
> -      - description: RZ/G2UL (R9A07G043)
> +      - description: RZ/Five and RZ/G2UL (R9A07G043)
>          items:
>            - enum:
>                - renesas,smarc-evk # SMARC EVK
>            - enum:
> +              - renesas,r9a07g043f01 # RZ/Five (RISC-V core)

Should we be consistent, and leave out the "(RISC-V core)" comment,
or add it everywhere?

Note that several of the SoCs listed in this file have SuperH or
RealTime ARM cores, so going for the former means a lot of work.

>                - renesas,r9a07g043u11 # RZ/G2UL Type-1
>                - renesas,r9a07g043u12 # RZ/G2UL Type-2
>            - const: renesas,r9a07g043

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Thu, Aug 18, 2022 at 4:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Document Renesas RZ/Five (R9A07G043) SoC.
> >
> > More info about RZ/Five SoC:
> > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > @@ -415,11 +415,12 @@ properties:
> >                - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
> >            - const: renesas,r9a06g032
> >
> > -      - description: RZ/G2UL (R9A07G043)
> > +      - description: RZ/Five and RZ/G2UL (R9A07G043)
> >          items:
> >            - enum:
> >                - renesas,smarc-evk # SMARC EVK
> >            - enum:
> > +              - renesas,r9a07g043f01 # RZ/Five (RISC-V core)
>
> Should we be consistent, and leave out the "(RISC-V core)" comment,
> or add it everywhere?
>
Rather leave it for now ;) . If Rob agrees on your suggestion on
splitting (renesas,{rmobile,rcar-gen[1234],rza,rzg,rzn,...}.yaml that
would make it cleaner.

> Note that several of the SoCs listed in this file have SuperH or
> RealTime ARM cores, so going for the former means a lot of work.
>
Agreed.

Cheers,
Prabhakar

[PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

[Lad Prabhakar]

Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
(R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
of the Renesas drivers depend on this config option.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
* No Change
---
 arch/riscv/Kconfig.socs | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..91b7f38b77a8 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
 
 endif # SOC_CANAAN
 
+config ARCH_RENESAS
+	bool
+	select GPIOLIB
+	select PINCTRL
+	select SOC_BUS
+
+config SOC_RENESAS_RZFIVE
+	bool "Renesas RZ/Five SoC"
+	select ARCH_R9A07G043
+	select ARCH_RENESAS
+	select RESET_CONTROLLER
+	help
+	  This enables support for Renesas RZ/Five SoC.
+
 endmenu # "SoC selection"
-- 
2.25.1

Re: [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

[Conor.Dooley]

On 15/08/2022 16:14, Lad Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> of the Renesas drivers depend on this config option.

Hey Lad,

I think I said something similar on v1, but I said it again
to Samuel today so I may as well repost here too:
"I think this and patch 12/12 with the defconfig changes should be
deferred until post LPC (which still leaves plenty of time for
making the 6.1 merge window). We already have like 4 different
approaches between the existing SOC_FOO symbols & two more when
D1 stuff and the Renesas stuff is considered.

Plan is to decide at LPC on one approach for what to do with
Kconfig.socs & to me it seems like a good idea to do what's being
done here - it's likely that further arm vendors will move and
keeping the common symbols makes a lot of sense to me..."

Also, for the sake of my OCD could you pick either riscv or
RISC-V and use it for the whole series? Pedantic I guess, but
/shrug

Thanks,
Conor.

> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> * No Change
> ---
>  arch/riscv/Kconfig.socs | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..91b7f38b77a8 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
> 
>  endif # SOC_CANAAN
> 
> +config ARCH_RENESAS
> +       bool
> +       select GPIOLIB
> +       select PINCTRL
> +       select SOC_BUS
> +
> +config SOC_RENESAS_RZFIVE
> +       bool "Renesas RZ/Five SoC"
> +       select ARCH_R9A07G043
> +       select ARCH_RENESAS
> +       select RESET_CONTROLLER
> +       help
> +         This enables support for Renesas RZ/Five SoC.
> +
>  endmenu # "SoC selection"
> --
> 2.25.1
> 

Re: [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

[Lad, Prabhakar]

Hi Conor,

Thank you for the review.

On Mon, Aug 15, 2022 at 8:10 PM <Conor.Dooley@microchip.com> wrote:
>
> On 15/08/2022 16:14, Lad Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> > (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> > of the Renesas drivers depend on this config option.
>
> Hey Lad,
>
> I think I said something similar on v1, but I said it again
> to Samuel today so I may as well repost here too:
> "I think this and patch 12/12 with the defconfig changes should be
patch 8/8.


> deferred until post LPC (which still leaves plenty of time for
> making the 6.1 merge window). We already have like 4 different
> approaches between the existing SOC_FOO symbols & two more when
> D1 stuff and the Renesas stuff is considered.
>
> Plan is to decide at LPC on one approach for what to do with
> Kconfig.socs & to me it seems like a good idea to do what's being
> done here - it's likely that further arm vendors will move and
> keeping the common symbols makes a lot of sense to me..."
>
Sure not a problem. But delaying patch 4 and 8 will make RZ/Five SoC
not buildable. Is that OK?

> Also, for the sake of my OCD could you pick either riscv or
> RISC-V and use it for the whole series? Pedantic I guess, but
> /shrug
>
Sorry did you mean I add riscv/RISC-V in the subject?

Cheers,
Prabhakar


> Thanks,
> Conor.
>
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * No Change
> > ---
> >  arch/riscv/Kconfig.socs | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 69774bb362d6..91b7f38b77a8 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
> >
> >  endif # SOC_CANAAN
> >
> > +config ARCH_RENESAS
> > +       bool
> > +       select GPIOLIB
> > +       select PINCTRL
> > +       select SOC_BUS
> > +
> > +config SOC_RENESAS_RZFIVE
> > +       bool "Renesas RZ/Five SoC"
> > +       select ARCH_R9A07G043
> > +       select ARCH_RENESAS
> > +       select RESET_CONTROLLER
> > +       help
> > +         This enables support for Renesas RZ/Five SoC.
> > +
> >  endmenu # "SoC selection"
> > --
> > 2.25.1
> >
>

Re: [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

[Conor.Dooley]

On 15/08/2022 20:57, Lad, Prabhakar wrote:
> Hi Conor,
> 
> Thank you for the review.
> 
> On Mon, Aug 15, 2022 at 8:10 PM <Conor.Dooley@microchip.com> wrote:
>>
>> On 15/08/2022 16:14, Lad Prabhakar wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
>>> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
>>> of the Renesas drivers depend on this config option.
>>
>> Hey Lad,
>>
>> I think I said something similar on v1, but I said it again
>> to Samuel today so I may as well repost here too:
>> "I think this and patch 12/12 with the defconfig changes should be
> patch 8/8.

It was a direct copy paste, hence the quotes ;)
Your patch 8/8 lines up with the current symbols while Samuel's
doesn't.

> 
> 
>> deferred until post LPC (which still leaves plenty of time for
>> making the 6.1 merge window). We already have like 4 different
>> approaches between the existing SOC_FOO symbols & two more when
>> D1 stuff and the Renesas stuff is considered.
>>
>> Plan is to decide at LPC on one approach for what to do with
>> Kconfig.socs & to me it seems like a good idea to do what's being
>> done here - it's likely that further arm vendors will move and
>> keeping the common symbols makes a lot of sense to me..."
>>
> Sure not a problem. But delaying patch 4 and 8 will make RZ/Five SoC
> not buildable. Is that OK?

No no, I prob just did a bad job of explaining. I meant more
along the lines of "I don't think this is the right approach
but I will defer reviewing until after LPC, when we have picked
one approach to use for everyone". I'm sorry, poor choice of
words maybe. I didn't mean drop these patches so that it does
not build, keeping it buildable until then so that we can all
test/review is the way to go. Not your fault we've done 4 different
things so far!

Hopefully that makes a bit more sense?

> 
>> Also, for the sake of my OCD could you pick either riscv or
>> RISC-V and use it for the whole series? Pedantic I guess, but
>> /shrug
>>
> Sorry did you mean I add riscv/RISC-V in the subject?

You have some patches with RISC-V and some with riscv.
What I meant was use one of the two for the whole series.
Thanks,
Conor.

> 
> Cheers,
> Prabhakar
> 
> 
>> Thanks,
>> Conor.
>>
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> v1->v2
>>> * No Change
>>> ---
>>>  arch/riscv/Kconfig.socs | 14 ++++++++++++++
>>>  1 file changed, 14 insertions(+)
>>>
>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>>> index 69774bb362d6..91b7f38b77a8 100644
>>> --- a/arch/riscv/Kconfig.socs
>>> +++ b/arch/riscv/Kconfig.socs
>>> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
>>>
>>>  endif # SOC_CANAAN
>>>
>>> +config ARCH_RENESAS
>>> +       bool
>>> +       select GPIOLIB
>>> +       select PINCTRL
>>> +       select SOC_BUS
>>> +
>>> +config SOC_RENESAS_RZFIVE
>>> +       bool "Renesas RZ/Five SoC"
>>> +       select ARCH_R9A07G043
>>> +       select ARCH_RENESAS
>>> +       select RESET_CONTROLLER
>>> +       help
>>> +         This enables support for Renesas RZ/Five SoC.
>>> +
>>>  endmenu # "SoC selection"
>>> --
>>> 2.25.1
>>>
>>
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

[Lad, Prabhakar]

Hi Conor,

On Mon, Aug 15, 2022 at 9:05 PM <Conor.Dooley@microchip.com> wrote:
>
> On 15/08/2022 20:57, Lad, Prabhakar wrote:
> > Hi Conor,
> >
> > Thank you for the review.
> >
> > On Mon, Aug 15, 2022 at 8:10 PM <Conor.Dooley@microchip.com> wrote:
> >>
> >> On 15/08/2022 16:14, Lad Prabhakar wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>
> >>> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> >>> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> >>> of the Renesas drivers depend on this config option.
> >>
> >> Hey Lad,
> >>
> >> I think I said something similar on v1, but I said it again
> >> to Samuel today so I may as well repost here too:
> >> "I think this and patch 12/12 with the defconfig changes should be
> > patch 8/8.
>
> It was a direct copy paste, hence the quotes ;)
:)
> Your patch 8/8 lines up with the current symbols while Samuel's
> doesn't.
>
> >
> >
> >> deferred until post LPC (which still leaves plenty of time for
> >> making the 6.1 merge window). We already have like 4 different
> >> approaches between the existing SOC_FOO symbols & two more when
> >> D1 stuff and the Renesas stuff is considered.
> >>
> >> Plan is to decide at LPC on one approach for what to do with
> >> Kconfig.socs & to me it seems like a good idea to do what's being
> >> done here - it's likely that further arm vendors will move and
> >> keeping the common symbols makes a lot of sense to me..."
> >>
> > Sure not a problem. But delaying patch 4 and 8 will make RZ/Five SoC
> > not buildable. Is that OK?
>
> No no, I prob just did a bad job of explaining. I meant more
> along the lines of "I don't think this is the right approach
> but I will defer reviewing until after LPC, when we have picked
> one approach to use for everyone". I'm sorry, poor choice of
> words maybe. I didn't mean drop these patches so that it does
> not build, keeping it buildable until then so that we can all
> test/review is the way to go. Not your fault we've done 4 different
> things so far!
>
> Hopefully that makes a bit more sense?
>
Yep, that makes sense.

> >
> >> Also, for the sake of my OCD could you pick either riscv or
> >> RISC-V and use it for the whole series? Pedantic I guess, but
> >> /shrug
> >>
> > Sorry did you mean I add riscv/RISC-V in the subject?
>
> You have some patches with RISC-V and some with riscv.
> What I meant was use one of the two for the whole series.

I followed the previous subjects for that file which were previously
accepted. But not a problem I'll change them to riscv instead.

Cheers,
Prabhakar

Re: [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> of the Renesas drivers depend on this config option.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

The technical part LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
>
>  endif # SOC_CANAAN
>
> +config ARCH_RENESAS

We definitely want ARCH_RENESAS, as it serves as a gatekeeper for
Kconfig options for IP cores found on Renesas ARM and RISC-V SoCs.

> +       bool
> +       select GPIOLIB
> +       select PINCTRL
> +       select SOC_BUS
> +
> +config SOC_RENESAS_RZFIVE

Do we need this symbol? You could as well make ARCH_RENESAS above
visible, and defer the actual SoC selection to ARCH_R9A07G043 in
drivers/soc/renesas/Kconfig[1].

I don't know what is the policy on RISC-V. ARM64 has a "single-symbol
in arch/arm64/Kconfig.platforms"-policy, so we handle SoC selection
in drivers/soc/renesas/Kconfig, and that is fine, as it avoids merge
conflicts.

> +       bool "Renesas RZ/Five SoC"
> +       select ARCH_R9A07G043
> +       select ARCH_RENESAS
> +       select RESET_CONTROLLER
> +       help
> +         This enables support for Renesas RZ/Five SoC.
> +
>  endmenu # "SoC selection"

[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-drivers-for-v6.1&id=ebd0e06f3063cc2e3a689112904b29720579c6d2

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Thu, Aug 18, 2022 at 4:16 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> > (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> > of the Renesas drivers depend on this config option.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> The technical part LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
> >
> >  endif # SOC_CANAAN
> >
> > +config ARCH_RENESAS
>
> We definitely want ARCH_RENESAS, as it serves as a gatekeeper for
> Kconfig options for IP cores found on Renesas ARM and RISC-V SoCs.
>
Agreed, or else we will end up touching too many Kconfig files.

> > +       bool
> > +       select GPIOLIB
> > +       select PINCTRL
> > +       select SOC_BUS
> > +
> > +config SOC_RENESAS_RZFIVE
>
> Do we need this symbol? You could as well make ARCH_RENESAS above
> visible, and defer the actual SoC selection to ARCH_R9A07G043 in
> drivers/soc/renesas/Kconfig[1].
>
I think we could drop it and just defer the actual SoC selection to
ARCH_R9A07G043 as you said.

> I don't know what is the policy on RISC-V. ARM64 has a "single-symbol
> in arch/arm64/Kconfig.platforms"-policy, so we handle SoC selection
> in drivers/soc/renesas/Kconfig, and that is fine, as it avoids merge
> conflicts.
>
Agreed.

@Conor - Does the above sound OK?

Cheers,
Prabhakar

Re: [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

[Conor.Dooley]

On 18/08/2022 19:19, Lad, Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi Geert,
> 
> Thank you for the review.
> 
> On Thu, Aug 18, 2022 at 4:16 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>
>> Hi Prabhakar,
>>
>> On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
>> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
>>> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
>>> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
>>> of the Renesas drivers depend on this config option.
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>
>> Thanks for your patch!
>>
>> The technical part LGTM, so
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>
>>> --- a/arch/riscv/Kconfig.socs
>>> +++ b/arch/riscv/Kconfig.socs
>>> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
>>>
>>>  endif # SOC_CANAAN
>>>
>>> +config ARCH_RENESAS
>>
>> We definitely want ARCH_RENESAS, as it serves as a gatekeeper for
>> Kconfig options for IP cores found on Renesas ARM and RISC-V SoCs.
>>
> Agreed, or else we will end up touching too many Kconfig files.
> 
>>> +       bool
>>> +       select GPIOLIB
>>> +       select PINCTRL
>>> +       select SOC_BUS
>>> +
>>> +config SOC_RENESAS_RZFIVE
>>
>> Do we need this symbol? You could as well make ARCH_RENESAS above
>> visible, and defer the actual SoC selection to ARCH_R9A07G043 in
>> drivers/soc/renesas/Kconfig[1].
>>
> I think we could drop it and just defer the actual SoC selection to
> ARCH_R9A07G043 as you said.
> 
>> I don't know what is the policy on RISC-V. ARM64 has a "single-symbol
>> in arch/arm64/Kconfig.platforms"-policy, so we handle SoC selection
>> in drivers/soc/renesas/Kconfig, and that is fine, as it avoids merge
>> conflicts.
>>
> Agreed.
> 
> @Conor - Does the above sound OK?

It's not my decision to be honest - Palmer's the boss :)

I would rather have a single symbol & a single approach so that we are
all doing the same thing here. As of now, we have all basically done
different things for each SOC that was added - there's SOC_SIFIVE &
SOC_MICROCHIP_POLARFIRE which are obviously not doing the same thing
for starters & then how the symbol is used: selects vs depends + default
all varies between the symbols.

I tried to make some changes to the PolarFire one a few months ago to
add some peripherals but Palmer was not too keen on the changes. We had
a conversation on IRC, the upshot of which was deciding to talk about it
at Plumbers (which is in 3 weeks) as none of them follow his original
intent:
<quote>
the original idea behind Kconfig.socs was to provide an easy place for
users to say "I want all the support for SOC X", and then just have one
Kconfig to turn that on
<\quote>

In theory, that's lovely but not really maintainable & none of us were
doing it anyway. Hopefully we can come up with a plan at Plumbers - so
feel free to chime in (or maybe it gets sorted out here and I don't
have to do any public speaking 😍).

I like Geert's suggestion, I am leaning towards moving everyone to use
ARCH_FOO as its more generic & people that aren't starting with RISC-V
are already likely to be using it. It's the same with the d1 stuff, why
add an extra symbol and layer of indirection why there's a perfectly
good ARCH_SUNXI everywhere that can be reused.

But as I said, not my decision to make & I certainly don't want to be
standing in the way (although I'd say this is unlikely to be applied
before LPC given recent application timelines).

Hope that helps? Or at least explains a bit of where I am coming from..
Conor.

Re: [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

[Geert Uytterhoeven]

Hi Conor,

On Thu, Aug 18, 2022 at 8:54 PM <Conor.Dooley@microchip.com> wrote:
> On 18/08/2022 19:19, Lad, Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > On Thu, Aug 18, 2022 at 4:16 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> >> On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
> >> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> >>> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> >>> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> >>> of the Renesas drivers depend on this config option.
> >>>
> >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>
> >> Thanks for your patch!
> >>
> >> The technical part LGTM, so
> >> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >>
> >>> --- a/arch/riscv/Kconfig.socs
> >>> +++ b/arch/riscv/Kconfig.socs
> >>> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
> >>>
> >>>  endif # SOC_CANAAN
> >>>
> >>> +config ARCH_RENESAS
> >>
> >> We definitely want ARCH_RENESAS, as it serves as a gatekeeper for
> >> Kconfig options for IP cores found on Renesas ARM and RISC-V SoCs.
> >>
> > Agreed, or else we will end up touching too many Kconfig files.
> >
> >>> +       bool
> >>> +       select GPIOLIB
> >>> +       select PINCTRL
> >>> +       select SOC_BUS
> >>> +
> >>> +config SOC_RENESAS_RZFIVE
> >>
> >> Do we need this symbol? You could as well make ARCH_RENESAS above
> >> visible, and defer the actual SoC selection to ARCH_R9A07G043 in
> >> drivers/soc/renesas/Kconfig[1].
> >>
> > I think we could drop it and just defer the actual SoC selection to
> > ARCH_R9A07G043 as you said.
> >
> >> I don't know what is the policy on RISC-V. ARM64 has a "single-symbol
> >> in arch/arm64/Kconfig.platforms"-policy, so we handle SoC selection
> >> in drivers/soc/renesas/Kconfig, and that is fine, as it avoids merge
> >> conflicts.
> >>
> > Agreed.
> >
> > @Conor - Does the above sound OK?
>
> It's not my decision to be honest - Palmer's the boss :)
>
> I would rather have a single symbol & a single approach so that we are
> all doing the same thing here. As of now, we have all basically done
> different things for each SOC that was added - there's SOC_SIFIVE &
> SOC_MICROCHIP_POLARFIRE which are obviously not doing the same thing
> for starters & then how the symbol is used: selects vs depends + default
> all varies between the symbols.
>
> I tried to make some changes to the PolarFire one a few months ago to
> add some peripherals but Palmer was not too keen on the changes. We had
> a conversation on IRC, the upshot of which was deciding to talk about it
> at Plumbers (which is in 3 weeks) as none of them follow his original
> intent:
> <quote>
> the original idea behind Kconfig.socs was to provide an easy place for
> users to say "I want all the support for SOC X", and then just have one
> Kconfig to turn that on
> <\quote>

For whatever definition of "all"? Does this include e.g. all
multi-media stuff?

For Renesas ARM SoCs, we make sure to select the critical core parts,
cfr. the selects above, and in drivers/soc/renesas/Kconfig.
These selects do not include optional drivers, including the serial
port (cfr. your confusion about adding CONFIG_SERIAL_SH_SCI=y
to the defconfig).
All the rest is handled by the defconfigs (shmobile_defconfig on
arm32, single defconfig on arm64, and out-of-tree renesas_defconfig
in my renesas-devel tree).

> In theory, that's lovely but not really maintainable & none of us were
> doing it anyway. Hopefully we can come up with a plan at Plumbers - so
> feel free to chime in (or maybe it gets sorted out here and I don't
> have to do any public speaking 😍).

Ah, there is my good reason for registering for LPC ;-)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

[Conor.Dooley]

On 19/08/2022 08:35, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi Conor,
> 
> On Thu, Aug 18, 2022 at 8:54 PM <Conor.Dooley@microchip.com> wrote:
>> On 18/08/2022 19:19, Lad, Prabhakar wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>> On Thu, Aug 18, 2022 at 4:16 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>>> On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
>>>> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
>>>>> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
>>>>> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
>>>>> of the Renesas drivers depend on this config option.
>>>>>
>>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>>
>>>> Thanks for your patch!
>>>>
>>>> The technical part LGTM, so
>>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>>>
>>>>> --- a/arch/riscv/Kconfig.socs
>>>>> +++ b/arch/riscv/Kconfig.socs
>>>>> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
>>>>>
>>>>>   endif # SOC_CANAAN
>>>>>
>>>>> +config ARCH_RENESAS
>>>>
>>>> We definitely want ARCH_RENESAS, as it serves as a gatekeeper for
>>>> Kconfig options for IP cores found on Renesas ARM and RISC-V SoCs.
>>>>
>>> Agreed, or else we will end up touching too many Kconfig files.
>>>
>>>>> +       bool
>>>>> +       select GPIOLIB
>>>>> +       select PINCTRL
>>>>> +       select SOC_BUS
>>>>> +
>>>>> +config SOC_RENESAS_RZFIVE
>>>>
>>>> Do we need this symbol? You could as well make ARCH_RENESAS above
>>>> visible, and defer the actual SoC selection to ARCH_R9A07G043 in
>>>> drivers/soc/renesas/Kconfig[1].
>>>>
>>> I think we could drop it and just defer the actual SoC selection to
>>> ARCH_R9A07G043 as you said.
>>>
>>>> I don't know what is the policy on RISC-V. ARM64 has a "single-symbol
>>>> in arch/arm64/Kconfig.platforms"-policy, so we handle SoC selection
>>>> in drivers/soc/renesas/Kconfig, and that is fine, as it avoids merge
>>>> conflicts.
>>>>
>>> Agreed.
>>>
>>> @Conor - Does the above sound OK?
>>
>> It's not my decision to be honest - Palmer's the boss :)
>>
>> I would rather have a single symbol & a single approach so that we are
>> all doing the same thing here. As of now, we have all basically done
>> different things for each SOC that was added - there's SOC_SIFIVE &
>> SOC_MICROCHIP_POLARFIRE which are obviously not doing the same thing
>> for starters & then how the symbol is used: selects vs depends + default
>> all varies between the symbols.
>>
>> I tried to make some changes to the PolarFire one a few months ago to
>> add some peripherals but Palmer was not too keen on the changes. We had
>> a conversation on IRC, the upshot of which was deciding to talk about it
>> at Plumbers (which is in 3 weeks) as none of them follow his original
>> intent:
>> <quote>
>> the original idea behind Kconfig.socs was to provide an easy place for
>> users to say "I want all the support for SOC X", and then just have one
>> Kconfig to turn that on
>> <\quote>
> 
> For whatever definition of "all"? Does this include e.g. all
> multi-media stuff?

Yeah.. gets unmaintainable fast!

> 
> For Renesas ARM SoCs, we make sure to select the critical core parts,
> cfr. the selects above, and in drivers/soc/renesas/Kconfig.
> These selects do not include optional drivers, including the serial
> port (cfr. your confusion about adding CONFIG_SERIAL_SH_SCI=y
> to the defconfig).

tbf, the reason it was done was fairly obvious, but since it wasn't
mentioned just wanted to double check it wasn't an accident ;)

I like the approach you suggested approach a lot tbh, makes a lot
of sense & doesn't involve having to merge the symbol for a core
driver through arch/riscv if something changes.

> All the rest is handled by the defconfigs (shmobile_defconfig on
> arm32, single defconfig on arm64, and out-of-tree renesas_defconfig
> in my renesas-devel tree).
> 
>> In theory, that's lovely but not really maintainable & none of us were
>> doing it anyway. Hopefully we can come up with a plan at Plumbers - so
>> feel free to chime in (or maybe it gets sorted out here and I don't
>> have to do any public speaking 😍).
> 
> Ah, there is my good reason for registering for LPC ;-)
> 
> Gr{oetje,eeting}s,
> 
>                          Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                  -- Linus Torvalds

[PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

[Lad Prabhakar]

Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
Single).

Below is the list of IP blocks added in the initial SoC DTSI which can be
used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
* Dropped including makefile change
* Updated ndev count
---
 arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
 1 file changed, 121 insertions(+)
 create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
new file mode 100644
index 000000000000..b288d2607796
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/r9a07g043-cpg.h>
+
+/ {
+	compatible = "renesas,r9a07g043";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+	extal_clk: extal-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <24000000>;
+
+		ax45mp: cpu@0 {
+			compatible = "andestech,ax45mp", "riscv";
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
+				 <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		scif0: serial@1004b800 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004b800 0 0x400>;
+			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
+				     <414 IRQ_TYPE_LEVEL_HIGH>,
+				     <415 IRQ_TYPE_LEVEL_HIGH>,
+				     <413 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller@11010000 {
+			compatible = "renesas,r9a07g043-cpg";
+			reg = <0 0x11010000 0 0x10000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sysc: system-controller@11020000 {
+			compatible = "renesas,r9a07g043-sysc";
+			reg = <0 0x11020000 0 0x10000>;
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl@11030000 {
+			compatible = "renesas,r9a07g043-pinctrl";
+			reg = <0 0x11030000 0 0x10000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			gpio-ranges = <&pinctrl 0 0 152>;
+			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_GPIO_RSTN>,
+				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
+				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
+		};
+
+		plic: interrupt-controller@12c00000 {
+			compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			riscv,ndev = <512>;
+			interrupt-controller;
+			reg = <0x0 0x12c00000 0 0x400000>;
+			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+		};
+	};
+};
-- 
2.25.1

Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

[Geert Uytterhoeven]

Hi Prabhalar,

On Mon, Aug 15, 2022 at 5:17 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> Below is the list of IP blocks added in the initial SoC DTSI which can be
> used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SoC

My first thought was:

    This should be arch/riscv/boot/dts/renesas/r9a07g043f01.dtsi,
     including the common r9a07g043.dtsi, shared by
     arch/arm64/boot/dts/renesas/r9a07g043u11.dtsi.

Then I realized this is harder than it sounds, due:

> +       soc: soc {
> +               compatible = "simple-bus";
> +               interrupt-parent = <&plic>;

vs. "interrupt-parent = <&plic>;" for r9a07g043u11, but mostly
due to

> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               scif0: serial@1004b800 {
> +                       compatible = "renesas,scif-r9a07g043",
> +                                    "renesas,scif-r9a07g044";
> +                       reg = <0 0x1004b800 0 0x400>;
> +                       interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <414 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <415 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <413 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <416 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <416 IRQ_TYPE_LEVEL_HIGH>;

vs. "interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH> ..." on
r9a07g043u11.
Interestingly, the actual hardware interrupt numbers are the same,
but the GIC DT bindings abstracts the offset of 32 by using a second
cell and GIC_SPI.  Unfortunately this cannot be handled by some CPP
magic, as dtc does not support arithmetic operations yet.

I expect this or similar issues to pop up everywhere, when more
RISCV-V SoCs will appear that share the non-CPU parts with ARM SoCs.

Ignoring this issue, which we probably can solve only later:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Geert,

On Fri, Aug 19, 2022 at 9:05 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhalar,
>
> On Mon, Aug 15, 2022 at 5:17 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
>
> My first thought was:
>
>     This should be arch/riscv/boot/dts/renesas/r9a07g043f01.dtsi,
>      including the common r9a07g043.dtsi, shared by
>      arch/arm64/boot/dts/renesas/r9a07g043u11.dtsi.
>
> Then I realized this is harder than it sounds, due:
>
Indeed, my initial thought after the comments from Conor was we could
share the SoC dtsi, but that would be to messey due to PLIC.

Cheers,
Prabhakar

> > +       soc: soc {
> > +               compatible = "simple-bus";
> > +               interrupt-parent = <&plic>;
>
> vs. "interrupt-parent = <&plic>;" for r9a07g043u11, but mostly
> due to
>
> > +               #address-cells = <2>;
> > +               #size-cells = <2>;
> > +               ranges;
> > +
> > +               scif0: serial@1004b800 {
> > +                       compatible = "renesas,scif-r9a07g043",
> > +                                    "renesas,scif-r9a07g044";
> > +                       reg = <0 0x1004b800 0 0x400>;
> > +                       interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <414 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <415 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <413 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <416 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <416 IRQ_TYPE_LEVEL_HIGH>;
>
> vs. "interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH> ..." on
> r9a07g043u11.
> Interestingly, the actual hardware interrupt numbers are the same,
> but the GIC DT bindings abstracts the offset of 32 by using a second
> cell and GIC_SPI.  Unfortunately this cannot be handled by some CPP
> magic, as dtc does not support arithmetic operations yet.
>
> I expect this or similar issues to pop up everywhere, when more
> RISCV-V SoCs will appear that share the non-CPU parts with ARM SoCs.
>
> Ignoring this issue, which we probably can solve only later:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

[Conor.Dooley]

Hey Prabhakar,
(btw should I use Lad or Prabhakar?)

On 15/08/2022 16:14, Lad Prabhakar wrote:
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
> 
> Below is the list of IP blocks added in the initial SoC DTSI which can be
> used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> * Dropped including makefile change
> * Updated ndev count
> ---
>  arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>  1 file changed, 121 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> 
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> new file mode 100644
> index 000000000000..b288d2607796
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SoC
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/r9a07g043-cpg.h>
> +
> +/ {
> +	compatible = "renesas,r9a07g043";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> +	extal_clk: extal-clk {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;

What's the value in having the clock-frequency here if the board .dtsi
overwrites it? dtbs_check will complain if someone forgets to fill it
IIUC & what the missing frequency means is also kinda obvious, no?

That aside, by convention so far we have put things like extals or
reference clocks below the /cpus node. Could you do the same here too
please?

> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <24000000>;
> +
> +		ax45mp: cpu@0 {
> +			compatible = "andestech,ax45mp", "riscv";
> +			device_type = "cpu";
> +			reg = <0x0>;
> +			status = "okay";
> +			riscv,isa = "rv64imafdc";
> +			mmu-type = "riscv,sv39";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <0x40>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <0x40>;
> +			clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> +				 <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;

I've been on a bit of a topology-fixing binge lately, so I noticed
that you are missing a link to the l2 cache here. FWIW this does show
up in userspace with things like "lstopo" so it might be nice to add
that in from the start. You don't need to have a driver for it at all,
just the entry itself & a "next-level-cache" entry for the CPU.

Other than those two things, and this l2 one is in the "nice to have"
category:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> +
> +			cpu0_intc: interrupt-controller {
> +				#interrupt-cells = <1>;
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +			};
> +		};
> +	};
> +
> +	soc: soc {
> +		compatible = "simple-bus";
> +		interrupt-parent = <&plic>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		scif0: serial@1004b800 {
> +			compatible = "renesas,scif-r9a07g043",
> +				     "renesas,scif-r9a07g044";
> +			reg = <0 0x1004b800 0 0x400>;
> +			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> +				     <414 IRQ_TYPE_LEVEL_HIGH>,
> +				     <415 IRQ_TYPE_LEVEL_HIGH>,
> +				     <413 IRQ_TYPE_LEVEL_HIGH>,
> +				     <416 IRQ_TYPE_LEVEL_HIGH>,
> +				     <416 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "eri", "rxi", "txi",
> +					  "bri", "dri", "tei";
> +			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> +			clock-names = "fck";
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> +			status = "disabled";
> +		};
> +
> +		cpg: clock-controller@11010000 {
> +			compatible = "renesas,r9a07g043-cpg";
> +			reg = <0 0x11010000 0 0x10000>;
> +			clocks = <&extal_clk>;
> +			clock-names = "extal";
> +			#clock-cells = <2>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <0>;
> +		};
> +
> +		sysc: system-controller@11020000 {
> +			compatible = "renesas,r9a07g043-sysc";
> +			reg = <0 0x11020000 0 0x10000>;
> +			status = "disabled";
> +		};
> +
> +		pinctrl: pinctrl@11030000 {
> +			compatible = "renesas,r9a07g043-pinctrl";
> +			reg = <0 0x11030000 0 0x10000>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			#interrupt-cells = <2>;
> +			interrupt-controller;
> +			gpio-ranges = <&pinctrl 0 0 152>;
> +			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_GPIO_RSTN>,
> +				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
> +				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> +		};
> +
> +		plic: interrupt-controller@12c00000 {
> +			compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> +			#interrupt-cells = <2>;
> +			#address-cells = <0>;
> +			riscv,ndev = <512>;
> +			interrupt-controller;
> +			reg = <0x0 0x12c00000 0 0x400000>;
> +			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> +			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> +		};
> +	};
> +};

Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

[Geert Uytterhoeven]

Hi Conor,

On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote:
> On 15/08/2022 16:14, Lad Prabhakar wrote:
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * Dropped including makefile change
> > * Updated ndev count
> > ---
> >  arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
> >  1 file changed, 121 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > new file mode 100644
> > index 000000000000..b288d2607796
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/clock/r9a07g043-cpg.h>
> > +
> > +/ {
> > +     compatible = "renesas,r9a07g043";
> > +     #address-cells = <2>;
> > +     #size-cells = <2>;
> > +
> > +     /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> > +     extal_clk: extal-clk {
> > +             compatible = "fixed-clock";
> > +             #clock-cells = <0>;
> > +             /* This value must be overridden by the board */
> > +             clock-frequency = <0>;
>
> What's the value in having the clock-frequency here if the board .dtsi
> overwrites it? dtbs_check will complain if someone forgets to fill it
> IIUC & what the missing frequency means is also kinda obvious, no?

Some external clocks may be optional. Hence "dtbs_check" will complain
if no "clock-frequency" is missing.

>
> That aside, by convention so far we have put things like extals or
> reference clocks below the /cpus node. Could you do the same here too
> please?

Really? We've been putting them at the root node for a long time,
since the separate "clocks" grouping subnode was deprecated.
The extal-clk is not even part of the SoC, so it should definitely
not be under the /cpus node.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

[Conor.Dooley]

On 20/08/2022 09:45, Geert Uytterhoeven wrote:
> Hi Conor,
> 
> On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote:
>> On 15/08/2022 16:14, Lad Prabhakar wrote:
>>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
>>> Single).
>>>
>>> Below is the list of IP blocks added in the initial SoC DTSI which can be
>>> used to boot via initramfs on RZ/Five SMARC EVK:
>>> - AX45MP CPU
>>> - CPG
>>> - PINCTRL
>>> - PLIC
>>> - SCIF0
>>> - SYSC
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> v1->v2
>>> * Dropped including makefile change
>>> * Updated ndev count
>>> ---
>>>  arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>>>  1 file changed, 121 insertions(+)
>>>  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>>>
>>> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>>> new file mode 100644
>>> index 000000000000..b288d2607796
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>>> @@ -0,0 +1,121 @@
>>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +/*
>>> + * Device Tree Source for the RZ/Five SoC
>>> + *
>>> + * Copyright (C) 2022 Renesas Electronics Corp.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/clock/r9a07g043-cpg.h>
>>> +
>>> +/ {
>>> +     compatible = "renesas,r9a07g043";
>>> +     #address-cells = <2>;
>>> +     #size-cells = <2>;
>>> +
>>> +     /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
>>> +     extal_clk: extal-clk {
>>> +             compatible = "fixed-clock";
>>> +             #clock-cells = <0>;
>>> +             /* This value must be overridden by the board */
>>> +             clock-frequency = <0>;
>>
>> What's the value in having the clock-frequency here if the board .dtsi
>> overwrites it? dtbs_check will complain if someone forgets to fill it
>> IIUC & what the missing frequency means is also kinda obvious, no?
> 
> Some external clocks may be optional. Hence "dtbs_check" will complain
> if no "clock-frequency" is missing.

Right, seems reasonable enough.

> 
>>
>> That aside, by convention so far we have put things like extals or
>> reference clocks below the /cpus node. Could you do the same here too
>> please?
> 
> Really? We've been putting them at the root node for a long time,
> since the separate "clocks" grouping subnode was deprecated.
> The extal-clk is not even part of the SoC, so it should definitely
> not be under the /cpus node.

Under may have been a confusing choice of words, I meant "physically"
under it in the file. Maybe after would have been a better choice of
words? I wasn't suggesting you put it inside the CPUs node.
Does that make more sense?
Conor.

Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

[Geert Uytterhoeven]

Hi Conor,

On Sat, Aug 20, 2022 at 10:49 AM <Conor.Dooley@microchip.com> wrote:
> On 20/08/2022 09:45, Geert Uytterhoeven wrote:
> > On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote:
> >> On 15/08/2022 16:14, Lad Prabhakar wrote:
> >>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> >>> Single).
> >>>
> >>> Below is the list of IP blocks added in the initial SoC DTSI which can be
> >>> used to boot via initramfs on RZ/Five SMARC EVK:
> >>> - AX45MP CPU
> >>> - CPG
> >>> - PINCTRL
> >>> - PLIC
> >>> - SCIF0
> >>> - SYSC
> >>>
> >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> >> That aside, by convention so far we have put things like extals or
> >> reference clocks below the /cpus node. Could you do the same here too
> >> please?
> >
> > Really? We've been putting them at the root node for a long time,
> > since the separate "clocks" grouping subnode was deprecated.
> > The extal-clk is not even part of the SoC, so it should definitely
> > not be under the /cpus node.
>
> Under may have been a confusing choice of words, I meant "physically"
> under it in the file. Maybe after would have been a better choice of
> words? I wasn't suggesting you put it inside the CPUs node.
> Does that make more sense?

Oh right, you mean the order of the nodes. Yes, "extal-clk" should
be after "cpus", following alphabetical sort order, as the nodes have no
unit addresses.

Sorry for missing that in my review.  I also misread "below"
(in Dutch there is only a single word for "below" and "under" ;-)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK

[Lad Prabhakar]

Enable the minimal blocks required for booting the Renesas RZ/Five
SMARC EVK with initramfs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
* New patch
---
 arch/riscv/boot/dts/Makefile                  |  1 +
 arch/riscv/boot/dts/renesas/Makefile          |  2 ++
 .../boot/dts/renesas/r9a07g043f01-smarc.dts   | 16 ++++++++++
 .../boot/dts/renesas/rzfive-smarc-som.dtsi    | 22 +++++++++++++
 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++
 5 files changed, 73 insertions(+)
 create mode 100644 arch/riscv/boot/dts/renesas/Makefile
 create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
 create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
 create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b0ff5fbabb0c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,5 +3,6 @@ subdir-y += sifive
 subdir-y += starfive
 subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
 subdir-y += microchip
+subdir-y += renesas
 
 obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
new file mode 100644
index 000000000000..2d3f5751a649
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
new file mode 100644
index 000000000000..7428f643a9b3
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include "r9a07g043.dtsi"
+#include "rzfive-smarc.dtsi"
+
+/ {
+	model = "Renesas SMARC EVK based on r9a07g043f01";
+	compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
new file mode 100644
index 000000000000..4a4acde6a2a7
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK SOM
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/ {
+	chosen {
+		bootargs = "ignore_loglevel";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x38000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <24000000>;
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
new file mode 100644
index 000000000000..4864a2a62d6b
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK carrier board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+#include "rzfive-smarc-som.dtsi"
+
+/ {
+	aliases {
+		serial0 = &scif0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&pinctrl {
+	scif0_pins: scif0 {
+		pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */
+			 <RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */
+	};
+};
+
+&scif0 {
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
-- 
2.25.1

Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK

[Conor.Dooley]

On 15/08/2022 16:14, Lad Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Enable the minimal blocks required for booting the Renesas RZ/Five
> SMARC EVK with initramfs.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> * New patch
> ---
>  arch/riscv/boot/dts/Makefile                  |  1 +
>  arch/riscv/boot/dts/renesas/Makefile          |  2 ++
>  .../boot/dts/renesas/r9a07g043f01-smarc.dts   | 16 ++++++++++
>  .../boot/dts/renesas/rzfive-smarc-som.dtsi    | 22 +++++++++++++
>  arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++
>  5 files changed, 73 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/renesas/Makefile
>  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
>  create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi

Just to sort out some of my own confusion here - is the smarc EVK
shared between your arm boards and the riscv ones? Or just the
peripherals etc on the soc?

If it is the forver, does the approach suggested here for the
allwinner stuff make sense to also use for risc-v stuff with
shared parts of devicetrees?
https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/

Would at least be interesting in hearing more opinions from the dt
people, Geert & Palmer. We have some SOM based stuff too with carriers
so I am interested in seeing how the cross platform part of that works
out.

Thanks,
Conor.

>  create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b0ff5fbabb0c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,5 +3,6 @@ subdir-y += sifive
>  subdir-y += starfive
>  subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
>  subdir-y += microchip
> +subdir-y += renesas
> 
>  obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
> new file mode 100644
> index 000000000000..2d3f5751a649
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> new file mode 100644
> index 000000000000..7428f643a9b3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +
> +#include "r9a07g043.dtsi"
> +#include "rzfive-smarc.dtsi"
> +
> +/ {
> +       model = "Renesas SMARC EVK based on r9a07g043f01";
> +       compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
> +};
> diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> new file mode 100644
> index 000000000000..4a4acde6a2a7
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK SOM
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +/ {
> +       chosen {
> +               bootargs = "ignore_loglevel";
> +       };
> +
> +       memory@48000000 {
> +               device_type = "memory";
> +               /* first 128MB is reserved for secure area. */
> +               reg = <0x0 0x48000000 0x0 0x38000000>;
> +       };
> +};
> +
> +&extal_clk {
> +       clock-frequency = <24000000>;
> +};
> diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> new file mode 100644
> index 000000000000..4864a2a62d6b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK carrier board
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> +#include "rzfive-smarc-som.dtsi"
> +
> +/ {
> +       aliases {
> +               serial0 = &scif0;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0:115200n8";
> +       };
> +};
> +
> +&pinctrl {
> +       scif0_pins: scif0 {
> +               pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */
> +                        <RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */
> +       };
> +};
> +
> +&scif0 {
> +       pinctrl-0 = <&scif0_pins>;
> +       pinctrl-names = "default";
> +       status = "okay";
> +};
> --
> 2.25.1
> 

Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK

[Lad, Prabhakar]

Hi Conor,

On Mon, Aug 15, 2022 at 8:00 PM <Conor.Dooley@microchip.com> wrote:
>
> On 15/08/2022 16:14, Lad Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Enable the minimal blocks required for booting the Renesas RZ/Five
> > SMARC EVK with initramfs.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * New patch
> > ---
> >  arch/riscv/boot/dts/Makefile                  |  1 +
> >  arch/riscv/boot/dts/renesas/Makefile          |  2 ++
> >  .../boot/dts/renesas/r9a07g043f01-smarc.dts   | 16 ++++++++++
> >  .../boot/dts/renesas/rzfive-smarc-som.dtsi    | 22 +++++++++++++
> >  arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++
> >  5 files changed, 73 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> >  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> >  create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
>
> Just to sort out some of my own confusion here - is the smarc EVK
> shared between your arm boards and the riscv ones? Or just the
> peripherals etc on the soc?
>
RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL
SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC
SoM and still be used.

> If it is the forver, does the approach suggested here for the
> allwinner stuff make sense to also use for risc-v stuff with
> shared parts of devicetrees?
> https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/
>
it does make sense. But I wonder where we would place the common
shared dtsi that can be used by two arch's.

> Would at least be interesting in hearing more opinions from the dt
> people, Geert & Palmer. We have some SOM based stuff too with carriers
> so I am interested in seeing how the cross platform part of that works
> out.
>
Yep, that would be interesting.

Cheers,
Prabhakar

Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, Aug 15, 2022 at 10:16 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Mon, Aug 15, 2022 at 8:00 PM <Conor.Dooley@microchip.com> wrote:
> > On 15/08/2022 16:14, Lad Prabhakar wrote:
> > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > >
> > > Enable the minimal blocks required for booting the Renesas RZ/Five
> > > SMARC EVK with initramfs.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2
> > > * New patch
> > > ---
> > >  arch/riscv/boot/dts/Makefile                  |  1 +
> > >  arch/riscv/boot/dts/renesas/Makefile          |  2 ++
> > >  .../boot/dts/renesas/r9a07g043f01-smarc.dts   | 16 ++++++++++
> > >  .../boot/dts/renesas/rzfive-smarc-som.dtsi    | 22 +++++++++++++
> > >  arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++
> > >  5 files changed, 73 insertions(+)
> > >  create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> > >  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> > >  create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> >
> > Just to sort out some of my own confusion here - is the smarc EVK
> > shared between your arm boards and the riscv ones? Or just the
> > peripherals etc on the soc?
> >
> RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL
> SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC
> SoM and still be used.
>
> > If it is the forver, does the approach suggested here for the
> > allwinner stuff make sense to also use for risc-v stuff with
> > shared parts of devicetrees?
> > https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/
> >
> it does make sense. But I wonder where we would place the common
> shared dtsi that can be used by two arch's.

You can keep it under arch/arm/boot/dts/renesas/, and refer to
it from riscv as <arm64/renesas/...>.
Cfr. the symlinks under scripts/dtc/include-prefixes/arm64/ and
e.g. cros-ec-keyboard.dtsi.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK

[Lad, Prabhakar]

Hi Geert,


On Fri, Aug 19, 2022 at 9:25 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Aug 15, 2022 at 10:16 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Mon, Aug 15, 2022 at 8:00 PM <Conor.Dooley@microchip.com> wrote:
> > > On 15/08/2022 16:14, Lad Prabhakar wrote:
> > > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > > >
> > > > Enable the minimal blocks required for booting the Renesas RZ/Five
> > > > SMARC EVK with initramfs.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v1->v2
> > > > * New patch
> > > > ---
> > > >  arch/riscv/boot/dts/Makefile                  |  1 +
> > > >  arch/riscv/boot/dts/renesas/Makefile          |  2 ++
> > > >  .../boot/dts/renesas/r9a07g043f01-smarc.dts   | 16 ++++++++++
> > > >  .../boot/dts/renesas/rzfive-smarc-som.dtsi    | 22 +++++++++++++
> > > >  arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++
> > > >  5 files changed, 73 insertions(+)
> > > >  create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> > > >  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> > > >  create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> > >
> > > Just to sort out some of my own confusion here - is the smarc EVK
> > > shared between your arm boards and the riscv ones? Or just the
> > > peripherals etc on the soc?
> > >
> > RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL
> > SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC
> > SoM and still be used.
> >
> > > If it is the forver, does the approach suggested here for the
> > > allwinner stuff make sense to also use for risc-v stuff with
> > > shared parts of devicetrees?
> > > https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/
> > >
> > it does make sense. But I wonder where we would place the common
> > shared dtsi that can be used by two arch's.
>
> You can keep it under arch/arm/boot/dts/renesas/, and refer to
> it from riscv as <arm64/renesas/...>.
> Cfr. the symlinks under scripts/dtc/include-prefixes/arm64/ and
> e.g. cros-ec-keyboard.dtsi.
>
Thanks for the pointer.

Cheers,
Prabhakar

Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK

[Conor.Dooley]

On 19/08/2022 12:39, Lad, Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi Geert,
> 
> 
> On Fri, Aug 19, 2022 at 9:25 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>
>> Hi Prabhakar,
>>
>> On Mon, Aug 15, 2022 at 10:16 PM Lad, Prabhakar
>> <prabhakar.csengg@gmail.com> wrote:
>>> On Mon, Aug 15, 2022 at 8:00 PM <Conor.Dooley@microchip.com> wrote:
>>>> On 15/08/2022 16:14, Lad Prabhakar wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> Enable the minimal blocks required for booting the Renesas RZ/Five
>>>>> SMARC EVK with initramfs.
>>>>>
>>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>>> ---
>>>>> v1->v2
>>>>> * New patch
>>>>> ---
>>>>>  arch/riscv/boot/dts/Makefile                  |  1 +
>>>>>  arch/riscv/boot/dts/renesas/Makefile          |  2 ++
>>>>>  .../boot/dts/renesas/r9a07g043f01-smarc.dts   | 16 ++++++++++
>>>>>  .../boot/dts/renesas/rzfive-smarc-som.dtsi    | 22 +++++++++++++
>>>>>  arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++
>>>>>  5 files changed, 73 insertions(+)
>>>>>  create mode 100644 arch/riscv/boot/dts/renesas/Makefile
>>>>>  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
>>>>>  create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
>>>>
>>>> Just to sort out some of my own confusion here - is the smarc EVK
>>>> shared between your arm boards and the riscv ones? Or just the
>>>> peripherals etc on the soc?
>>>>
>>> RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL
>>> SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC
>>> SoM and still be used.
>>>
>>>> If it is the forver, does the approach suggested here for the
>>>> allwinner stuff make sense to also use for risc-v stuff with
>>>> shared parts of devicetrees?
>>>> https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/
>>>>
>>> it does make sense. But I wonder where we would place the common
>>> shared dtsi that can be used by two arch's.
>>
>> You can keep it under arch/arm/boot/dts/renesas/, and refer to
>> it from riscv as <arm64/renesas/...>.
>> Cfr. the symlinks under scripts/dtc/include-prefixes/arm64/ and
>> e.g. cros-ec-keyboard.dtsi.
>>

Is this something that you intend doing or is that future work?
I had a quick, and I mean quick, look through the arm smarc dtsi
and none of them appeared to be a 1:1 match with what I see here.

I assume that's got something to do with the "minimal" in the
patch's subject line, and some re-org of the arm files would be
required? In any case, you've not introduced any more dtbs_check
detectable issues so you're good in my book whichever way you do
it.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK

[Geert Uytterhoeven]

On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Enable the minimal blocks required for booting the Renesas RZ/Five
> SMARC EVK with initramfs.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture

[Lad Prabhakar]

Initial Renesas RISC-V architecture support will be for the
RZ/Five SMARC EVK board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
* New patch
---
 MAINTAINERS | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index e3058091899f..b03763ed649b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17562,6 +17562,16 @@ F:	drivers/spi/spi-microchip-core.c
 F:	drivers/usb/musb/mpfs.c
 F:	include/soc/microchip/mpfs.h
 
+RISC-V/Renesas RISC-V ARCHITECTURE
+M:	Geert Uytterhoeven <geert+renesas@glider.be>
+L:	linux-renesas-soc@vger.kernel.org
+S:	Supported
+Q:	http://patchwork.kernel.org/project/linux-renesas-soc/list/
+C:	irc://irc.libera.chat/renesas-soc
+T:	git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
+F:	Documentation/devicetree/bindings/soc/renesas/
+F:	arch/riscv/boot/dts/renesas/
+
 RNBD BLOCK DRIVERS
 M:	Md. Haris Iqbal <haris.iqbal@ionos.com>
 M:	Jack Wang <jinpu.wang@ionos.com>
-- 
2.25.1

Re: [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Initial Renesas RISC-V architecture support will be for the
> RZ/Five SMARC EVK board.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -17562,6 +17562,16 @@ F:     drivers/spi/spi-microchip-core.c
>  F:     drivers/usb/musb/mpfs.c
>  F:     include/soc/microchip/mpfs.h
>
> +RISC-V/Renesas RISC-V ARCHITECTURE
> +M:     Geert Uytterhoeven <geert+renesas@glider.be>
> +L:     linux-renesas-soc@vger.kernel.org
> +S:     Supported
> +Q:     http://patchwork.kernel.org/project/linux-renesas-soc/list/
> +C:     irc://irc.libera.chat/renesas-soc
> +T:     git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
> +F:     Documentation/devicetree/bindings/soc/renesas/
> +F:     arch/riscv/boot/dts/renesas/
> +
>  RNBD BLOCK DRIVERS
>  M:     Md. Haris Iqbal <haris.iqbal@ionos.com>
>  M:     Jack Wang <jinpu.wang@ionos.com>

Perhaps we should merge them all into a single section for "Renesas
ARM/ARM64/RISC-V ARCHITECTURE", to follow up on "[PATCH/RFC]
MAINTAINERS: Merge ARM/Renesas ARM64 and ARM/SH-Mobile ARM
architectures" I've just ssent?
https://lore.kernel.org/r/a869b8afdc47aa637ebeefcc1ca7bc61244f34b9.1660898008.git.geert+renesas@glider.be/

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Fri, Aug 19, 2022 at 9:42 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Initial Renesas RISC-V architecture support will be for the
> > RZ/Five SMARC EVK board.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -17562,6 +17562,16 @@ F:     drivers/spi/spi-microchip-core.c
> >  F:     drivers/usb/musb/mpfs.c
> >  F:     include/soc/microchip/mpfs.h
> >
> > +RISC-V/Renesas RISC-V ARCHITECTURE
> > +M:     Geert Uytterhoeven <geert+renesas@glider.be>
> > +L:     linux-renesas-soc@vger.kernel.org
> > +S:     Supported
> > +Q:     http://patchwork.kernel.org/project/linux-renesas-soc/list/
> > +C:     irc://irc.libera.chat/renesas-soc
> > +T:     git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
> > +F:     Documentation/devicetree/bindings/soc/renesas/
> > +F:     arch/riscv/boot/dts/renesas/
> > +
> >  RNBD BLOCK DRIVERS
> >  M:     Md. Haris Iqbal <haris.iqbal@ionos.com>
> >  M:     Jack Wang <jinpu.wang@ionos.com>
>
> Perhaps we should merge them all into a single section for "Renesas
> ARM/ARM64/RISC-V ARCHITECTURE", to follow up on "[PATCH/RFC]
> MAINTAINERS: Merge ARM/Renesas ARM64 and ARM/SH-Mobile ARM
> architectures" I've just ssent?
> https://lore.kernel.org/r/a869b8afdc47aa637ebeefcc1ca7bc61244f34b9.1660898008.git.geert+renesas@glider.be/
>
Agreed, I'll merge this on top of your changes.

Cheers,
Prabhakar

[PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC

[Lad Prabhakar]

Enable Renesas RZ/Five SoC config in defconfig. It allows the default
upstream kernel to boot on RZ/Five SMARC EVK board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
* New patch
---
 arch/riscv/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index aed332a9d4ea..de0ccf816c08 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -26,6 +26,7 @@ CONFIG_EXPERT=y
 # CONFIG_SYSFS_SYSCALL is not set
 CONFIG_PROFILING=y
 CONFIG_SOC_MICROCHIP_POLARFIRE=y
+CONFIG_SOC_RENESAS_RZFIVE=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_SOC_VIRT=y
@@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SH_SCI=y
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_VIRTIO=y
-- 
2.25.1

Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC

[Conor.Dooley]

On 15/08/2022 16:14, Lad Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> upstream kernel to boot on RZ/Five SMARC EVK board.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> * New patch
> ---
>  arch/riscv/configs/defconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index aed332a9d4ea..de0ccf816c08 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -26,6 +26,7 @@ CONFIG_EXPERT=y
>  # CONFIG_SYSFS_SYSCALL is not set
>  CONFIG_PROFILING=y
>  CONFIG_SOC_MICROCHIP_POLARFIRE=y
> +CONFIG_SOC_RENESAS_RZFIVE=y
>  CONFIG_SOC_SIFIVE=y
>  CONFIG_SOC_STARFIVE=y
>  CONFIG_SOC_VIRT=y
> @@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y
>  CONFIG_SERIAL_8250=y
>  CONFIG_SERIAL_8250_CONSOLE=y
>  CONFIG_SERIAL_OF_PLATFORM=y
> +CONFIG_SERIAL_SH_SCI=y

What's this? The patch text makes this look like an accidental
inclusion, but I figure it is required for boot?
Thanks,
Conor.

>  CONFIG_VIRTIO_CONSOLE=y
>  CONFIG_HW_RANDOM=y
>  CONFIG_HW_RANDOM_VIRTIO=y
> --
> 2.25.1
> 

Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Conor,

Thank you for the review.

On Mon, Aug 15, 2022 at 7:52 PM <Conor.Dooley@microchip.com> wrote:
>
> On 15/08/2022 16:14, Lad Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > upstream kernel to boot on RZ/Five SMARC EVK board.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * New patch
> > ---
> >  arch/riscv/configs/defconfig | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index aed332a9d4ea..de0ccf816c08 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -26,6 +26,7 @@ CONFIG_EXPERT=y
> >  # CONFIG_SYSFS_SYSCALL is not set
> >  CONFIG_PROFILING=y
> >  CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > +CONFIG_SOC_RENESAS_RZFIVE=y
> >  CONFIG_SOC_SIFIVE=y
> >  CONFIG_SOC_STARFIVE=y
> >  CONFIG_SOC_VIRT=y
> > @@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y
> >  CONFIG_SERIAL_8250=y
> >  CONFIG_SERIAL_8250_CONSOLE=y
> >  CONFIG_SERIAL_OF_PLATFORM=y
> > +CONFIG_SERIAL_SH_SCI=y
>
> What's this? The patch text makes this look like an accidental
> inclusion, but I figure it is required for boot?
This enables the serial driver used by the RZ/Five SoC. SInce the
intention was to have a bootable board with default defconfig. I'll
update the commit message.

Cheers,
Prabhakar

> Thanks,
> Conor.
>
> >  CONFIG_VIRTIO_CONSOLE=y
> >  CONFIG_HW_RANDOM=y
> >  CONFIG_HW_RANDOM_VIRTIO=y
> > --
> > 2.25.1
> >
>

Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC

[Conor.Dooley]

On 15/08/2022 20:44, Lad, Prabhakar wrote:
> Hi Conor,
> 
> Thank you for the review.
> 
> On Mon, Aug 15, 2022 at 7:52 PM <Conor.Dooley@microchip.com> wrote:
>>
>> On 15/08/2022 16:14, Lad Prabhakar wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Enable Renesas RZ/Five SoC config in defconfig. It allows the default
>>> upstream kernel to boot on RZ/Five SMARC EVK board.
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> v1->v2
>>> * New patch
>>> ---
>>>  arch/riscv/configs/defconfig | 2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
>>> index aed332a9d4ea..de0ccf816c08 100644
>>> --- a/arch/riscv/configs/defconfig
>>> +++ b/arch/riscv/configs/defconfig
>>> @@ -26,6 +26,7 @@ CONFIG_EXPERT=y
>>>  # CONFIG_SYSFS_SYSCALL is not set
>>>  CONFIG_PROFILING=y
>>>  CONFIG_SOC_MICROCHIP_POLARFIRE=y
>>> +CONFIG_SOC_RENESAS_RZFIVE=y
>>>  CONFIG_SOC_SIFIVE=y
>>>  CONFIG_SOC_STARFIVE=y
>>>  CONFIG_SOC_VIRT=y
>>> @@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y
>>>  CONFIG_SERIAL_8250=y
>>>  CONFIG_SERIAL_8250_CONSOLE=y
>>>  CONFIG_SERIAL_OF_PLATFORM=y
>>> +CONFIG_SERIAL_SH_SCI=y
>>
>> What's this? The patch text makes this look like an accidental
>> inclusion, but I figure it is required for boot?
> This enables the serial driver used by the RZ/Five SoC. SInce the
> intention was to have a bootable board with default defconfig. I'll
> update the commit message.

SGTM, feel free to add
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
when you send your next version if you like.

Conor.

Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC

[Geert Uytterhoeven]

On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> upstream kernel to boot on RZ/Five SMARC EVK board.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
But this may need a respin if "[PATCH v2 4/8] RISC-V: Kconfig.socs:
Add Renesas RZ/Five SoC kconfig option" is changed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds