Re: [RFC 11/14] x86: add support for Dynamic Kernel Stacks

From: Dave Hansen <dave.hansen@intel.com>
To: Andy Lutomirski <luto@kernel.org>,
	Pasha Tatashin <pasha.tatashin@soleen.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
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Subject: Re: [RFC 11/14] x86: add support for Dynamic Kernel Stacks
Date: Mon, 11 Mar 2024 16:34:35 -0700	[thread overview]
Message-ID: <bedfa55b-b1d0-4e59-8c94-dbc5f8485a7f@intel.com> (raw)
In-Reply-To: <3e180c07-53db-4acb-a75c-1a33447d81af@app.fastmail.com>

On 3/11/24 15:17, Andy Lutomirski wrote:
> I *think* that all x86 implementations won't fill the TLB for a
> non-accessed page without also setting the accessed bit,

That's my understanding as well.  The SDM is a little more obtuse about it:

> Whenever the processor uses a paging-structure entry as part of
> linear-address translation, it sets the accessed flag in that entry
> (if it is not already set).

but it's there.

But if we start needing Accessed=1 to be accurate, clearing those PTEs
gets more expensive because it needs to be atomic to lock out the page
walker.  It basically needs to start getting treated similarly to what
is done for Dirty=1 on userspace PTEs.  Not the end of the world, of
course, but one more source of overhead.