Re: [PATCH v4 2/8] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney <ddaney@caviumnetworks.com>]

On 11/30/2017 02:56 PM, James Hogan wrote:
> On Thu, Nov 30, 2017 at 01:49:43PM -0800, David Daney wrote:
>> On 11/30/2017 01:36 PM, James Hogan wrote:
>>> On Tue, Nov 28, 2017 at 04:55:34PM -0800, David Daney wrote:
>>>> Signed-off-by: Carlos Munoz <cmunoz@cavium.com>
>>>> Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com>
>>>> Signed-off-by: David Daney <david.daney@cavium.com>
>>>> ---
>>>>    arch/mips/cavium-octeon/setup.c       |  6 ++++++
>>>>    arch/mips/include/asm/octeon/octeon.h | 12 ++++++++++--
>>>>    2 files changed, 16 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
>>>> index a8034d0dcade..99e6a68bc652 100644
>>>> --- a/arch/mips/cavium-octeon/setup.c
>>>> +++ b/arch/mips/cavium-octeon/setup.c
>>>> @@ -609,6 +609,12 @@ void octeon_user_io_init(void)
>>>>    #else
>>>>    	cvmmemctl.s.cvmsegenak = 0;
>>>>    #endif
>>>> +	if (OCTEON_IS_OCTEON3()) {
>>>> +		/* Enable LMTDMA */
>>>> +		cvmmemctl.s.lmtena = 1;
>>>> +		/* Scratch line to use for LMT operation */
>>>> +		cvmmemctl.s.lmtline = 2;
>>>
>>> Out of curiosity, is there significance to the value 2 and associated
>>> virtual address 0xffffffffffff8100, or is it pretty arbitrary?
>>
>> Yes, there is significance.
>>
>> CPU local memory starts at 0xffffffffffff8000, each line is 0x80 bytes.
>> so the 2nd line starts at 0xffffffffffff8100
> 
> What I mean is, why is 2 chosen instead of any other value?

That is explained in the change log of patch 5/8:


     1st 128-bytes: Use by IOBDMA
     2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
     3rd 128-bytes: OCTEON-III LMTLINE

> 
> Cheers
> James
>