From: Ben Dooks <ben.dooks@codethink.co.uk>
To: Dmitry Osipenko <digetx@gmail.com>
Cc: pdeschrijver@nvidia.com, jonathanh@nvidia.co,
thierry.reding@gmail.com, linux-clk@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
pgaikwad@nvidia.com, linux-kernel@lists.codethink.co.uk
Subject: Re: [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks
Date: Mon, 23 Jul 2018 09:28:25 +0100 [thread overview]
Message-ID: <ca29f065814a22f46b9b1683165548cb@codethink.co.uk> (raw)
In-Reply-To: <1721645.6LMGIEI4vR@dimapc>
On 2018-07-22 12:55, Dmitry Osipenko wrote:
> On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote:
>> The 2D and 3D clocks have an IDLE field in bits 15:8 so add these
>> clocks by making a 2D and 3D mux, and split the divider into the
>> standard 2D/3D ones and 2D/3D idle clocks.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[snip]
>
> According to TRM, Tegra20 and Tegra114 have these "idle-mode" clock
> dividers
> as well. Why only T30 should have them?
I've got a separate series to sort t20 bits out, i've not used the
tegra114
>> a/include/dt-bindings/clock/tegra30-car.h
>> b/include/dt-bindings/clock/tegra30-car.h index
>> 3c90f1535551..eda4ca60351e
>> 100644
>> --- a/include/dt-bindings/clock/tegra30-car.h
>> +++ b/include/dt-bindings/clock/tegra30-car.h
>> @@ -269,6 +269,11 @@
>> #define TEGRA30_CLK_AUDIO3_MUX 306
>> #define TEGRA30_CLK_AUDIO4_MUX 307
>> #define TEGRA30_CLK_SPDIF_MUX 308
>> -#define TEGRA30_CLK_CLK_MAX 309
>> +
>> +#define TEGRA30_CLK_GR2D_MUX 309
>> +#define TEGRA30_CLK_GR3D_MUX 310
>> +#define TEGRA30_CLK_GR2D_IDLE 311
>> +#define TEGRA30_CLK_GR3D_IDLE 312
>> +#define TEGRA30_CLK_CLK_MAX 313
>>
>> #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
>
> IIUC, that "idle-mode" divisor is just some kind of power-safe feature,
> is
> there any real use-case for these clocks? Why not to just pre-configure
> the
> "idle-mode" bits during the clocks initialization?
It is is nice to have it available after to check, other than that we're
not
using any drivers that currently dynamically change the values of this.
next prev parent reply other threads:[~2018-07-23 8:28 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-20 13:45 tegra clock updates and fixes Ben Dooks
2018-07-20 13:45 ` [PATCH 1/8] clk: tegra: implement reset status callback Ben Dooks
2018-07-20 13:45 ` [PATCH 2/8] clk: tegra: host1x has fractional divider Ben Dooks
2018-07-23 8:50 ` Peter De Schrijver
2018-07-23 9:32 ` Ben Dooks
2018-07-23 11:12 ` Peter De Schrijver
2018-07-23 11:32 ` Ben Dooks
2018-07-20 13:45 ` [PATCH 3/8] clk: tegra: fix fractional clocks for VDI, VI, EPP, MPE, 2D and 3D Ben Dooks
2018-07-23 8:50 ` Peter De Schrijver
2018-07-20 13:45 ` [PATCH 4/8] clk: tegra: fix MUX_I2S_SPDIF macro Ben Dooks
2018-07-20 13:45 ` [PATCH 5/8] clk: tegra: add mux-only clock option Ben Dooks
2018-07-20 13:45 ` [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks Ben Dooks
2018-07-22 11:55 ` Dmitry Osipenko
2018-07-23 8:28 ` Ben Dooks [this message]
2018-07-23 11:33 ` Dmitry Osipenko
2018-07-23 11:37 ` Ben Dooks
2018-07-23 13:05 ` Dmitry Osipenko
2018-07-24 11:31 ` Dmitry Osipenko
2018-07-24 12:32 ` Ben Dooks
2018-07-20 13:45 ` [PATCH 7/8] clk: tegra: replace warn on with single line Ben Dooks
2018-07-20 13:45 ` [PATCH 8/8] clk: tegra: show clock name in error from _calc_rate Ben Dooks
2018-07-26 13:32 ` [Linux-kernel] tegra clock updates and fixes Ben Dooks
2018-07-26 15:22 ` Stephen Boyd
2018-07-27 8:22 ` Ben Dooks
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