From: Krishna Chaitanya Chundru <quic_krichai@quicinc.com>
To: Vinod Koul <vkoul@kernel.org>
Cc: <helgaas@kernel.org>, <linux-pci@vger.kernel.org>,
<linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<mka@chromium.org>, <quic_vbadigan@quicinc.com>,
<quic_hemantk@quicinc.com>, <quic_nitegupt@quicinc.com>,
<quic_skananth@quicinc.com>, <quic_ramkri@quicinc.com>,
<manivannan.sadhasivam@linaro.org>, <swboyd@chromium.org>,
<dmitry.baryshkov@linaro.org>, <svarbanov@mm-sol.com>,
<agross@kernel.org>, <andersson@kernel.org>,
<konrad.dybcio@somainline.org>, <lpieralisi@kernel.org>,
<robh@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>,
<linux-phy@lists.infradead.org>, <kishon@ti.com>,
<mturquette@baylibre.com>, <linux-clk@vger.kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Subject: Re: [PATCH v7 2/5] PCI: qcom: Add retry logic for link to be stable in either L1.1 or L1.2
Date: Sun, 25 Sep 2022 07:21:36 +0530 [thread overview]
Message-ID: <ccd8b282-107b-ea74-184b-34f72f07866f@quicinc.com> (raw)
In-Reply-To: <Yy6eJnXUMZk4i2PC@matsya>
On 9/24/2022 11:35 AM, Vinod Koul wrote:
> On 20-09-22, 15:52, Krishna chaitanya chundru wrote:
>> When link is in L1ss(L1.1 or L1.2), all the clocks will gate off and there
>> will be no activity on the link. At that point clocks and phy
>> can be turned off. If clocks got disabled before link enters
>> L1ss the PCIe link goes down.
>>
>> Few endpoints are taking time more time to settle the link in L1 substates.
>> When we check the traffic in protocol analyzer, we see some DLLP packets
>> going on still. So Wait for max time of 200ms for the link to be stable in
>> L1 substates.
>>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>> ---
>> changes since v6:
>> - updated comments.
>> ---
>> drivers/pci/controller/dwc/pcie-qcom.c | 46 ++++++++++++++++++++++++++--------
>> 1 file changed, 35 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index 3f5424a..7a6f69e 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -1809,23 +1809,47 @@ static int qcom_pcie_probe(struct platform_device *pdev)
>> static int __maybe_unused qcom_pcie_pm_suspend(struct qcom_pcie *pcie)
>> {
>> u32 val;
>> + ktime_t timeout, start;
>> struct dw_pcie *pci = pcie->pci;
>> struct device *dev = pci->dev;
>>
>> - /* if the link is not active turn off clocks */
>> - if (!dw_pcie_link_up(pci)) {
>> - dev_dbg(dev, "Link is not active\n");
>> - goto suspend;
>> - }
>> + /*
>> + * When link is in L1ss, all the clocks will gate off and
>> + * there will be no activity on the link. At that point clocks
>> + * and phy can be turned off. If clocks got disabled before
>> + * link enters L1ss the PCIe link goes down.
>> + *
>> + * Few endpoints are taking time more time to settle the link
>> + * in L1ss. Wait for max of 200ms for the link to be stable in
>> + * L1ss.
>> + */
>> + start = ktime_get();
>> + /* Wait max 200 ms */
>> + timeout = ktime_add_ms(start, 200);
>> +
>> + while (1) {
>> + /* if the liink is not active turn off clocks */
>> + if (!dw_pcie_link_up(pci)) {
>> + dev_dbg(dev, "Link is not active\n");
>> + break;
>> + }
>>
>> - /* if the link is not in l1ss don't turn off clocks */
>> - val = readl(pcie->parf + PCIE20_PARF_PM_STTS);
>> - if (!(val & PCIE20_PARF_PM_STTS_LINKST_IN_L1SUB)) {
>> - dev_warn(dev, "Link is not in L1ss\n");
>> - return 0;
>> + /* if the link is not in l1ss don't turn off clocks */
>> + val = readl(pcie->parf + PCIE20_PARF_PM_STTS);
>> + if ((val & PCIE20_PARF_PM_STTS_LINKST_IN_L1SUB)) {
>> + dev_dbg(dev, "Link enters L1ss after %lld ms\n",
>> + ktime_to_ms(ktime_get() - start));
>> + break;
>> + }
>> +
>> + if (ktime_after(ktime_get(), timeout)) {
>> + dev_warn(dev, "Link is not in L1ss\n");
>> + return 0;
>> + }
>> +
> ugh, why not use readl_poll_timeout()?
As this is called from the syscore ops, all the interrupts will be
disabled by the time the execution reaches here.
readl_poll_timeout uses interrupt internally and cause some issues.
So we are using this method instead of readl_poll_timeout.
>
>> + udelay(1000);
>> }
>>
>> -suspend:
>> if (pcie->cfg->ops->suspend)
>> pcie->cfg->ops->suspend(pcie);
>>
>> --
>> 2.7.4
next prev parent reply other threads:[~2022-09-25 1:52 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-20 10:22 [PATCH v7 0/5] PCI: qcom: Add system suspend & resume support Krishna chaitanya chundru
2022-09-20 10:22 ` [PATCH v7 1/5] PCI: qcom: Add system suspend and " Krishna chaitanya chundru
2022-09-20 18:16 ` Bjorn Helgaas
2022-09-21 9:53 ` Krishna Chaitanya Chundru
2022-09-21 16:56 ` Bjorn Helgaas
2022-09-22 15:39 ` Krishna Chaitanya Chundru
2022-09-22 18:42 ` Bjorn Helgaas
2022-09-23 1:59 ` Krishna Chaitanya Chundru
2022-09-23 14:26 ` Bjorn Helgaas
2022-09-25 1:53 ` Krishna Chaitanya Chundru
2022-09-28 14:32 ` Krishna Chaitanya Chundru
2022-09-26 15:30 ` Krishna Chaitanya Chundru
2022-09-29 18:53 ` Bjorn Helgaas
2022-10-03 12:10 ` Krishna Chaitanya Chundru
2022-10-05 21:13 ` Bjorn Helgaas
2022-10-12 14:06 ` Krishna Chaitanya Chundru
2022-10-13 0:44 ` Bjorn Helgaas
2022-09-20 21:58 ` Jeff Johnson
2022-09-20 10:22 ` [PATCH v7 2/5] PCI: qcom: Add retry logic for link to be stable in either L1.1 or L1.2 Krishna chaitanya chundru
2022-09-20 22:00 ` Jeff Johnson
2022-09-24 6:05 ` Vinod Koul
2022-09-25 1:51 ` Krishna Chaitanya Chundru [this message]
2022-09-20 10:22 ` [PATCH v7 3/5] phy: core: Add support for phy suspend & resume Krishna chaitanya chundru
2022-09-20 10:22 ` [PATCH v7 4/5] phy: qcom: Add power suspend & resume callbacks to PCIe phy Krishna chaitanya chundru
2022-09-20 10:22 ` [PATCH v7 5/5] clk: qcom: gcc-sc7280: Update the .pwrsts for PCIe GDSC Krishna chaitanya chundru
2022-09-27 3:23 ` (subset) [PATCH v7 0/5] PCI: qcom: Add system suspend & resume support Bjorn Andersson
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