From: Zong Li <zong@andestech.com>
To: <palmer@sifive.com>, <hch@infradead.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<zongbox@gmail.com>
Cc: Zong Li <zong@andestech.com>, <greentime@andestech.com>
Subject: [PATCH v2 0/4] Building for 32-bit RISC-V kernel
Date: Mon, 25 Jun 2018 16:49:36 +0800 [thread overview]
Message-ID: <cover.1529915117.git.zong@andestech.com> (raw)
These patches for building 32-bit RISC-V kernel.
- Fix the compile errors and warnings on RV32I.
- Fix some incompatible problem on RV32I.
- Add format.h for compatible of print format.
The fixed width integer types format for Elf_Addr will move to
generic header by another patch. For now, there are some warning
about unexpected argument of type on RV32I.
Change in v1:
- Fix some error in v1
- Remove implementation of fixed width integer types format for Elf_Addr.
Zong Li (4):
RISC-V: Add conditional macro for zone of DMA32
RISC-V: Select GENERIC_UCMPDI2 on RV32I
RISC-V: Add definiion of extract symbol's index and type for 32-bit
RISC-V: Change variable type for 32-bit compatible
arch/riscv/Kconfig | 1 +
arch/riscv/include/uapi/asm/elf.h | 9 +++++++--
arch/riscv/kernel/module.c | 22 +++++++++++-----------
arch/riscv/mm/init.c | 2 ++
4 files changed, 21 insertions(+), 13 deletions(-)
--
2.16.1
next reply other threads:[~2018-06-25 8:51 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-25 8:49 Zong Li [this message]
2018-06-25 8:49 ` [PATCH v2 1/4] RISC-V: Add conditional macro for zone of DMA32 Zong Li
2018-06-29 7:08 ` Christoph Hellwig
2018-06-25 8:49 ` [PATCH v2 2/4] RISC-V: Select GENERIC_UCMPDI2 on RV32I Zong Li
2018-06-29 7:08 ` Christoph Hellwig
2018-06-25 8:49 ` [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit Zong Li
2018-06-29 7:12 ` Christoph Hellwig
2018-06-29 16:53 ` Zong Li
2018-07-04 20:58 ` Palmer Dabbelt
2018-07-05 13:33 ` Zong Li
2018-07-05 16:42 ` Palmer Dabbelt
2018-06-25 8:49 ` [PATCH v2 4/4] RISC-V: Change variable type for 32-bit compatible Zong Li
2018-06-29 7:12 ` Christoph Hellwig
2018-06-29 7:23 ` [PATCH v2 0/4] Building for 32-bit RISC-V kernel Christoph Hellwig
2018-06-29 17:06 ` Zong Li
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cover.1529915117.git.zong@andestech.com \
--to=zong@andestech.com \
--cc=greentime@andestech.com \
--cc=hch@infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@sifive.com \
--cc=zongbox@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).