* [PATCH v3 1/2] dt-bindings: serial: lantiq: Convert to YAML schema
2019-08-21 7:06 [PATCH v3 0/2] dt-bindings: serial: lantiq: Convert to YAML & add support for new SoC Rahul Tanwar
@ 2019-08-21 7:06 ` Rahul Tanwar
2019-08-27 17:21 ` Rob Herring
2019-08-21 7:06 ` [PATCH v3 2/2] dt-bindings: lantiq: Update for new SoC Rahul Tanwar
1 sibling, 1 reply; 5+ messages in thread
From: Rahul Tanwar @ 2019-08-21 7:06 UTC (permalink / raw)
To: robh+dt, devicetree, gregkh, mark.rutland, linux-serial
Cc: linux-kernel, andriy.shevchenko, qi-ming.wu, cheol.yong.kim,
rahul.tanwar, Rahul Tanwar
Convert the existing DT binding document for Lantiq SoC ASC serial controller
from txt format to YAML format.
Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
---
.../devicetree/bindings/serial/lantiq,asc.yaml | 55 ++++++++++++++++++++++
.../devicetree/bindings/serial/lantiq_asc.txt | 31 ------------
2 files changed, 55 insertions(+), 31 deletions(-)
create mode 100644 Documentation/devicetree/bindings/serial/lantiq,asc.yaml
delete mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.txt
diff --git a/Documentation/devicetree/bindings/serial/lantiq,asc.yaml b/Documentation/devicetree/bindings/serial/lantiq,asc.yaml
new file mode 100644
index 000000000000..72ea2a3d75c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/lantiq,asc.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/lantiq,asc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq SoC ASC serial controller
+
+maintainers:
+ - Rahul Tanwar <rahul.tanwar@intel.com>
+
+allOf:
+ - $ref: /schemas/serial.yaml#
+
+properties:
+ compatible:
+ enum:
+ - lantiq,asc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 3
+
+ clocks:
+ items:
+ - description: phandle to the frequency clock
+ - description: phandle to the gate clock
+
+ clock-names:
+ items:
+ - const: freq
+ - const: asc
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+
+examples:
+ - |
+ asc0: serial@16600000 {
+ compatible = "lantiq,asc";
+ reg = <0x16600000 0x100000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
+ clock-names = "freq", "asc";
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
deleted file mode 100644
index 40e81a5818f6..000000000000
--- a/Documentation/devicetree/bindings/serial/lantiq_asc.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Lantiq SoC ASC serial controller
-
-Required properties:
-- compatible : Should be "lantiq,asc"
-- reg : Address and length of the register set for the device
-- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
- depends on the interrupt-parent interrupt controller.
-
-Optional properties:
-- clocks: Should contain frequency clock and gate clock
-- clock-names: Should be "freq" and "asc"
-
-Example:
-
-asc0: serial@16600000 {
- compatible = "lantiq,asc";
- reg = <0x16600000 0x100000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
- clock-names = "freq", "asc";
-};
-
-asc1: serial@e100c00 {
- compatible = "lantiq,asc";
- reg = <0xE100C00 0x400>;
- interrupt-parent = <&icu0>;
- interrupts = <112 113 114>;
-};
--
2.11.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v3 2/2] dt-bindings: lantiq: Update for new SoC
2019-08-21 7:06 [PATCH v3 0/2] dt-bindings: serial: lantiq: Convert to YAML & add support for new SoC Rahul Tanwar
2019-08-21 7:06 ` [PATCH v3 1/2] dt-bindings: serial: lantiq: Convert to YAML schema Rahul Tanwar
@ 2019-08-21 7:06 ` Rahul Tanwar
2019-08-27 17:22 ` Rob Herring
1 sibling, 1 reply; 5+ messages in thread
From: Rahul Tanwar @ 2019-08-21 7:06 UTC (permalink / raw)
To: robh+dt, devicetree, gregkh, mark.rutland, linux-serial
Cc: linux-kernel, andriy.shevchenko, qi-ming.wu, cheol.yong.kim,
rahul.tanwar, Rahul Tanwar
Intel Lightning Mountain(LGM) reuses Lantiq ASC serial controller IP.
Update the dt bindings to support LGM as well.
Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
---
.../devicetree/bindings/serial/lantiq,asc.yaml | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/lantiq,asc.yaml b/Documentation/devicetree/bindings/serial/lantiq,asc.yaml
index 72ea2a3d75c9..14241ef37e8a 100644
--- a/Documentation/devicetree/bindings/serial/lantiq,asc.yaml
+++ b/Documentation/devicetree/bindings/serial/lantiq,asc.yaml
@@ -15,12 +15,14 @@ allOf:
properties:
compatible:
enum:
+ - intel,lgm-asc
- lantiq,asc
reg:
maxItems: 1
interrupts:
+ minItems: 1
maxItems: 3
clocks:
@@ -38,6 +40,29 @@ required:
- reg
- interrupts
+if:
+ properties:
+ compatible:
+ enum:
+ - intel,lgm-asc
+
+then:
+ properties:
+ interrupts:
+ minItems: 1
+ maxItems: 1
+ items:
+ - description: combined interrupt for tx, rx & err
+
+else:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+ items:
+ - description: tx interrupt
+ - description: rx interrupt
+ - description: err interrupt
examples:
- |
@@ -52,4 +77,14 @@ examples:
clock-names = "freq", "asc";
};
+ - |
+ asc0: serial@e0a00000 {
+ compatible = "intel,lgm-asc";
+ reg = <0xe0a00000 0x1000>;
+ interrupt-parent = <&ioapic1>;
+ interrupts = <128 1>;
+ clocks = <&cgu0 LGM_CLK_NOC4>, <&cgu0 LGM_GCLK_ASC0>;
+ clock-names = "freq", "asc";
+ };
+
...
--
2.11.0
^ permalink raw reply related [flat|nested] 5+ messages in thread