From: Hector Martin <marcan@marcan.st>
To: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh+dt@kernel.org>, Sven Peter <sven@svenpeter.dev>,
Alyssa Rosenzweig <alyssa@rosenzweig.io>,
Mark Kettenis <mark.kettenis@xs4all.nl>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 3/7] irqchip/apple-aic: Add Fast IPI support
Date: Mon, 28 Feb 2022 00:33:54 +0900 [thread overview]
Message-ID: <d0e2a08e-79d6-03e8-09a2-bb634fa3c23c@marcan.st> (raw)
In-Reply-To: <87mtif2eoz.wl-maz@kernel.org>
On 25/02/2022 23.39, Marc Zyngier wrote:
> On Thu, 24 Feb 2022 13:07:37 +0000,
>> if (!(pending & irq_bit) &&
>> - (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit))
>> - send |= AIC_IPI_SEND_CPU(cpu);
>> + (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) {
>> + if (static_branch_likely(&use_fast_ipi))
>> + aic_ipi_send_fast(cpu);
>
> OK, this is suffering from the same issue that GICv3 has, which is
> that memory barriers don't provide order against sysregs. You need a
> DSB for that, which is a pain. Something like this:
Doesn't the control flow here guarantee the ordering? atomic_read() must
complete before the sysreg is written since there is a control flow
dependency, and the prior atomic/barrier dance ensures that read is
ordered properly with everything that comes before it.
--
Hector Martin (marcan@marcan.st)
Public Key: https://mrcn.st/pub
next prev parent reply other threads:[~2022-02-27 15:34 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-24 13:07 [PATCH v2 0/7] irqchip/apple-aic: Add support for AICv2 Hector Martin
2022-02-24 13:07 ` [PATCH v2 1/7] PCI: apple: Change MSI handling to handle 4-cell AIC fwspec form Hector Martin
2022-02-24 13:07 ` [PATCH v2 2/7] dt-bindings: interrupt-controller: apple,aic2: New binding for AICv2 Hector Martin
2022-02-25 20:19 ` Rob Herring
2022-02-25 21:58 ` Hector Martin
2022-03-07 11:35 ` Marc Zyngier
2022-02-24 13:07 ` [PATCH v2 3/7] irqchip/apple-aic: Add Fast IPI support Hector Martin
2022-02-25 14:39 ` Marc Zyngier
2022-02-27 15:33 ` Hector Martin [this message]
2022-03-07 11:35 ` Marc Zyngier
2022-02-24 13:07 ` [PATCH v2 4/7] irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqs Hector Martin
2022-02-24 13:07 ` [PATCH v2 5/7] irqchip/apple-aic: Dynamically compute register offsets Hector Martin
2022-02-24 13:07 ` [PATCH v2 6/7] irqchip/apple-aic: Support multiple dies Hector Martin
2022-02-24 13:07 ` [PATCH v2 7/7] irqchip/apple-aic: Add support for AICv2 Hector Martin
2022-02-25 15:27 ` Marc Zyngier
2022-02-25 22:05 ` Hector Martin
2022-02-24 18:26 ` [PATCH v2 0/7] " Mark Rutland
2022-02-24 19:06 ` Marc Zyngier
2022-02-25 4:27 ` Hector Martin
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