From: Peter Ujfalusi <peter.ujfalusi@ti.com>
To: Thierry Reding <treding@nvidia.com>, Tony Lindgren <tony@atomide.com>
Cc: Jon Hunter <jonathanh@nvidia.com>,
Belisko Marek <marek.belisko@gmail.com>,
LKML <linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>,
"Dr. H. Nikolaus Schaller" <hns@goldelico.com>,
Laxman Dewangan <ldewangan@nvidia.com>
Subject: Re: omap5 fixing palmas IRQ_TYPE_NONE warning leads to gpadc timeouts
Date: Mon, 26 Nov 2018 11:49:54 +0200 [thread overview]
Message-ID: <d3f17ac6-c13b-5b5f-a482-b565b130f1ba@ti.com> (raw)
In-Reply-To: <20181126093625.GA10878@ulmo>
Thierry,
On 11/26/18 11:36 AM, Thierry Reding wrote:
> On Fri, Nov 23, 2018 at 08:48:27AM -0800, Tony Lindgren wrote:
>> * Jon Hunter <jonathanh@nvidia.com> [181120 11:14]:
>>> On 19/11/2018 17:14, Tony Lindgren wrote:
>>>> Well so commit 7e9d474954f4 ("ARM: tegra: Correct polarity for
>>>> Tegra114 PMIC interrupt") states that tegra114 inverts the
>>>> polarity of the PMIC interrupt. So adding Jon and Thierry to Cc.
>>>
>>> Yes Tegra can invert the polarity of the PMIC interrupt.
>>
>> So is there some IP on Tegra called "Tegra PMC" that is
>> inverting the interrupt? Or is the "Tegra PMC" that commit
>> 7e9d474954f4 mentions just the palmas configuration for
>> inverting the interrupt?
>
> Yes, there's indeed an IP called PMC (Power-Management Controller) on
> Tegra. It has a special input that is usually wired up to the PMIC
> interrupt and a bit in the control register that configures the polarity
> of that interrupt. If the PMIC generates a low-active interrupt we
> usually set that bit to make sure it is properly sampled by the PMC.
>
> The symptoms of this being incorrectly configured is usually an
> interrupt storm on the PMIC interrupt, which I think typically results
> in the system not booting at all, or taking a very long time to boot
> because of that storm.
>
>> The problem I'm having is With omap5 where I can only get the
>> PMIC interrupts working with IRQ_TYPE_LEVEL_HIGH if
>> PALMAS_POLARITY_CTRL_INT_POLARITY is not set unlike for
>> Tegra.
>
> Does somebody have access to the Palmas documentation? That should
> pretty clearly state what the default polarity is and what it changes to
> if you set the interrupt polarity bit.
The register map documentation I have states the following:
bit7 INT_POLARITY Select the polarity of the INT output line
0: Interrupt line (INT) is low when interrupt is pending (default) RW
1: Interrupt line (INT) is high when interrupt is pending
By default the Palmas irq is active low.
> From what you're saying it sounds like either the logic is the wrong way
> around in the Palmas MFD driver (and we correct it by switching it back
> to the correct polarity in the PMC) or that you'd need to find some way
> of inverting in on OMAP5.
>
> Thierry
>
- Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
next prev parent reply other threads:[~2018-11-26 9:49 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-20 16:37 omap5 fixing palmas IRQ_TYPE_NONE warning leads to gpadc timeouts Belisko Marek
2018-07-03 8:45 ` Tony Lindgren
2018-07-03 18:31 ` Belisko Marek
2018-11-13 18:06 ` Tony Lindgren
2018-11-14 17:03 ` Tony Lindgren
2018-11-14 17:26 ` Tony Lindgren
2018-11-19 10:18 ` Peter Ujfalusi
2018-11-19 16:19 ` Tony Lindgren
2018-11-19 17:14 ` Tony Lindgren
2018-11-20 11:14 ` Jon Hunter
2018-11-23 16:48 ` Tony Lindgren
2018-11-26 9:36 ` Thierry Reding
2018-11-26 9:49 ` Peter Ujfalusi [this message]
2018-11-26 10:25 ` Thierry Reding
2018-11-26 19:32 ` Tony Lindgren
2018-11-26 20:17 ` Jon Hunter
2018-11-27 17:55 ` Tony Lindgren
2018-11-27 18:17 ` Tony Lindgren
2018-11-26 10:13 ` Jon Hunter
2018-11-20 12:22 ` Laxman Dewangan
2018-11-26 10:14 ` Thierry Reding
2018-11-26 19:14 ` Tony Lindgren
2018-11-26 19:19 ` Santosh Shilimkar
2018-11-27 18:03 ` Tony Lindgren
2018-11-20 7:36 ` Peter Ujfalusi
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