* [0/2] Add mmsys reset control for MT8186
@ 2022-02-15 13:19 Rex-BC Chen
2022-02-15 13:19 ` [1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data Rex-BC Chen
2022-02-15 13:19 ` [2/2] soc: mediatek: mmsys: add mmsys reset control for MT8186 Rex-BC Chen
0 siblings, 2 replies; 5+ messages in thread
From: Rex-BC Chen @ 2022-02-15 13:19 UTC (permalink / raw)
To: matthias.bgg
Cc: chunkuang.hu, jitao.shi, xinlei.lee, enric.balletbo,
angelogioacchino.delregno, linux-arm-kernel, linux-mediatek,
linux-kernel, Project_Global_Chrome_Upstream_Group, Rex-BC Chen
This series is based on mmsys patch for MT8186 on [1].
[1]: https://patchwork.kernel.org/project/linux-mediatek/patch/20220215075953.3310-4-rex-bc.chen@mediatek.com/
v1
1. Add a new variable in mmsys driver data to control different register offset for different SoCs.
2. Add MT8183 reset register offset.
3. Add mmsys reset control for MT8186.
Rex-BC Chen (2):
soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
soc: mediatek: mmsys: add mmsys reset control for MT8186
drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
drivers/soc/mediatek/mtk-mmsys.c | 7 +++++--
drivers/soc/mediatek/mtk-mmsys.h | 3 +--
4 files changed, 10 insertions(+), 4 deletions(-)
--
2.18.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
2022-02-15 13:19 [0/2] Add mmsys reset control for MT8186 Rex-BC Chen
@ 2022-02-15 13:19 ` Rex-BC Chen
2022-02-15 13:54 ` AngeloGioacchino Del Regno
2022-02-15 13:19 ` [2/2] soc: mediatek: mmsys: add mmsys reset control for MT8186 Rex-BC Chen
1 sibling, 1 reply; 5+ messages in thread
From: Rex-BC Chen @ 2022-02-15 13:19 UTC (permalink / raw)
To: matthias.bgg
Cc: chunkuang.hu, jitao.shi, xinlei.lee, enric.balletbo,
angelogioacchino.delregno, linux-arm-kernel, linux-mediatek,
linux-kernel, Project_Global_Chrome_Upstream_Group, Rex-BC Chen
There are different software reset registers for difference MTK SoCs.
Therefore, we add a new variable "sw0_rst_offset" to control it.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
drivers/soc/mediatek/mtk-mmsys.c | 6 ++++--
drivers/soc/mediatek/mtk-mmsys.h | 3 +--
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 9dee485807c9..0c021f4b76d2 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -25,6 +25,8 @@
#define MT8183_RDMA0_SOUT_COLOR0 0x1
#define MT8183_RDMA1_SOUT_DSI0 0x1
+#define MT8183_MMSYS_SW0_RST_B 0x140
+
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 0da25069ffb3..cab62c3eac05 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
.routes = mmsys_default_routing_table,
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
+ .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+ .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -128,14 +130,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
spin_lock_irqsave(&mmsys->lock, flags);
- reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
+ reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
if (assert)
reg &= ~BIT(id);
else
reg |= BIT(id);
- writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
+ writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
spin_unlock_irqrestore(&mmsys->lock, flags);
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea..83320019b4cf 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -78,8 +78,6 @@
#define DSI_SEL_IN_RDMA 0x1
#define DSI_SEL_IN_MASK 0x1
-#define MMSYS_SW0_RST_B 0x140
-
struct mtk_mmsys_routes {
u32 from_comp;
u32 to_comp;
@@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const unsigned int sw0_rst_offset;
};
/*
--
2.18.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [2/2] soc: mediatek: mmsys: add mmsys reset control for MT8186
2022-02-15 13:19 [0/2] Add mmsys reset control for MT8186 Rex-BC Chen
2022-02-15 13:19 ` [1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data Rex-BC Chen
@ 2022-02-15 13:19 ` Rex-BC Chen
1 sibling, 0 replies; 5+ messages in thread
From: Rex-BC Chen @ 2022-02-15 13:19 UTC (permalink / raw)
To: matthias.bgg
Cc: chunkuang.hu, jitao.shi, xinlei.lee, enric.balletbo,
angelogioacchino.delregno, linux-arm-kernel, linux-mediatek,
linux-kernel, Project_Global_Chrome_Upstream_Group, Rex-BC Chen
Add mmsys reset control register offset 0x160 for MT8186.
This patch is based on mmsys patch for MT8186 on [1].
[1]: https://patchwork.kernel.org/project/linux-mediatek/patch/20220215075953.3310-4-rex-bc.chen@mediatek.com/
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
drivers/soc/mediatek/mtk-mmsys.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index 7de329f2d729..c72ccf86ea28 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -52,6 +52,8 @@
#define MT8186_DPI0_FROM_DITHER0 1
#define MT8186_DPI0_FROM_RDMA0 2
+#define MT8186_MMSYS_SW0_RST_B 0x160
+
static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index cab62c3eac05..4fc4c2c9ea20 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -63,6 +63,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
.clk_driver = "clk-mt8186-mm",
.routes = mmsys_mt8186_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
+ .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
--
2.18.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
2022-02-15 13:19 ` [1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data Rex-BC Chen
@ 2022-02-15 13:54 ` AngeloGioacchino Del Regno
2022-02-16 1:39 ` Rex-BC Chen
0 siblings, 1 reply; 5+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-15 13:54 UTC (permalink / raw)
To: Rex-BC Chen, matthias.bgg
Cc: chunkuang.hu, jitao.shi, xinlei.lee, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Il 15/02/22 14:19, Rex-BC Chen ha scritto:
> There are different software reset registers for difference MTK SoCs.
> Therefore, we add a new variable "sw0_rst_offset" to control it.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
> drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
> drivers/soc/mediatek/mtk-mmsys.c | 6 ++++--
> drivers/soc/mediatek/mtk-mmsys.h | 3 +--
> 3 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 9dee485807c9..0c021f4b76d2 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -25,6 +25,8 @@
> #define MT8183_RDMA0_SOUT_COLOR0 0x1
> #define MT8183_RDMA1_SOUT_DSI0 0x1
>
> +#define MT8183_MMSYS_SW0_RST_B 0x140
> +
> static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 0da25069ffb3..cab62c3eac05 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .clk_driver = "clk-mt8173-mm",
> .routes = mmsys_default_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> + .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> + .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> @@ -128,14 +130,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
>
> spin_lock_irqsave(&mmsys->lock, flags);
>
> - reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
> + reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
>
> if (assert)
> reg &= ~BIT(id);
> else
> reg |= BIT(id);
>
> - writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
> + writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
>
> spin_unlock_irqrestore(&mmsys->lock, flags);
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 8b0ed05117ea..83320019b4cf 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -78,8 +78,6 @@
> #define DSI_SEL_IN_RDMA 0x1
> #define DSI_SEL_IN_MASK 0x1
>
> -#define MMSYS_SW0_RST_B 0x140
> -
> struct mtk_mmsys_routes {
> u32 from_comp;
> u32 to_comp;
> @@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> + const unsigned int sw0_rst_offset;
I don't think that this offset will ever be larger than 0xffff.
Can we use u16 here instead?
> };
>
> /*
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
2022-02-15 13:54 ` AngeloGioacchino Del Regno
@ 2022-02-16 1:39 ` Rex-BC Chen
0 siblings, 0 replies; 5+ messages in thread
From: Rex-BC Chen @ 2022-02-16 1:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, matthias.bgg
Cc: chunkuang.hu, jitao.shi, xinlei.lee, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Hello Angelo,
Thanks for yor review.
I add reply comment below:
On Tue, 2022-02-15 at 14:54 +0100, AngeloGioacchino Del Regno wrote:
> Il 15/02/22 14:19, Rex-BC Chen ha scritto:
> > There are different software reset registers for difference MTK
> > SoCs.
> > Therefore, we add a new variable "sw0_rst_offset" to control it.
> >
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
> > drivers/soc/mediatek/mtk-mmsys.c | 6 ++++--
> > drivers/soc/mediatek/mtk-mmsys.h | 3 +--
> > 3 files changed, 7 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mt8183-mmsys.h
> > b/drivers/soc/mediatek/mt8183-mmsys.h
> > index 9dee485807c9..0c021f4b76d2 100644
> > --- a/drivers/soc/mediatek/mt8183-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> > @@ -25,6 +25,8 @@
> > #define MT8183_RDMA0_SOUT_COLOR0 0x1
> > #define MT8183_RDMA1_SOUT_DSI0 0x1
> >
> > +#define MT8183_MMSYS_SW0_RST_B 0x140
> > +
> > static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[]
> > = {
> > {
> > DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 0da25069ffb3..cab62c3eac05 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .clk_driver = "clk-mt8173-mm",
> > .routes = mmsys_default_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > + .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .clk_driver = "clk-mt8183-mm",
> > .routes = mmsys_mt8183_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> > + .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > @@ -128,14 +130,14 @@ static int mtk_mmsys_reset_update(struct
> > reset_controller_dev *rcdev, unsigned l
> >
> > spin_lock_irqsave(&mmsys->lock, flags);
> >
> > - reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
> > + reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
> >
> > if (assert)
> > reg &= ~BIT(id);
> > else
> > reg |= BIT(id);
> >
> > - writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
> > + writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
> >
> > spin_unlock_irqrestore(&mmsys->lock, flags);
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 8b0ed05117ea..83320019b4cf 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -78,8 +78,6 @@
> > #define DSI_SEL_IN_RDMA 0x1
> > #define DSI_SEL_IN_MASK 0x1
> >
> > -#define MMSYS_SW0_RST_B 0x140
> > -
> > struct mtk_mmsys_routes {
> > u32 from_comp;
> > u32 to_comp;
> > @@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
> > const char *clk_driver;
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > + const unsigned int sw0_rst_offset;
>
> I don't think that this offset will ever be larger than 0xffff.
> Can we use u16 here instead?
>
Yes, the value of offset is enough using u16.
I will modify this in next version.
BRs,
Rex
> > };
> >
> > /*
>
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-02-16 1:39 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2022-02-15 13:19 [0/2] Add mmsys reset control for MT8186 Rex-BC Chen
2022-02-15 13:19 ` [1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data Rex-BC Chen
2022-02-15 13:54 ` AngeloGioacchino Del Regno
2022-02-16 1:39 ` Rex-BC Chen
2022-02-15 13:19 ` [2/2] soc: mediatek: mmsys: add mmsys reset control for MT8186 Rex-BC Chen
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