* [PATCH v2 0/7] Tegra210 clock bug fixes
@ 2017-02-23 10:44 Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1 Peter De Schrijver
` (8 more replies)
0 siblings, 9 replies; 14+ messages in thread
From: Peter De Schrijver @ 2017-02-23 10:44 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
A number of bug fixes for the Tegra210 clock implementation.
Changelog:
v2: add better description for 'remove non-existing pll_m_out1 clock'
Peter De Schrijver (7):
clk: tegra: fix pll_a1 iddq register, add pll_a1
clk: tegra: fix isp clock modelling
clk: tegra: correct afi parent
clk: tegra: remove non-existing pll_m_out1 clock
clk: tegra: don't warn for PLL defaults unnecessarily
clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation
clk: tegra: fix type for m field
drivers/clk/tegra/clk-id.h | 1 +
drivers/clk/tegra/clk-tegra-periph.c | 13 +++++++++---
drivers/clk/tegra/clk-tegra210.c | 35 ++++++++++++++++++++------------
drivers/clk/tegra/clk.h | 2 +-
include/dt-bindings/clock/tegra210-car.h | 4 ++--
5 files changed, 36 insertions(+), 19 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1
2017-02-23 10:44 [PATCH v2 0/7] Tegra210 clock bug fixes Peter De Schrijver
@ 2017-02-23 10:44 ` Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 2/7] clk: tegra: fix isp clock modelling Peter De Schrijver
` (7 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Peter De Schrijver @ 2017-02-23 10:44 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather
than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add pll_a1
to the set of clocks defined for Tegra210.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 2896d2e..2ef8d49 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -1772,7 +1772,7 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
.misc_reg = PLLA1_MISC0,
.lock_mask = PLLCX_BASE_LOCK,
.lock_delay = 300,
- .iddq_reg = PLLA1_MISC0,
+ .iddq_reg = PLLA1_MISC1,
.iddq_bit_idx = PLLCX_IDDQ_BIT,
.reset_reg = PLLA1_MISC0,
.reset_bit_idx = PLLCX_RESET_BIT,
@@ -2209,6 +2209,7 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
[tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
[tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
[tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
+ [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
};
static struct tegra_devclk devclks[] __initdata = {
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/7] clk: tegra: fix isp clock modelling
2017-02-23 10:44 [PATCH v2 0/7] Tegra210 clock bug fixes Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1 Peter De Schrijver
@ 2017-02-23 10:44 ` Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 3/7] clk: tegra: correct afi parent Peter De Schrijver
` (6 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Peter De Schrijver @ 2017-02-23 10:44 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
The 2 isp clocks (ispa and ispb) share a mux/divider control. So model
this as 1 mux/divider clock and child gate clocks.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-id.h | 1 +
drivers/clk/tegra/clk-tegra-periph.c | 11 +++++++++--
drivers/clk/tegra/clk-tegra210.c | 1 +
include/dt-bindings/clock/tegra210-car.h | 4 ++--
4 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 5738635..1019eb8 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -307,6 +307,7 @@ enum clk_id {
tegra_clk_xusb_ssp_src,
tegra_clk_sclk_mux,
tegra_clk_sor_safe,
+ tegra_clk_ispa,
tegra_clk_max,
};
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 4ce4e7f..19b00b7 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -168,6 +168,12 @@
0, TEGRA_PERIPH_NO_GATE, _clk_id,\
_parents##_idx, 0, _lock)
+#define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \
+ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
+ 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
+ 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
+ _parents##_idx, 0, NULL)
+
#define INT(_name, _parents, _offset, \
_clk_num, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
@@ -739,7 +745,7 @@
MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
- MUX8("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_9),
+ MUX8_NOGATE("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, tegra_clk_isp_9),
MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8),
MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
@@ -819,7 +825,8 @@
GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
- GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
+ GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),
+ GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),
GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 2ef8d49..7bda8ba 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2210,6 +2210,7 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
[tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
[tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
[tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
+ [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
};
static struct tegra_devclk devclks[] __initdata = {
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 35288b2..f5c6563 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -39,7 +39,7 @@
/* 20 (register bit affects vi and vi_sensor) */
/* 21 */
#define TEGRA210_CLK_USBD 22
-#define TEGRA210_CLK_ISP 23
+#define TEGRA210_CLK_ISPA 23
/* 24 */
/* 25 */
#define TEGRA210_CLK_DISP2 26
@@ -349,7 +349,7 @@
#define TEGRA210_CLK_PLL_RE_OUT1 319
/* 320 */
/* 321 */
-/* 322 */
+#define TEGRA210_CLK_ISP 322
/* 323 */
/* 324 */
/* 325 */
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 3/7] clk: tegra: correct afi parent
2017-02-23 10:44 [PATCH v2 0/7] Tegra210 clock bug fixes Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1 Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 2/7] clk: tegra: fix isp clock modelling Peter De Schrijver
@ 2017-02-23 10:44 ` Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 4/7] clk: tegra: remove non-existing pll_m_out1 clock Peter De Schrijver
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Peter De Schrijver @ 2017-02-23 10:44 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
The parent for afi is actually mselect, not clk_m.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-tegra-periph.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 19b00b7..c9e795b 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -815,7 +815,7 @@
GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
- GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0),
+ GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0),
GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 4/7] clk: tegra: remove non-existing pll_m_out1 clock
2017-02-23 10:44 [PATCH v2 0/7] Tegra210 clock bug fixes Peter De Schrijver
` (2 preceding siblings ...)
2017-02-23 10:44 ` [PATCH v2 3/7] clk: tegra: correct afi parent Peter De Schrijver
@ 2017-02-23 10:44 ` Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 5/7] clk: tegra: don't warn for PLL defaults unnecessarily Peter De Schrijver
` (4 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Peter De Schrijver @ 2017-02-23 10:44 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
This clock doesn't actually exist, so remove it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 7bda8ba..b7ef8a7 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2115,7 +2115,6 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
[tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
[tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
[tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
- [tegra_clk_pll_m_out1] = { .dt_id = TEGRA210_CLK_PLL_M_OUT1, .present = true },
[tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
[tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
[tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
@@ -2229,7 +2228,6 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
{ .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
{ .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
{ .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
- { .con_id = "pll_m_out1", .dt_id = TEGRA210_CLK_PLL_M_OUT1 },
{ .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
{ .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
{ .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
@@ -2404,9 +2402,6 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
clk_register_clkdev(clk, "pll_mb", NULL);
clks[TEGRA210_CLK_PLL_MB] = clk;
- clk_register_clkdev(clk, "pll_m_out1", NULL);
- clks[TEGRA210_CLK_PLL_M_OUT1] = clk;
-
/* PLLM_UD */
clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
CLK_SET_RATE_PARENT, 1, 1);
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 5/7] clk: tegra: don't warn for PLL defaults unnecessarily
2017-02-23 10:44 [PATCH v2 0/7] Tegra210 clock bug fixes Peter De Schrijver
` (3 preceding siblings ...)
2017-02-23 10:44 ` [PATCH v2 4/7] clk: tegra: remove non-existing pll_m_out1 clock Peter De Schrijver
@ 2017-02-23 10:44 ` Peter De Schrijver
2017-03-23 14:37 ` Jon Hunter
2017-03-27 11:02 ` Jon Hunter
2017-02-23 10:44 ` [PATCH v2 6/7] clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation Peter De Schrijver
` (3 subsequent siblings)
8 siblings, 2 replies; 14+ messages in thread
From: Peter De Schrijver @ 2017-02-23 10:44 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
If the PLL is on, only warn if the defaults are not yet set. Otherwise be
silent.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index b7ef8a7..fe698d2 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -502,7 +502,7 @@ static void tegra210_pllcx_set_defaults(const char *name,
pllcx->params->defaults_set = true;
if (readl_relaxed(clk_base + pllcx->params->base_reg) &
- PLL_ENABLE) {
+ PLL_ENABLE && !pllcx->params->defaults_set) {
/* PLL is ON: only check if defaults already set */
pllcx_check_defaults(pllcx->params);
pr_warn("%s already enabled. Postponing set full defaults\n",
@@ -608,7 +608,6 @@ static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
if (readl_relaxed(clk_base + plld->params->base_reg) &
PLL_ENABLE) {
- pr_warn("PLL_D already enabled. Postponing set full defaults\n");
/*
* PLL is ON: check if defaults already set, then set those
@@ -625,6 +624,9 @@ static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
_pll_misc_chk_default(clk_base, plld->params, 0, val,
~mask & PLLD_MISC0_WRITE_MASK);
+ if (!plld->params->defaults_set)
+ pr_warn("PLL_D already enabled. Postponing set full defaults\n");
+
/* Enable lock detect */
mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
@@ -896,7 +898,6 @@ static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
- pr_warn("PLL_X already enabled. Postponing set full defaults\n");
/*
* PLL is ON: check if defaults already set, then set those
@@ -904,6 +905,8 @@ static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
*/
pllx_check_defaults(pllx);
+ if (!pllx->params->defaults_set)
+ pr_warn("PLL_X already enabled. Postponing set full defaults\n");
/* Configure dyn ramp, disable lock override */
writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
@@ -948,7 +951,6 @@ static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
pllmb->params->defaults_set = true;
if (val & PLL_ENABLE) {
- pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
/*
* PLL is ON: check if defaults already set, then set those
@@ -959,6 +961,8 @@ static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
_pll_misc_chk_default(clk_base, pllmb->params, 0, val,
~mask & PLLMB_MISC1_WRITE_MASK);
+ if (!pllmb->params->defaults_set)
+ pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
/* Enable lock detect */
val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
val &= ~mask;
@@ -1008,13 +1012,14 @@ static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
pllp->params->defaults_set = true;
if (val & PLL_ENABLE) {
- pr_warn("PLL_P already enabled. Postponing set full defaults\n");
/*
* PLL is ON: check if defaults already set, then set those
* that can be updated in flight.
*/
pllp_check_defaults(pllp, true);
+ if (!pllp->params->defaults_set)
+ pr_warn("PLL_P already enabled. Postponing set full defaults\n");
/* Enable lock detect */
val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
@@ -1069,13 +1074,14 @@ static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu)
pllu->params->defaults_set = true;
if (val & PLL_ENABLE) {
- pr_warn("PLL_U already enabled. Postponing set full defaults\n");
/*
* PLL is ON: check if defaults already set, then set those
* that can be updated in flight.
*/
pllu_check_defaults(pllu, false);
+ if (!pllu->params->defaults_set)
+ pr_warn("PLL_U already enabled. Postponing set full defaults\n");
/* Enable lock detect */
val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[0]);
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 6/7] clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation
2017-02-23 10:44 [PATCH v2 0/7] Tegra210 clock bug fixes Peter De Schrijver
` (4 preceding siblings ...)
2017-02-23 10:44 ` [PATCH v2 5/7] clk: tegra: don't warn for PLL defaults unnecessarily Peter De Schrijver
@ 2017-02-23 10:44 ` Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 7/7] clk: tegra: fix type for m field Peter De Schrijver
` (2 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Peter De Schrijver @ 2017-02-23 10:44 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
Return the actually achieved rate in cfg->output_rate rather than just the
requested rate. This is important to make clk_round_rate return the correct
result.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index fe698d2..58d7f9c 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -1222,6 +1222,7 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
cfg->n = p_rate / cf;
cfg->sdm_data = 0;
+ cfg->output_rate = input_rate;
if (params->sdm_ctrl_reg) {
unsigned long rem = p_rate - cf * cfg->n;
/* If ssc is enabled SDM enabled as well, even for integer n */
@@ -1232,10 +1233,15 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
s -= PLL_SDM_COEFF / 2;
cfg->sdm_data = sdin_din_to_data(s);
}
+ cfg->output_rate *= cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 +
+ sdin_data_to_din(cfg->sdm_data);
+ cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;
+ } else {
+ cfg->output_rate *= cfg->n;
+ cfg->output_rate /= p * cfg->m;
}
cfg->input_rate = input_rate;
- cfg->output_rate = rate;
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 7/7] clk: tegra: fix type for m field
2017-02-23 10:44 [PATCH v2 0/7] Tegra210 clock bug fixes Peter De Schrijver
` (5 preceding siblings ...)
2017-02-23 10:44 ` [PATCH v2 6/7] clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation Peter De Schrijver
@ 2017-02-23 10:44 ` Peter De Schrijver
2017-02-27 18:28 ` [PATCH v2 0/7] Tegra210 clock bug fixes Mikko Perttunen
2017-03-20 12:59 ` Thierry Reding
8 siblings, 0 replies; 14+ messages in thread
From: Peter De Schrijver @ 2017-02-23 10:44 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
When used as part of fractional ndiv calculations, the current range is not
enough because the denominator of the fraction is multiplied with m.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 6ba82ec..a62ea73 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -116,7 +116,7 @@ struct tegra_clk_pll_freq_table {
unsigned long input_rate;
unsigned long output_rate;
u32 n;
- u16 m;
+ u32 m;
u8 p;
u8 cpcon;
u16 sdm_data;
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/7] Tegra210 clock bug fixes
2017-02-23 10:44 [PATCH v2 0/7] Tegra210 clock bug fixes Peter De Schrijver
` (6 preceding siblings ...)
2017-02-23 10:44 ` [PATCH v2 7/7] clk: tegra: fix type for m field Peter De Schrijver
@ 2017-02-27 18:28 ` Mikko Perttunen
2017-03-20 12:59 ` Thierry Reding
8 siblings, 0 replies; 14+ messages in thread
From: Mikko Perttunen @ 2017-02-27 18:28 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
Series,
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
On 02/23/2017 12:44 PM, Peter De Schrijver wrote:
> A number of bug fixes for the Tegra210 clock implementation.
>
> Changelog:
>
> v2: add better description for 'remove non-existing pll_m_out1 clock'
>
> Peter De Schrijver (7):
> clk: tegra: fix pll_a1 iddq register, add pll_a1
> clk: tegra: fix isp clock modelling
> clk: tegra: correct afi parent
> clk: tegra: remove non-existing pll_m_out1 clock
> clk: tegra: don't warn for PLL defaults unnecessarily
> clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation
> clk: tegra: fix type for m field
>
> drivers/clk/tegra/clk-id.h | 1 +
> drivers/clk/tegra/clk-tegra-periph.c | 13 +++++++++---
> drivers/clk/tegra/clk-tegra210.c | 35 ++++++++++++++++++++------------
> drivers/clk/tegra/clk.h | 2 +-
> include/dt-bindings/clock/tegra210-car.h | 4 ++--
> 5 files changed, 36 insertions(+), 19 deletions(-)
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/7] Tegra210 clock bug fixes
2017-02-23 10:44 [PATCH v2 0/7] Tegra210 clock bug fixes Peter De Schrijver
` (7 preceding siblings ...)
2017-02-27 18:28 ` [PATCH v2 0/7] Tegra210 clock bug fixes Mikko Perttunen
@ 2017-03-20 12:59 ` Thierry Reding
8 siblings, 0 replies; 14+ messages in thread
From: Thierry Reding @ 2017-03-20 12:59 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Stephen Warren, Alexandre Courbot, Rob Herring, Mark Rutland,
Rhyland Klein, linux-clk, linux-tegra, linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 1023 bytes --]
On Thu, Feb 23, 2017 at 12:44:37PM +0200, Peter De Schrijver wrote:
> A number of bug fixes for the Tegra210 clock implementation.
>
> Changelog:
>
> v2: add better description for 'remove non-existing pll_m_out1 clock'
>
> Peter De Schrijver (7):
> clk: tegra: fix pll_a1 iddq register, add pll_a1
> clk: tegra: fix isp clock modelling
> clk: tegra: correct afi parent
> clk: tegra: remove non-existing pll_m_out1 clock
> clk: tegra: don't warn for PLL defaults unnecessarily
> clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation
> clk: tegra: fix type for m field
>
> drivers/clk/tegra/clk-id.h | 1 +
> drivers/clk/tegra/clk-tegra-periph.c | 13 +++++++++---
> drivers/clk/tegra/clk-tegra210.c | 35 ++++++++++++++++++++------------
> drivers/clk/tegra/clk.h | 2 +-
> include/dt-bindings/clock/tegra210-car.h | 4 ++--
> 5 files changed, 36 insertions(+), 19 deletions(-)
Applied to for-4.12/clk, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/7] clk: tegra: don't warn for PLL defaults unnecessarily
2017-02-23 10:44 ` [PATCH v2 5/7] clk: tegra: don't warn for PLL defaults unnecessarily Peter De Schrijver
@ 2017-03-23 14:37 ` Jon Hunter
2017-03-24 9:25 ` Peter De Schrijver
2017-03-27 11:02 ` Jon Hunter
1 sibling, 1 reply; 14+ messages in thread
From: Jon Hunter @ 2017-03-23 14:37 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
Hi Peter,
On 23/02/17 10:44, Peter De Schrijver wrote:
> If the PLL is on, only warn if the defaults are not yet set. Otherwise be
> silent.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
This patch is breaking boot for Tegra210 Smaug on -next [0]. Reverting
this on top of -next allows the board to boot again. I have not had
chance to dig into this any further yet, but can unless you have some
thoughts.
Cheers
Jon
[0]
https://nvtb.github.io//linux-next/test_next-20170323/20170323021534/boot/tegra210-smaug/tegra210-smaug/defconfig_log.txt
--
nvpublic
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/7] clk: tegra: don't warn for PLL defaults unnecessarily
2017-03-23 14:37 ` Jon Hunter
@ 2017-03-24 9:25 ` Peter De Schrijver
2017-03-24 9:27 ` Jon Hunter
0 siblings, 1 reply; 14+ messages in thread
From: Peter De Schrijver @ 2017-03-24 9:25 UTC (permalink / raw)
To: Jon Hunter
Cc: Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Stephen Warren, Thierry Reding, Alexandre Courbot, Rob Herring,
Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
On Thu, Mar 23, 2017 at 02:37:23PM +0000, Jon Hunter wrote:
> Hi Peter,
>
> On 23/02/17 10:44, Peter De Schrijver wrote:
> > If the PLL is on, only warn if the defaults are not yet set. Otherwise be
> > silent.
> >
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>
> This patch is breaking boot for Tegra210 Smaug on -next [0]. Reverting
> this on top of -next allows the board to boot again. I have not had
> chance to dig into this any further yet, but can unless you have some
> thoughts.
My guess would be pllm. Maybe the bootloader on Smaug switches to pllm for
a higher emc frequency? On jetson cboot doesn't do that, so at least that
could be a difference.
Peter.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/7] clk: tegra: don't warn for PLL defaults unnecessarily
2017-03-24 9:25 ` Peter De Schrijver
@ 2017-03-24 9:27 ` Jon Hunter
0 siblings, 0 replies; 14+ messages in thread
From: Jon Hunter @ 2017-03-24 9:27 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Stephen Warren, Thierry Reding, Alexandre Courbot, Rob Herring,
Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
On 24/03/17 09:25, Peter De Schrijver wrote:
> On Thu, Mar 23, 2017 at 02:37:23PM +0000, Jon Hunter wrote:
>> Hi Peter,
>>
>> On 23/02/17 10:44, Peter De Schrijver wrote:
>>> If the PLL is on, only warn if the defaults are not yet set. Otherwise be
>>> silent.
>>>
>>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>
>> This patch is breaking boot for Tegra210 Smaug on -next [0]. Reverting
>> this on top of -next allows the board to boot again. I have not had
>> chance to dig into this any further yet, but can unless you have some
>> thoughts.
>
> My guess would be pllm. Maybe the bootloader on Smaug switches to pllm for
> a higher emc frequency? On jetson cboot doesn't do that, so at least that
> could be a difference.
Thanks. I will take a closer look at what is going on either today or
Monday and let you know what I find.
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/7] clk: tegra: don't warn for PLL defaults unnecessarily
2017-02-23 10:44 ` [PATCH v2 5/7] clk: tegra: don't warn for PLL defaults unnecessarily Peter De Schrijver
2017-03-23 14:37 ` Jon Hunter
@ 2017-03-27 11:02 ` Jon Hunter
1 sibling, 0 replies; 14+ messages in thread
From: Jon Hunter @ 2017-03-27 11:02 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
Hi Peter,
On 23/02/17 10:44, Peter De Schrijver wrote:
> If the PLL is on, only warn if the defaults are not yet set. Otherwise be
> silent.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index b7ef8a7..fe698d2 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -502,7 +502,7 @@ static void tegra210_pllcx_set_defaults(const char *name,
> pllcx->params->defaults_set = true;
>
> if (readl_relaxed(clk_base + pllcx->params->base_reg) &
> - PLL_ENABLE) {
> + PLL_ENABLE && !pllcx->params->defaults_set) {
> /* PLL is ON: only check if defaults already set */
> pllcx_check_defaults(pllcx->params);
> pr_warn("%s already enabled. Postponing set full defaults\n",
The above hunk is causing the Tegra210 Smaug boot to fail. Looking more
at the code, I believe that the above hunk is not correct, because
'defaults_set' is always true and this is now causing us to always reset
the PLL if in-use or not. I will send a patch to correct this.
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2017-03-27 11:05 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-23 10:44 [PATCH v2 0/7] Tegra210 clock bug fixes Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1 Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 2/7] clk: tegra: fix isp clock modelling Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 3/7] clk: tegra: correct afi parent Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 4/7] clk: tegra: remove non-existing pll_m_out1 clock Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 5/7] clk: tegra: don't warn for PLL defaults unnecessarily Peter De Schrijver
2017-03-23 14:37 ` Jon Hunter
2017-03-24 9:25 ` Peter De Schrijver
2017-03-24 9:27 ` Jon Hunter
2017-03-27 11:02 ` Jon Hunter
2017-02-23 10:44 ` [PATCH v2 6/7] clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation Peter De Schrijver
2017-02-23 10:44 ` [PATCH v2 7/7] clk: tegra: fix type for m field Peter De Schrijver
2017-02-27 18:28 ` [PATCH v2 0/7] Tegra210 clock bug fixes Mikko Perttunen
2017-03-20 12:59 ` Thierry Reding
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