From: Suzuki K Poulose <Suzuki.Poulose@arm.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Will Deacon <will.deacon@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <marc.zyngier@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
James Morse <james.morse@arm.com>,
Andre Przywara <andre.przywara@arm.com>
Subject: Re: [PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes
Date: Mon, 5 Sep 2016 11:24:02 +0100 [thread overview]
Message-ID: <d7277900-068a-98fc-4f52-4f619ba96cf8@arm.com> (raw)
In-Reply-To: <CAKv+Gu92Z=k0NXSL2UayuxWv-=wH1aJ3r-ByXxexWmz6sfE7zw@mail.gmail.com>
On 05/09/16 11:10, Ard Biesheuvel wrote:
> On 5 September 2016 at 10:58, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>> +/*
>> + * read_ctr - read CTR_EL0. If the system has mismatched
>> + * cache line sizes, provide the system wide safe value.
>> + */
>> + .macro read_ctr, reg
>> +alternative_if_not ARM64_MISMATCHED_CACHE_LINE_SIZE
>> + mrs \reg, ctr_el0 // read CTR
>> + nop
>> + nop
>> +alternative_else
>> + adr_l \reg, arm64_ftr_reg_ctrel0 // Read system wide safe CTR value
>> + ldr \reg, [\reg, #ARM64_FTR_SYSVAL] // from arm64_ftr_reg_ctrel0.sys_val
>
> You should be able to use
>
> ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
>
> here, and save one instruction.
I had given a thought about that and chose the above to account for a
rare chance of arm64_ftr_reg_ctrel0 spanning across a 4K boundary. But,
you are right, ldr_l could treat (arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL)
as the symbol address and still get the right offset.
Suzuki
prev parent reply other threads:[~2016-09-05 10:24 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-05 9:58 [PATCH v3 0/9] arm64: Work around for mismatched cache line size Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 1/9] arm64: Set the safe value for L1 icache policy Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 2/9] arm64: Use consistent naming for errata handling Suzuki K Poulose
2016-09-07 10:36 ` Andre Przywara
2016-09-05 9:58 ` [PATCH v3 3/9] arm64: Rearrange CPU errata workaround checks Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 4/9] arm64: alternative: Disallow patching instructions using literals Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 5/9] arm64: insn: Add helpers for adrp offsets Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 6/9] arm64: alternative: Add support for patching adrp instructions Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 7/9] arm64: Introduce raw_{d,i}cache_line_size Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 8/9] arm64: Refactor sysinstr exception handling Suzuki K Poulose
2016-09-07 8:44 ` Will Deacon
2016-09-07 11:29 ` Andre Przywara
2016-09-05 9:58 ` [PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes Suzuki K Poulose
2016-09-05 10:10 ` Ard Biesheuvel
2016-09-05 10:24 ` Suzuki K Poulose [this message]
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