From: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
To: bhelgaas@google.com, lorenzo.pieralisi@arm.com,
Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com,
adouglas@cadence.com, niklas.cassel@axis.com,
jesper.nilsson@axis.com
Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, gustavo.pimentel@synopsys.com
Subject: [RFC 04/10] PCI: dwc: MSI callbacks handler rework
Date: Tue, 10 Apr 2018 18:14:43 +0100 [thread overview]
Message-ID: <dbfe4f7dfd60f2760f728e43e5f38a68cea91032.1523379766.git.gustavo.pimentel@synopsys.com> (raw)
In-Reply-To: <cover.1523379766.git.gustavo.pimentel@synopsys.com>
In-Reply-To: <cover.1523379766.git.gustavo.pimentel@synopsys.com>
Adds in pci_epc_set_msi function a maximum number of 32 interrupts
validation.
Removes duplicate defines located on pcie-designware.h file. Uses now
the defines available on /include/uapi/linux/pci-regs.h file.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
drivers/pci/dwc/pcie-designware-ep.c | 46 +++++++++++++++++++++++-------------
drivers/pci/dwc/pcie-designware.h | 11 ---------
drivers/pci/endpoint/pci-epc-core.c | 3 ++-
3 files changed, 32 insertions(+), 28 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index 874d4c2..e352786 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -251,29 +251,38 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
{
- int val;
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (ep->cap_addr.msi_addr == 0)
+ return 0;
- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
- if (!(val & MSI_CAP_MSI_EN_MASK))
+ reg = ep->cap_addr.msi_addr + PCI_MSI_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ if (!(val & PCI_MSI_FLAGS_ENABLE))
return -EINVAL;
- val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
+ val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
+
return val;
}
-static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 encode_int)
+static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
{
- int val;
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (ep->cap_addr.msi_addr == 0)
+ return 0;
- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
- val &= ~MSI_CAP_MMC_MASK;
- val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
+ reg = ep->cap_addr.msi_addr + PCI_MSI_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ val &= ~PCI_MSI_FLAGS_QMASK;
+ val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
dw_pcie_dbi_ro_wr_en(pci);
- dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
+ dw_pcie_writew_dbi(pci, reg, val);
dw_pcie_dbi_ro_wr_dis(pci);
return 0;
@@ -372,21 +381,26 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct pci_epc *epc = ep->epc;
u16 msg_ctrl, msg_data;
- u32 msg_addr_lower, msg_addr_upper;
+ u32 msg_addr_lower, msg_addr_upper, reg;
u64 msg_addr;
bool has_upper;
int ret;
/* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
- msg_ctrl = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+ reg = ep->cap_addr.msi_addr + PCI_MSI_FLAGS;
+ msg_ctrl = dw_pcie_readw_dbi(pci, reg);
has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
- msg_addr_lower = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
+ reg = ep->cap_addr.msi_addr + PCI_MSI_ADDRESS_LO;
+ msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
if (has_upper) {
- msg_addr_upper = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
- msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);
+ reg = ep->cap_addr.msi_addr + PCI_MSI_ADDRESS_HI;
+ msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
+ reg = ep->cap_addr.msi_addr + PCI_MSI_DATA_64;
+ msg_data = dw_pcie_readw_dbi(pci, reg);
} else {
msg_addr_upper = 0;
- msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);
+ reg = ep->cap_addr.msi_addr + PCI_MSI_DATA_32;
+ msg_data = dw_pcie_readw_dbi(pci, reg);
}
msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 456fd94..2acf18b0 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -96,17 +96,6 @@
#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
((0x3 << 20) | ((region) << 9) | (0x1 << 8))
-#define MSI_MESSAGE_CONTROL 0x52
-#define MSI_CAP_MMC_SHIFT 1
-#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT)
-#define MSI_CAP_MME_SHIFT 4
-#define MSI_CAP_MSI_EN_MASK 0x1
-#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
-#define MSI_MESSAGE_ADDR_L32 0x54
-#define MSI_MESSAGE_ADDR_U32 0x58
-#define MSI_MESSAGE_DATA_32 0x58
-#define MSI_MESSAGE_DATA_64 0x5C
-
#define MAX_MSI_IRQS 256
#define MAX_MSI_IRQS_PER_CTRL 32
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 294a383..dbd17e4 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -201,7 +201,8 @@ int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
u8 encode_int;
unsigned long flags;
- if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
+ if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
+ interrupts > 32)
return -EINVAL;
if (!epc->ops->set_msi)
--
2.7.4
next prev parent reply other threads:[~2018-04-10 17:14 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-10 17:14 [RFC 00/10] Adds pcitest tool support for MSI-X Gustavo Pimentel
2018-04-10 17:14 ` [RFC 01/10] PCI: dwc: Add MSI-X callbacks handler Gustavo Pimentel
2018-04-16 9:29 ` Kishon Vijay Abraham I
2018-04-23 9:36 ` Gustavo Pimentel
2018-04-24 7:07 ` Kishon Vijay Abraham I
2018-04-24 9:36 ` Gustavo Pimentel
2018-04-24 11:24 ` Kishon Vijay Abraham I
2018-04-26 15:30 ` Gustavo Pimentel
2018-04-24 14:05 ` Alan Douglas
2018-04-24 9:15 ` Alan Douglas
2018-04-24 11:43 ` Gustavo Pimentel
2018-05-10 10:40 ` Gustavo Pimentel
2018-04-10 17:14 ` [RFC 02/10] PCI: cadence: Update cdns_pcie_ep_raise_irq function signature Gustavo Pimentel
2018-04-13 16:05 ` Alan Douglas
2018-04-10 17:14 ` [RFC 03/10] PCI: endpoint: Add MSI-X interfaces Gustavo Pimentel
2018-04-17 10:24 ` Kishon Vijay Abraham I
2018-04-17 15:51 ` Gustavo Pimentel
2018-04-10 17:14 ` Gustavo Pimentel [this message]
2018-04-10 17:14 ` [RFC 05/10] PCI: dwc: Add legacy interrupt callback handler Gustavo Pimentel
2018-04-10 17:14 ` [RFC 06/10] misc: pci_endpoint_test: Add MSI-X support Gustavo Pimentel
2018-04-17 10:33 ` Kishon Vijay Abraham I
2018-04-17 17:38 ` Gustavo Pimentel
2018-04-24 7:19 ` Kishon Vijay Abraham I
2018-04-24 10:57 ` Gustavo Pimentel
2018-04-24 11:43 ` Kishon Vijay Abraham I
2018-04-26 15:36 ` Gustavo Pimentel
2018-04-24 6:59 ` Alan Douglas
2018-04-24 11:11 ` Gustavo Pimentel
2018-04-10 17:14 ` [RFC 07/10] misc: pci_endpoint_test: Replace lower into upper case characters Gustavo Pimentel
2018-04-10 17:14 ` [RFC 08/10] PCI: endpoint: functions/pci-epf-test: Add MSI-X support Gustavo Pimentel
2018-04-10 17:14 ` [RFC 09/10] PCI: endpoint: functions/pci-epf-test: Replace lower into upper case characters Gustavo Pimentel
2018-04-10 17:14 ` [RFC 10/10] tools: PCI: Add MSI-X support Gustavo Pimentel
2018-04-24 9:57 ` Alan Douglas
2018-04-24 17:18 ` Gustavo Pimentel
2018-04-24 6:48 ` [RFC 00/10] Adds pcitest tool support for MSI-X Alan Douglas
2018-04-24 8:49 ` Gustavo Pimentel
2018-04-24 9:28 ` Alan Douglas
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