* [PATCH 0/2] Add GPIO level-sensitive interrupt support @ 2020-02-10 13:48 Alexandre Torgue 2020-02-10 13:49 ` [PATCH 1/2] irqchip/stm32: Add irq retrigger support Alexandre Torgue 2020-02-10 13:49 ` [PATCH 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip Alexandre Torgue 0 siblings, 2 replies; 9+ messages in thread From: Alexandre Torgue @ 2020-02-10 13:48 UTC (permalink / raw) To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Linus Walleij Cc: linux-arm-kernel, linux-kernel, linux-gpio, marex This series adds the possibility to handle gpio interrupts on level. GPIO hardware block is directly linked to EXTI block but EXTI handles external interrupts only on edge. To be able to handle GPIO interrupt on level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip) is retriggered following interrupt type and gpio line value. In exti irq chip, retrigger ops function is added. Regards Alex Alexandre Torgue (2): irqchip/stm32: Add irq retrigger support pinctrl: stm32: Add level interrupt support to gpio irq chip drivers/irqchip/irq-stm32-exti.c | 14 +++++++- drivers/pinctrl/stm32/pinctrl-stm32.c | 47 +++++++++++++++++++++++++-- 2 files changed, 58 insertions(+), 3 deletions(-) -- 2.17.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] irqchip/stm32: Add irq retrigger support 2020-02-10 13:48 [PATCH 0/2] Add GPIO level-sensitive interrupt support Alexandre Torgue @ 2020-02-10 13:49 ` Alexandre Torgue 2020-02-10 13:49 ` [PATCH 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip Alexandre Torgue 1 sibling, 0 replies; 9+ messages in thread From: Alexandre Torgue @ 2020-02-10 13:49 UTC (permalink / raw) To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Linus Walleij Cc: linux-arm-kernel, linux-kernel, linux-gpio, marex This commit introduces retrigger support for stm32_ext_h chip. It consists to rise the GIC interrupt mapped to an EXTI line. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index e00f2fa27f00..c971d115edb4 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -604,12 +604,24 @@ static void stm32_exti_h_syscore_deinit(void) unregister_syscore_ops(&stm32_exti_h_syscore_ops); } +static int stm32_exti_h_retrigger(struct irq_data *d) +{ + struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); + const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; + void __iomem *base = chip_data->host_data->base; + u32 mask = BIT(d->hwirq % IRQS_PER_BANK); + + writel_relaxed(mask, base + stm32_bank->swier_ofst); + + return irq_chip_retrigger_hierarchy(d); +} + static struct irq_chip stm32_exti_h_chip = { .name = "stm32-exti-h", .irq_eoi = stm32_exti_h_eoi, .irq_mask = stm32_exti_h_mask, .irq_unmask = stm32_exti_h_unmask, - .irq_retrigger = irq_chip_retrigger_hierarchy, + .irq_retrigger = stm32_exti_h_retrigger, .irq_set_type = stm32_exti_h_set_type, .irq_set_wake = stm32_exti_h_set_wake, .flags = IRQCHIP_MASK_ON_SUSPEND, -- 2.17.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip 2020-02-10 13:48 [PATCH 0/2] Add GPIO level-sensitive interrupt support Alexandre Torgue 2020-02-10 13:49 ` [PATCH 1/2] irqchip/stm32: Add irq retrigger support Alexandre Torgue @ 2020-02-10 13:49 ` Alexandre Torgue 2020-02-10 18:39 ` Marek Vasut 1 sibling, 1 reply; 9+ messages in thread From: Alexandre Torgue @ 2020-02-10 13:49 UTC (permalink / raw) To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Linus Walleij Cc: linux-arm-kernel, linux-kernel, linux-gpio, marex This patch adds level interrupt support to gpio irq chip. GPIO hardware block is directly linked to EXTI block but EXTI handles external interrupts only on edge. To be able to handle GPIO interrupt on level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip) is retriggered following interrupt type and gpio line value. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 2d5e0435af0a..04e1b062c20e 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -89,6 +89,7 @@ struct stm32_gpio_bank { struct pinctrl_gpio_range range; struct fwnode_handle *fwnode; struct irq_domain *domain; + u32 irq_type[STM32_GPIO_PINS_PER_BANK]; u32 bank_nr; u32 bank_ioport_nr; u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; @@ -303,6 +304,48 @@ static const struct gpio_chip stm32_gpio_template = { .get_direction = stm32_gpio_get_direction, }; +void stm32_gpio_irq_eoi(struct irq_data *d) +{ + struct stm32_gpio_bank *bank = d->domain->host_data; + int line; + + irq_chip_eoi_parent(d); + + /* If level interrupt type then retrig */ + line = stm32_gpio_get(&bank->gpio_chip, d->hwirq); + if ((line == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || + (line == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) + irq_chip_retrigger_hierarchy(d); +}; + +static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) +{ + struct stm32_gpio_bank *bank = d->domain->host_data; + u32 parent_type; + + bank->irq_type[d->hwirq] = type; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_EDGE_BOTH: + parent_type = type; + break; + case IRQ_TYPE_LEVEL_HIGH: + parent_type = IRQ_TYPE_EDGE_RISING; + break; + case IRQ_TYPE_LEVEL_LOW: + parent_type = IRQ_TYPE_EDGE_FALLING; + break; + default: + return -EINVAL; + } + + irq_chip_set_type_parent(d, parent_type); + + return 0; +}; + static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) { struct stm32_gpio_bank *bank = irq_data->domain->host_data; @@ -332,11 +375,11 @@ static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) static struct irq_chip stm32_gpio_irq_chip = { .name = "stm32gpio", - .irq_eoi = irq_chip_eoi_parent, + .irq_eoi = stm32_gpio_irq_eoi, .irq_ack = irq_chip_ack_parent, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, - .irq_set_type = irq_chip_set_type_parent, + .irq_set_type = stm32_gpio_set_type, .irq_set_wake = irq_chip_set_wake_parent, .irq_request_resources = stm32_gpio_irq_request_resources, .irq_release_resources = stm32_gpio_irq_release_resources, -- 2.17.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip 2020-02-10 13:49 ` [PATCH 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip Alexandre Torgue @ 2020-02-10 18:39 ` Marek Vasut 2020-02-11 10:08 ` Alexandre Torgue 0 siblings, 1 reply; 9+ messages in thread From: Marek Vasut @ 2020-02-10 18:39 UTC (permalink / raw) To: Alexandre Torgue, Thomas Gleixner, Jason Cooper, Marc Zyngier, Linus Walleij Cc: linux-arm-kernel, linux-kernel, linux-gpio On 2/10/20 2:49 PM, Alexandre Torgue wrote: > This patch adds level interrupt support to gpio irq chip. > > GPIO hardware block is directly linked to EXTI block but EXTI handles > external interrupts only on edge. To be able to handle GPIO interrupt on > level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip) > is retriggered following interrupt type and gpio line value. > > Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> > > diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c > index 2d5e0435af0a..04e1b062c20e 100644 > --- a/drivers/pinctrl/stm32/pinctrl-stm32.c > +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c > @@ -89,6 +89,7 @@ struct stm32_gpio_bank { > struct pinctrl_gpio_range range; > struct fwnode_handle *fwnode; > struct irq_domain *domain; > + u32 irq_type[STM32_GPIO_PINS_PER_BANK]; You might want reverse xmas tree order here. > u32 bank_nr; > u32 bank_ioport_nr; > u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; > @@ -303,6 +304,48 @@ static const struct gpio_chip stm32_gpio_template = { > .get_direction = stm32_gpio_get_direction, > }; > > +void stm32_gpio_irq_eoi(struct irq_data *d) > +{ > + struct stm32_gpio_bank *bank = d->domain->host_data; > + int line; > + > + irq_chip_eoi_parent(d); > + > + /* If level interrupt type then retrig */ > + line = stm32_gpio_get(&bank->gpio_chip, d->hwirq); > + if ((line == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || > + (line == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) > + irq_chip_retrigger_hierarchy(d); > +}; > + > +static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) > +{ > + struct stm32_gpio_bank *bank = d->domain->host_data; > + u32 parent_type; > + > + bank->irq_type[d->hwirq] = type; > + > + switch (type) { > + case IRQ_TYPE_EDGE_RISING: > + case IRQ_TYPE_EDGE_FALLING: > + case IRQ_TYPE_EDGE_BOTH: > + parent_type = type; > + break; > + case IRQ_TYPE_LEVEL_HIGH: > + parent_type = IRQ_TYPE_EDGE_RISING; > + break; > + case IRQ_TYPE_LEVEL_LOW: > + parent_type = IRQ_TYPE_EDGE_FALLING; > + break; > + default: > + return -EINVAL; > + } > + > + irq_chip_set_type_parent(d, parent_type); irq_chip_set_type_parent() returns error code, shouldn't that be handled? Otherwise, tested on STM32MP1 with KSZ8851-16MLL NIC. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip 2020-02-10 18:39 ` Marek Vasut @ 2020-02-11 10:08 ` Alexandre Torgue 2020-02-19 11:19 ` Marc Zyngier 0 siblings, 1 reply; 9+ messages in thread From: Alexandre Torgue @ 2020-02-11 10:08 UTC (permalink / raw) To: Marek Vasut, Thomas Gleixner, Jason Cooper, Marc Zyngier, Linus Walleij Cc: linux-arm-kernel, linux-kernel, linux-gpio Hi Marek On 2/10/20 7:39 PM, Marek Vasut wrote: > On 2/10/20 2:49 PM, Alexandre Torgue wrote: >> This patch adds level interrupt support to gpio irq chip. >> >> GPIO hardware block is directly linked to EXTI block but EXTI handles >> external interrupts only on edge. To be able to handle GPIO interrupt on >> level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip) >> is retriggered following interrupt type and gpio line value. >> >> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> >> >> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c >> index 2d5e0435af0a..04e1b062c20e 100644 >> --- a/drivers/pinctrl/stm32/pinctrl-stm32.c >> +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c >> @@ -89,6 +89,7 @@ struct stm32_gpio_bank { >> struct pinctrl_gpio_range range; >> struct fwnode_handle *fwnode; >> struct irq_domain *domain; >> + u32 irq_type[STM32_GPIO_PINS_PER_BANK]; > > You might want reverse xmas tree order here. I agree > >> u32 bank_nr; >> u32 bank_ioport_nr; >> u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; >> @@ -303,6 +304,48 @@ static const struct gpio_chip stm32_gpio_template = { >> .get_direction = stm32_gpio_get_direction, >> }; >> >> +void stm32_gpio_irq_eoi(struct irq_data *d) >> +{ >> + struct stm32_gpio_bank *bank = d->domain->host_data; >> + int line; >> + >> + irq_chip_eoi_parent(d); >> + >> + /* If level interrupt type then retrig */ >> + line = stm32_gpio_get(&bank->gpio_chip, d->hwirq); >> + if ((line == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || >> + (line == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) >> + irq_chip_retrigger_hierarchy(d); >> +}; >> + >> +static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) >> +{ >> + struct stm32_gpio_bank *bank = d->domain->host_data; >> + u32 parent_type; >> + >> + bank->irq_type[d->hwirq] = type; >> + >> + switch (type) { >> + case IRQ_TYPE_EDGE_RISING: >> + case IRQ_TYPE_EDGE_FALLING: >> + case IRQ_TYPE_EDGE_BOTH: >> + parent_type = type; >> + break; >> + case IRQ_TYPE_LEVEL_HIGH: >> + parent_type = IRQ_TYPE_EDGE_RISING; >> + break; >> + case IRQ_TYPE_LEVEL_LOW: >> + parent_type = IRQ_TYPE_EDGE_FALLING; >> + break; >> + default: >> + return -EINVAL; >> + } >> + >> + irq_chip_set_type_parent(d, parent_type); > > irq_chip_set_type_parent() returns error code, shouldn't that be handled? Yes. It'll be fixed in v2. > > Otherwise, tested on STM32MP1 with KSZ8851-16MLL NIC. Thanks ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip 2020-02-11 10:08 ` Alexandre Torgue @ 2020-02-19 11:19 ` Marc Zyngier 2020-02-19 11:30 ` Alexandre Torgue 0 siblings, 1 reply; 9+ messages in thread From: Marc Zyngier @ 2020-02-19 11:19 UTC (permalink / raw) To: Alexandre Torgue Cc: Marek Vasut, Thomas Gleixner, Jason Cooper, Marc Zyngier, Linus Walleij, linux-arm-kernel, linux-kernel, linux-gpio, linux-kernel-owner On 2020-02-11 10:08, Alexandre Torgue wrote: [...] > Yes. It'll be fixed in v2. And when you do that, please use my official email address (my @arm.com address goes to my ex manager, and I don't think he cares much about this). M. -- Jazz is not dead. It just smells funny... ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip 2020-02-19 11:19 ` Marc Zyngier @ 2020-02-19 11:30 ` Alexandre Torgue 2020-02-19 11:39 ` Marc Zyngier 0 siblings, 1 reply; 9+ messages in thread From: Alexandre Torgue @ 2020-02-19 11:30 UTC (permalink / raw) To: Marc Zyngier Cc: Marek Vasut, Thomas Gleixner, Jason Cooper, Marc Zyngier, Linus Walleij, linux-arm-kernel, linux-kernel, linux-gpio, linux-kernel-owner On 2/19/20 12:19 PM, Marc Zyngier wrote: > On 2020-02-11 10:08, Alexandre Torgue wrote: > > [...] > >> Yes. It'll be fixed in v2. > > And when you do that, please use my official email address (my @arm.com > address goes to my ex manager, and I don't think he cares much about this). Ok I update my script. Alex > > M. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip 2020-02-19 11:30 ` Alexandre Torgue @ 2020-02-19 11:39 ` Marc Zyngier 2020-02-19 11:48 ` Alexandre Torgue 0 siblings, 1 reply; 9+ messages in thread From: Marc Zyngier @ 2020-02-19 11:39 UTC (permalink / raw) To: Alexandre Torgue Cc: Marek Vasut, Thomas Gleixner, Jason Cooper, Marc Zyngier, Linus Walleij, linux-arm-kernel, linux-kernel, linux-gpio, linux-kernel-owner On 2020-02-19 11:30, Alexandre Torgue wrote: > On 2/19/20 12:19 PM, Marc Zyngier wrote: >> On 2020-02-11 10:08, Alexandre Torgue wrote: >> >> [...] >> >>> Yes. It'll be fixed in v2. >> >> And when you do that, please use my official email address (my >> @arm.com >> address goes to my ex manager, and I don't think he cares much about >> this). > > Ok I update my script. Surely your script is a wrapper around scripts/get_maintainer.pl, right? M. -- Jazz is not dead. It just smells funny... ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip 2020-02-19 11:39 ` Marc Zyngier @ 2020-02-19 11:48 ` Alexandre Torgue 0 siblings, 0 replies; 9+ messages in thread From: Alexandre Torgue @ 2020-02-19 11:48 UTC (permalink / raw) To: Marc Zyngier Cc: Marek Vasut, Thomas Gleixner, Jason Cooper, Marc Zyngier, Linus Walleij, linux-arm-kernel, linux-kernel, linux-gpio, linux-kernel-owner On 2/19/20 12:39 PM, Marc Zyngier wrote: > On 2020-02-19 11:30, Alexandre Torgue wrote: >> On 2/19/20 12:19 PM, Marc Zyngier wrote: >>> On 2020-02-11 10:08, Alexandre Torgue wrote: >>> >>> [...] >>> >>>> Yes. It'll be fixed in v2. >>> >>> And when you do that, please use my official email address (my @arm.com >>> address goes to my ex manager, and I don't think he cares much about >>> this). >> >> Ok I update my script. > > Surely your script is a wrapper around scripts/get_maintainer.pl, right? No. it's an old script which create groups (hard coded) to be used for git send-mail. But yes, a good improvement would be to use get_maintainer.pl. > > M. ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-02-19 11:48 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-02-10 13:48 [PATCH 0/2] Add GPIO level-sensitive interrupt support Alexandre Torgue 2020-02-10 13:49 ` [PATCH 1/2] irqchip/stm32: Add irq retrigger support Alexandre Torgue 2020-02-10 13:49 ` [PATCH 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip Alexandre Torgue 2020-02-10 18:39 ` Marek Vasut 2020-02-11 10:08 ` Alexandre Torgue 2020-02-19 11:19 ` Marc Zyngier 2020-02-19 11:30 ` Alexandre Torgue 2020-02-19 11:39 ` Marc Zyngier 2020-02-19 11:48 ` Alexandre Torgue
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