[PATCH 0/3] add support of SCPSYS power domain for MediaTek MT7622

[PATCH 0/3] add support of SCPSYS power domain for MediaTek MT7622

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

There are four power domains on MediaTek MT7622 SoC which are respectively
ETHSYS for Ethernet including extra embedded switch, HIF0SYS for PCI-E and
SATA, HIF1SYS for USB and WBSYS for WIFI and Bluetooth.

Those functions could be selectively powered gated when the corresponding
function is no longer to use in order to reach more minimal power
dissipation through the patch series introduced here.

Chen Zhong (2):
  soc: mediatek: add header files required for MT7622 SCPSYS dt-binding
  soc: mediatek: add SCPSYS power domain driver for MediaTek MT7622 SoC

Sean Wang (1):
  dt-bindings: soc: update the binding document for SCPSYS on MediaTek
    MT7622 SoC

 .../devicetree/bindings/soc/mediatek/scpsys.txt    |  3 +
 drivers/soc/mediatek/mtk-scpsys.c                  | 76 ++++++++++++++++++++++
 include/dt-bindings/power/mt7622-power.h           | 22 +++++++
 include/linux/soc/mediatek/infracfg.h              |  8 ++-
 4 files changed, 108 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/power/mt7622-power.h

-- 
2.7.4

[PATCH 1/3] dt-bindings: soc: update the binding document for SCPSYS on MediaTek MT7622 SoC

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

Update the binding document for enabling SCPSYS on MediaTek MT7622 SoC.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
---
 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index b1d165b..40056f7 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -12,11 +12,13 @@ power/power_domain.txt. It provides the power domains defined in
 - include/dt-bindings/power/mt8173-power.h
 - include/dt-bindings/power/mt6797-power.h
 - include/dt-bindings/power/mt2701-power.h
+- include/dt-bindings/power/mt7622-power.h
 
 Required properties:
 - compatible: Should be one of:
 	- "mediatek,mt2701-scpsys"
 	- "mediatek,mt6797-scpsys"
+	- "mediatek,mt7622-scpsys"
 	- "mediatek,mt8173-scpsys"
 - #power-domain-cells: Must be 1
 - reg: Address range of the SCPSYS unit
@@ -26,6 +28,7 @@ Required properties:
                       enabled before enabling certain power domains.
 	Required clocks for MT2701: "mm", "mfg", "ethif"
 	Required clocks for MT6797: "mm", "mfg", "vdec"
+	Required clocks for MT7622: "hif_sel"
 	Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
 
 Optional properties:
-- 
2.7.4

[PATCH 2/3] soc: mediatek: add header files required for MT7622 SCPSYS dt-binding

[sean.wang]

From: Chen Zhong <chen.zhong@mediatek.com>

Add relevant header files required for dt-bindings of SCPSYS power domain
control for all subsystems found on MT7622 SoC.

Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
 include/dt-bindings/power/mt7622-power.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 include/dt-bindings/power/mt7622-power.h

diff --git a/include/dt-bindings/power/mt7622-power.h b/include/dt-bindings/power/mt7622-power.h
new file mode 100644
index 0000000..1b63926
--- /dev/null
+++ b/include/dt-bindings/power/mt7622-power.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT7622_POWER_H
+#define _DT_BINDINGS_POWER_MT7622_POWER_H
+
+#define MT7622_POWER_DOMAIN_ETHSYS	0
+#define MT7622_POWER_DOMAIN_HIF0	1
+#define MT7622_POWER_DOMAIN_HIF1	2
+#define MT7622_POWER_DOMAIN_WB		3
+
+#endif /* _DT_BINDINGS_POWER_MT7622_POWER_H */
-- 
2.7.4

[PATCH 3/3] soc: mediatek: add SCPSYS power domain driver for MediaTek MT7622 SoC

[sean.wang]

From: Chen Zhong <chen.zhong@mediatek.com>

Add SCPSYS power domain driver for MT7622 SoC having four power domains
which are respectively ETHSYS for Ethernet including embedded switch,
WBSYS for WIFI and Bluetooth, HIF0SYS for PCI-E and SATA, and HIF1SYS for
USB. Those functions could be selectively powered gated when the
corresponding function is no longer to use in order to reach more minimal
power dissipation.

Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
 drivers/soc/mediatek/mtk-scpsys.c     | 76 +++++++++++++++++++++++++++++++++++
 include/linux/soc/mediatek/infracfg.h |  8 +++-
 2 files changed, 83 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index beb7916..8a0ca02 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -21,6 +21,7 @@
 #include <linux/soc/mediatek/infracfg.h>
 
 #include <dt-bindings/power/mt2701-power.h>
+#include <dt-bindings/power/mt7622-power.h>
 #include <dt-bindings/power/mt8173-power.h>
 
 #define SPM_VDE_PWR_CON			0x0210
@@ -38,6 +39,11 @@
 #define SPM_MFG_2D_PWR_CON		0x02c0
 #define SPM_MFG_ASYNC_PWR_CON		0x02c4
 #define SPM_USB_PWR_CON			0x02cc
+#define SPM_ETHSYS_PWR_CON		0x02e0	/* MT7622 */
+#define SPM_HIF0_PWR_CON		0x02e4	/* MT7622 */
+#define SPM_HIF1_PWR_CON		0x02e8	/* MT7622 */
+#define SPM_WB_PWR_CON			0x02ec	/* MT7622 */
+
 
 #define SPM_PWR_STATUS			0x060c
 #define SPM_PWR_STATUS_2ND		0x0610
@@ -63,6 +69,10 @@
 #define PWR_STATUS_MFG_ASYNC		BIT(23)
 #define PWR_STATUS_AUDIO		BIT(24)
 #define PWR_STATUS_USB			BIT(25)
+#define PWR_STATUS_ETHSYS		BIT(24)	/* MT7622 */
+#define PWR_STATUS_HIF0			BIT(25)	/* MT7622 */
+#define PWR_STATUS_HIF1			BIT(26)	/* MT7622 */
+#define PWR_STATUS_WB			BIT(27)	/* MT7622 */
 
 enum clk_id {
 	CLK_NONE,
@@ -71,6 +81,7 @@ enum clk_id {
 	CLK_VENC,
 	CLK_VENC_LT,
 	CLK_ETHIF,
+	CLK_HIFSEL,
 	CLK_MAX,
 };
 
@@ -81,6 +92,7 @@ static const char * const clk_names[] = {
 	"venc",
 	"venc_lt",
 	"ethif",
+	"hif_sel",
 	NULL,
 };
 
@@ -567,6 +579,67 @@ static int __init scpsys_probe_mt2701(struct platform_device *pdev)
 }
 
 /*
+ * MT7622 power domain support
+ */
+static const struct scp_domain_data scp_domain_data_mt7622[] = {
+	[MT7622_POWER_DOMAIN_ETHSYS] = {
+		.name = "ethsys",
+		.sta_mask = PWR_STATUS_ETHSYS,
+		.ctl_offs = SPM_ETHSYS_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.clk_id = {CLK_NONE},
+		.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
+		.active_wakeup = true,
+	},
+	[MT7622_POWER_DOMAIN_HIF0] = {
+		.name = "hif0",
+		.sta_mask = PWR_STATUS_HIF0,
+		.ctl_offs = SPM_HIF0_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.clk_id = {CLK_HIFSEL},
+		.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
+		.active_wakeup = true,
+	},
+	[MT7622_POWER_DOMAIN_HIF1] = {
+		.name = "hif1",
+		.sta_mask = PWR_STATUS_HIF1,
+		.ctl_offs = SPM_HIF1_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.clk_id = {CLK_HIFSEL},
+		.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
+		.active_wakeup = true,
+	},
+	[MT7622_POWER_DOMAIN_WB] = {
+		.name = "wb",
+		.sta_mask = PWR_STATUS_WB,
+		.ctl_offs = SPM_WB_PWR_CON,
+		.sram_pdn_bits = 0,
+		.sram_pdn_ack_bits = 0,
+		.clk_id = {CLK_NONE},
+		.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
+		.active_wakeup = true,
+	},
+};
+
+#define NUM_DOMAINS_MT7622	ARRAY_SIZE(scp_domain_data_mt7622)
+
+static int __init scpsys_probe_mt7622(struct platform_device *pdev)
+{
+	struct scp *scp;
+
+	scp = init_scp(pdev, scp_domain_data_mt7622, NUM_DOMAINS_MT7622);
+	if (IS_ERR(scp))
+		return PTR_ERR(scp);
+
+	mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT7622);
+
+	return 0;
+}
+
+/*
  * MT8173 power domain support
  */
 
@@ -698,6 +771,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
 		.compatible = "mediatek,mt2701-scpsys",
 		.data = scpsys_probe_mt2701,
 	}, {
+		.compatible = "mediatek,mt7622-scpsys",
+		.data = scpsys_probe_mt7622,
+	}, {
 		.compatible = "mediatek,mt8173-scpsys",
 		.data = scpsys_probe_mt8173,
 	}, {
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
index a5714e9..c1e5062 100644
--- a/include/linux/soc/mediatek/infracfg.h
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -20,7 +20,13 @@
 #define MT8173_TOP_AXI_PROT_EN_MFG_M1		BIT(22)
 #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT	BIT(23)
 
+#define MT7622_TOP_AXI_PROT_EN_ETHSYS		(BIT(3) | BIT(17))
+#define MT7622_TOP_AXI_PROT_EN_HIF0		(BIT(24) | BIT(25))
+#define MT7622_TOP_AXI_PROT_EN_HIF1		(BIT(26) | BIT(27) | \
+						 BIT(28))
+#define MT7622_TOP_AXI_PROT_EN_WB		(BIT(2) | BIT(6) | \
+						 BIT(7) | BIT(8))
+
 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask);
 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask);
-
 #endif /* __SOC_MEDIATEK_INFRACFG_H */
-- 
2.7.4

Re: [PATCH 1/3] dt-bindings: soc: update the binding document for SCPSYS on MediaTek MT7622 SoC

[Rob Herring]

On Fri, Jul 21, 2017 at 11:57:12AM +0800, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> Update the binding document for enabling SCPSYS on MediaTek MT7622 SoC.
> 
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
> ---
>  Documentation/devicetree/bindings/soc/mediatek/scpsys.txt | 3 +++
>  1 file changed, 3 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 3/3] soc: mediatek: add SCPSYS power domain driver for MediaTek MT7622 SoC

[Matthias Brugger]

On 07/21/2017 05:57 AM, sean.wang@mediatek.com wrote:
> From: Chen Zhong <chen.zhong@mediatek.com>
> 
> Add SCPSYS power domain driver for MT7622 SoC having four power domains
> which are respectively ETHSYS for Ethernet including embedded switch,
> WBSYS for WIFI and Bluetooth, HIF0SYS for PCI-E and SATA, and HIF1SYS for
> USB. Those functions could be selectively powered gated when the
> corresponding function is no longer to use in order to reach more minimal
> power dissipation.
> 
> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
>   drivers/soc/mediatek/mtk-scpsys.c     | 76 +++++++++++++++++++++++++++++++++++
>   include/linux/soc/mediatek/infracfg.h |  8 +++-
>   2 files changed, 83 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index beb7916..8a0ca02 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -21,6 +21,7 @@
>   #include <linux/soc/mediatek/infracfg.h>
>   
>   #include <dt-bindings/power/mt2701-power.h>
> +#include <dt-bindings/power/mt7622-power.h>
>   #include <dt-bindings/power/mt8173-power.h>
>   
>   #define SPM_VDE_PWR_CON			0x0210
> @@ -38,6 +39,11 @@
>   #define SPM_MFG_2D_PWR_CON		0x02c0
>   #define SPM_MFG_ASYNC_PWR_CON		0x02c4
>   #define SPM_USB_PWR_CON			0x02cc
> +#define SPM_ETHSYS_PWR_CON		0x02e0	/* MT7622 */
> +#define SPM_HIF0_PWR_CON		0x02e4	/* MT7622 */
> +#define SPM_HIF1_PWR_CON		0x02e8	/* MT7622 */
> +#define SPM_WB_PWR_CON			0x02ec	/* MT7622 */
> +
>   
>   #define SPM_PWR_STATUS			0x060c
>   #define SPM_PWR_STATUS_2ND		0x0610
> @@ -63,6 +69,10 @@
>   #define PWR_STATUS_MFG_ASYNC		BIT(23)
>   #define PWR_STATUS_AUDIO		BIT(24)
>   #define PWR_STATUS_USB			BIT(25)
> +#define PWR_STATUS_ETHSYS		BIT(24)	/* MT7622 */
> +#define PWR_STATUS_HIF0			BIT(25)	/* MT7622 */
> +#define PWR_STATUS_HIF1			BIT(26)	/* MT7622 */
> +#define PWR_STATUS_WB			BIT(27)	/* MT7622 */
>   
>   enum clk_id {
>   	CLK_NONE,
> @@ -71,6 +81,7 @@ enum clk_id {
>   	CLK_VENC,
>   	CLK_VENC_LT,
>   	CLK_ETHIF,
> +	CLK_HIFSEL,
>   	CLK_MAX,
>   };
>   
> @@ -81,6 +92,7 @@ static const char * const clk_names[] = {
>   	"venc",
>   	"venc_lt",
>   	"ethif",
> +	"hif_sel",
>   	NULL,
>   };
>   
> @@ -567,6 +579,67 @@ static int __init scpsys_probe_mt2701(struct platform_device *pdev)
>   }
>   
>   /*
> + * MT7622 power domain support
> + */
> +static const struct scp_domain_data scp_domain_data_mt7622[] = {
> +	[MT7622_POWER_DOMAIN_ETHSYS] = {
> +		.name = "ethsys",
> +		.sta_mask = PWR_STATUS_ETHSYS,
> +		.ctl_offs = SPM_ETHSYS_PWR_CON,
> +		.sram_pdn_bits = GENMASK(11, 8),
> +		.sram_pdn_ack_bits = GENMASK(15, 12),
> +		.clk_id = {CLK_NONE},
> +		.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
> +		.active_wakeup = true,
> +	},
> +	[MT7622_POWER_DOMAIN_HIF0] = {
> +		.name = "hif0",
> +		.sta_mask = PWR_STATUS_HIF0,
> +		.ctl_offs = SPM_HIF0_PWR_CON,
> +		.sram_pdn_bits = GENMASK(11, 8),
> +		.sram_pdn_ack_bits = GENMASK(15, 12),
> +		.clk_id = {CLK_HIFSEL},
> +		.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
> +		.active_wakeup = true,
> +	},
> +	[MT7622_POWER_DOMAIN_HIF1] = {
> +		.name = "hif1",
> +		.sta_mask = PWR_STATUS_HIF1,
> +		.ctl_offs = SPM_HIF1_PWR_CON,
> +		.sram_pdn_bits = GENMASK(11, 8),
> +		.sram_pdn_ack_bits = GENMASK(15, 12),
> +		.clk_id = {CLK_HIFSEL},
> +		.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
> +		.active_wakeup = true,
> +	},
> +	[MT7622_POWER_DOMAIN_WB] = {
> +		.name = "wb",
> +		.sta_mask = PWR_STATUS_WB,
> +		.ctl_offs = SPM_WB_PWR_CON,
> +		.sram_pdn_bits = 0,
> +		.sram_pdn_ack_bits = 0,
> +		.clk_id = {CLK_NONE},
> +		.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
> +		.active_wakeup = true,
> +	},
> +};
> +
> +#define NUM_DOMAINS_MT7622	ARRAY_SIZE(scp_domain_data_mt7622)
> +
> +static int __init scpsys_probe_mt7622(struct platform_device *pdev)
> +{
> +	struct scp *scp;
> +
> +	scp = init_scp(pdev, scp_domain_data_mt7622, NUM_DOMAINS_MT7622);

This does not look correct, init_scp awaits 4 arguments.

Apart, please rebase your patches against v4.13-rc1 as this does not apply cleanly.

Thanks,
Matthias

> +	if (IS_ERR(scp))
> +		return PTR_ERR(scp);
> +
> +	mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT7622);
> +
> +	return 0;
> +}
> +
> +/*
>    * MT8173 power domain support
>    */
>   
> @@ -698,6 +771,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
>   		.compatible = "mediatek,mt2701-scpsys",
>   		.data = scpsys_probe_mt2701,
>   	}, {
> +		.compatible = "mediatek,mt7622-scpsys",
> +		.data = scpsys_probe_mt7622,
> +	}, {
>   		.compatible = "mediatek,mt8173-scpsys",
>   		.data = scpsys_probe_mt8173,
>   	}, {
> diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
> index a5714e9..c1e5062 100644
> --- a/include/linux/soc/mediatek/infracfg.h
> +++ b/include/linux/soc/mediatek/infracfg.h
> @@ -20,7 +20,13 @@
>   #define MT8173_TOP_AXI_PROT_EN_MFG_M1		BIT(22)
>   #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT	BIT(23)
>   
> +#define MT7622_TOP_AXI_PROT_EN_ETHSYS		(BIT(3) | BIT(17))
> +#define MT7622_TOP_AXI_PROT_EN_HIF0		(BIT(24) | BIT(25))
> +#define MT7622_TOP_AXI_PROT_EN_HIF1		(BIT(26) | BIT(27) | \
> +						 BIT(28))
> +#define MT7622_TOP_AXI_PROT_EN_WB		(BIT(2) | BIT(6) | \
> +						 BIT(7) | BIT(8))
> +
>   int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask);
>   int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask);
> -
>   #endif /* __SOC_MEDIATEK_INFRACFG_H */
>