From: Andy Lutomirski <luto@kernel.org>
To: peterz@infradead.org, x86@kernel.org
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Dave Hansen <dave.hansen@linux.intel.com>,
Rik van Riel <riel@redhat.com>, Brian Gerst <brgerst@gmail.com>,
Andrew Morton <akpm@linux-foundation.org>,
Denys Vlasenko <dvlasenk@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Linus Torvalds <torvalds@linux-foundation.org>,
"linux-tip-commits@vger.kernel.org"
<linux-tip-commits@vger.kernel.org>,
Andy Lutomirski <luto@kernel.org>,
stable@vger.kernel.org
Subject: [PATCH] x86/mm: Improve switch_mm barrier comments
Date: Tue, 12 Jan 2016 12:11:10 -0800 [thread overview]
Message-ID: <e0dccd19c3b5c25107bb6d460c3d180c15b3c9fd.1452629371.git.luto@kernel.org> (raw)
In-Reply-To: <20160112102105.GA4878@gmail.com>
My previous comments were still a bit confusing and there was a
typo. Fix it up.
Reported-by: Peter Zijlstra <peterz@infradead.org>
Fixes: 71b3c126e611 ("x86/mm: Add barriers and document switch_mm()-vs-flush synchronization")
Cc: stable@vger.kernel.org
Signed-off-by: Andy Lutomirski <luto@kernel.org>
---
arch/x86/include/asm/mmu_context.h | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
index 1edc9cd198b8..e08d27369fce 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -132,14 +132,14 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
* be sent, and CPU 0's TLB will contain a stale entry.)
*
* The bad outcome can occur if either CPU's load is
- * reordered before that CPU's store, so both CPUs much
+ * reordered before that CPU's store, so both CPUs must
* execute full barriers to prevent this from happening.
*
* Thus, switch_mm needs a full barrier between the
* store to mm_cpumask and any operation that could load
* from next->pgd. This barrier synchronizes with
- * remote TLB flushers. Fortunately, load_cr3 is
- * serializing and thus acts as a full barrier.
+ * remote TLB flushers. Fortunately, cpumask_set_cpu is
+ * (on x86) a full barrier, and load_cr3 is serializing.
*
*/
load_cr3(next->pgd);
@@ -188,9 +188,10 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
* tlb flush IPI delivery. We must reload CR3
* to make sure to use no freed page tables.
*
- * As above, this is a barrier that forces
- * TLB repopulation to be ordered after the
- * store to mm_cpumask.
+ * As above, either of cpumask_set_cpu and
+ * load_cr3 is a sufficient barrier to force TLB
+ * repopulation to be ordered after the store to
+ * mm_cpumask.
*/
load_cr3(next->pgd);
trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
--
2.5.0
next prev parent reply other threads:[~2016-01-12 20:12 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <tip-71b3c126e61177eb693423f2e18a1914205b165e@git.kernel.org>
2016-01-11 18:25 ` [tip:x86/urgent] x86/mm: Add barriers and document switch_mm() -vs-flush synchronization Peter Zijlstra
2016-01-11 21:50 ` Andy Lutomirski
2016-01-11 22:22 ` Peter Zijlstra
2016-01-12 10:21 ` Ingo Molnar
2016-01-12 20:11 ` Andy Lutomirski [this message]
2016-01-12 20:47 ` [PATCH v2] x86/mm: Improve switch_mm barrier comments Andy Lutomirski
2016-01-14 9:06 ` [tip:x86/urgent] x86/mm: Improve switch_mm() " tip-bot for Andy Lutomirski
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