[PATCH v3] mtd: spi-nor: macronix: Add support for mx66l2g45g

[PATCH v3] mtd: spi-nor: macronix: Add support for mx66l2g45g

[Jiaqing Zhao]

Macronix mx66l2g45g is a 3V, 2Gbit (256MB) NOR flash that supports
x1, x2, and x4 operation modes.

Tested read/write/erase with Aspeed AST2600 BMC SoC operating in x2
mode at 50MHz, using Aspeed spi-mem driver.

Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
---
 drivers/mtd/spi-nor/macronix.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index d81a4cb2812b..33d02a01b381 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -95,6 +95,8 @@ static const struct flash_info macronix_nor_parts[] = {
 	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048)
 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
 			      SPI_NOR_QUAD_READ) },
+	// TODO: Use SNOR_ID3() for "mx66l2g45g"
+	{ "mx66l2g45g",  INFO(0xc2201c, 0, 0, 0) PARSE_SFDP },
 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048)
 		NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
 	{ "mx66u2g45g",	 INFO(0xc2253c, 0, 64 * 1024, 4096)
-- 
2.34.1

Re: [PATCH v3] mtd: spi-nor: macronix: Add support for mx66l2g45g

[Michael Walle]

Am 2022-05-23 17:03, schrieb Jiaqing Zhao:
> Macronix mx66l2g45g is a 3V, 2Gbit (256MB) NOR flash that supports
> x1, x2, and x4 operation modes.
> 
> Tested read/write/erase with Aspeed AST2600 BMC SoC operating in x2
> mode at 50MHz, using Aspeed spi-mem driver.
> 
> Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>

Reviewed-by: Michael Walle <michael@walle.cc>

# is this picked up by b4? link goes to the sfdp dump
Link: 
https://lore.kernel.org/r/2b859cff-2403-0526-f3ae-749920b3fd8b@linux.intel.com

-michael

Re: [PATCH v3] mtd: spi-nor: macronix: Add support for mx66l2g45g

[Jiaqing Zhao]

On 2022-05-24 01:04, Michael Walle wrote:
> Am 2022-05-23 17:03, schrieb Jiaqing Zhao:
>> Macronix mx66l2g45g is a 3V, 2Gbit (256MB) NOR flash that supports
>> x1, x2, and x4 operation modes.
>>
>> Tested read/write/erase with Aspeed AST2600 BMC SoC operating in x2
>> mode at 50MHz, using Aspeed spi-mem driver.
>>
>> Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
> 
> Reviewed-by: Michael Walle <michael@walle.cc>
> 
> # is this picked up by b4? link goes to the sfdp dump

May I ask what do you mean by "is this picked up by b4?"

> Link: https://lore.kernel.org/r/2b859cff-2403-0526-f3ae-749920b3fd8b@linux.intel.com
> 
> -michael

Re: [PATCH v3] mtd: spi-nor: macronix: Add support for mx66l2g45g

[Michael Walle]

Am 2022-05-24 05:35, schrieb Jiaqing Zhao:
> On 2022-05-24 01:04, Michael Walle wrote:
>> Am 2022-05-23 17:03, schrieb Jiaqing Zhao:
>>> Macronix mx66l2g45g is a 3V, 2Gbit (256MB) NOR flash that supports
>>> x1, x2, and x4 operation modes.
>>> 
>>> Tested read/write/erase with Aspeed AST2600 BMC SoC operating in x2
>>> mode at 50MHz, using Aspeed spi-mem driver.
>>> 
>>> Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
>> 
>> Reviewed-by: Michael Walle <michael@walle.cc>
>> 
>> # is this picked up by b4? link goes to the sfdp dump
> 
> May I ask what do you mean by "is this picked up by b4?"

It was question to the maintainers (or myself). b4 the tool
the spi-nor maintainers [1] use to pick up the patches. And,
no it is not picked up automatically.

-michael

[1] 
https://people.kernel.org/monsieuricon/introducing-b4-and-patch-attestation

>> Link: 
>> https://lore.kernel.org/r/2b859cff-2403-0526-f3ae-749920b3fd8b@linux.intel.com