* [PATCH] tty: serial: qcom-geni-serial: Fix %lu -> %u in print statements
@ 2022-08-02 20:23 Douglas Anderson
2022-08-04 7:00 ` Jiri Slaby
0 siblings, 1 reply; 2+ messages in thread
From: Douglas Anderson @ 2022-08-02 20:23 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Mark Brown, Douglas Anderson, Andy Gross, Bjorn Andersson,
Jiri Slaby, Vijaya Krishna Nivarthi, linux-arm-msm, linux-kernel,
linux-serial
When we multiply an unsigned int by a u32 we still end up with an
unsigned int. That means we should specify "%u" not "%lu" in the
format code.
NOTE: this fix was chosen instead of somehow promoting the value to
"unsigned long" since the max baud rate from the earlier call to
uart_get_baud_rate() is 4000000 and the max sampling rate is 32.
4000000 * 32 = 0x07a12000, not even close to overflowing 32-bits.
Fixes: c474c775716e ("tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which otherwise could return a sub-optimal clock rate.")
Reported-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
drivers/tty/serial/qcom_geni_serial.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index f754619451dc..f7c1f1807040 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -1033,12 +1033,12 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
sampling_rate, &clk_div);
if (!clk_rate) {
dev_err(port->se.dev,
- "Couldn't find suitable clock rate for %lu\n",
+ "Couldn't find suitable clock rate for %u\n",
baud * sampling_rate);
goto out_restart_rx;
}
- dev_dbg(port->se.dev, "desired_rate-%lu, clk_rate-%lu, clk_div-%u\n",
+ dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n",
baud * sampling_rate, clk_rate, clk_div);
uport->uartclk = clk_rate;
--
2.37.1.455.g008518b4e5-goog
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] tty: serial: qcom-geni-serial: Fix %lu -> %u in print statements
2022-08-02 20:23 [PATCH] tty: serial: qcom-geni-serial: Fix %lu -> %u in print statements Douglas Anderson
@ 2022-08-04 7:00 ` Jiri Slaby
0 siblings, 0 replies; 2+ messages in thread
From: Jiri Slaby @ 2022-08-04 7:00 UTC (permalink / raw)
To: Douglas Anderson, Greg Kroah-Hartman
Cc: Mark Brown, Andy Gross, Bjorn Andersson, Vijaya Krishna Nivarthi,
linux-arm-msm, linux-kernel, linux-serial
On 02. 08. 22, 22:23, Douglas Anderson wrote:
> When we multiply an unsigned int by a u32 we still end up with an
> unsigned int. That means we should specify "%u" not "%lu" in the
> format code.
>
> NOTE: this fix was chosen instead of somehow promoting the value to
> "unsigned long" since the max baud rate from the earlier call to
> uart_get_baud_rate() is 4000000 and the max sampling rate is 32.
> 4000000 * 32 = 0x07a12000, not even close to overflowing 32-bits.
Acked-by: Jiri Slaby <jirislaby@kernel.org>
I wonder, how this became unnoticed by the 0day bot?
> Fixes: c474c775716e ("tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which otherwise could return a sub-optimal clock rate.")
> Reported-by: Mark Brown <broonie@kernel.org>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
>
> drivers/tty/serial/qcom_geni_serial.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
> index f754619451dc..f7c1f1807040 100644
> --- a/drivers/tty/serial/qcom_geni_serial.c
> +++ b/drivers/tty/serial/qcom_geni_serial.c
> @@ -1033,12 +1033,12 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
> sampling_rate, &clk_div);
> if (!clk_rate) {
> dev_err(port->se.dev,
> - "Couldn't find suitable clock rate for %lu\n",
> + "Couldn't find suitable clock rate for %u\n",
> baud * sampling_rate);
> goto out_restart_rx;
> }
>
> - dev_dbg(port->se.dev, "desired_rate-%lu, clk_rate-%lu, clk_div-%u\n",
> + dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n",
> baud * sampling_rate, clk_rate, clk_div);
>
> uport->uartclk = clk_rate;
--
js
suse labs
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