From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, guoren@linux.alibaba.com,
vincent.chen@sifive.com, paul.walmsley@sifive.com,
palmerdabbelt@google.com, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, oleg@redhat.com
Subject: [RFC PATCH v4 07/13] riscv: Add has_vector/riscv_vsize to save vector features.
Date: Tue, 26 May 2020 15:02:36 +0800 [thread overview]
Message-ID: <e896db91e3303f64ac401021f848e536e9d42aaa.1590474856.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1590474856.git.greentime.hu@sifive.com>
From: Guo Ren <guoren@linux.alibaba.com>
This patch is used to detect vector support status of CPU and use
riscv_vsize to save the size of all the vector registers. It assumes
all harts has the same capabilities in SMP system.
[greentime.hu@sifive.com: add support for dynamic vlen]
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
---
arch/riscv/kernel/cpufeature.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index c8527d770c98..5a68a926da68 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -16,6 +16,10 @@ unsigned long elf_hwcap __read_mostly;
#ifdef CONFIG_FPU
bool has_fpu __read_mostly;
#endif
+#ifdef CONFIG_VECTOR
+bool has_vector __read_mostly;
+unsigned long riscv_vsize __read_mostly;
+#endif
void riscv_fill_hwcap(void)
{
@@ -73,4 +77,11 @@ void riscv_fill_hwcap(void)
if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
has_fpu = true;
#endif
+
+#ifdef CONFIG_VECTOR
+ if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+ has_vector = true;
+ riscv_vsize = csr_read(CSR_VLENB) * 32;
+ }
+#endif
}
--
2.26.2
next prev parent reply other threads:[~2020-05-26 7:03 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-26 7:02 [RFC PATCH v4 00/13] riscv: Add vector ISA support Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 01/13] ptrace: Use regset_size() for dynamic regset size Greentime Hu
2020-05-26 14:00 ` Oleg Nesterov
2020-05-27 6:34 ` Greentime Hu
2020-05-27 11:31 ` Oleg Nesterov
2020-05-26 7:02 ` [RFC PATCH v4 02/13] riscv: Separate patch for cflags and aflags Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 03/13] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 04/13] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 05/13] riscv: Add new csr defines related to vector extension Greentime Hu
2020-05-31 1:56 ` Guo Ren
2020-06-01 8:15 ` Greentime Hu
2020-06-01 8:59 ` Guo Ren
2020-06-01 9:03 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 06/13] riscv: Add vector feature to compile Greentime Hu
2020-05-26 7:02 ` Greentime Hu [this message]
2020-05-31 0:58 ` [RFC PATCH v4 07/13] riscv: Add has_vector/riscv_vsize to save vector features Guo Ren
2020-06-01 8:07 ` Greentime Hu
2020-06-01 9:13 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 08/13] riscv: Reset vector register Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 09/13] riscv: Add vector struct and assembler definitions Greentime Hu
2020-06-01 9:12 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 10/13] riscv: Add task switch support for vector Greentime Hu
2020-05-31 15:29 ` Guo Ren
2020-05-31 16:08 ` Guo Ren
2020-06-01 9:12 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 11/13] riscv: Add ptrace vector support Greentime Hu
2020-06-01 9:14 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 12/13] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-05-31 15:28 ` Guo Ren
2020-06-01 9:13 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 13/13] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2020-05-31 15:52 ` [RFC PATCH v4 00/13] riscv: Add vector ISA support Guo Ren
2020-06-02 2:21 ` Greentime Hu
2020-06-02 3:08 ` Guo Ren
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