* [PATCH] ARM: dts: zynq: enablement of coresight topology
@ 2019-10-09 14:07 Michal Simek
2019-10-10 7:35 ` qwang2
2019-10-23 17:32 ` Mathieu Poirier
0 siblings, 2 replies; 4+ messages in thread
From: Michal Simek @ 2019-10-09 14:07 UTC (permalink / raw)
To: linux-kernel, monstr, michal.simek, git
Cc: Zumeng Chen, Quanyang Wang, Mark Rutland, Peter Crosthwaite,
Rob Herring, Rob Herring, Rob Herring, Steffen Trumtrar,
devicetree, linux-arm-kernel, u-boot
From: Zumeng Chen <zumeng.chen@windriver.com>
This patch is to build the coresight topology structure of zynq-7000
series according to the docs of coresight and userguide of zynq-7000.
Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/boot/dts/zynq-7000.dtsi | 158 +++++++++++++++++++++++++++++++
1 file changed, 158 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index ca6425ad794c..86430ad76fee 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -59,6 +59,40 @@
regulator-always-on;
};
+ replicator {
+ compatible = "arm,coresight-static-replicator";
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&etb_in_port>;
+ };
+ };
+ };
+ in-ports {
+ /* replicator input port */
+ port {
+ replicator_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&funnel_out_port>;
+ };
+ };
+ };
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <1>;
@@ -365,5 +399,129 @@
reg = <0xf8005000 0x1000>;
timeout-sec = <10>;
};
+
+ etb@f8801000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0xf8801000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ etb_in_port: endpoint {
+ remote-endpoint = <&replicator_out_port1>;
+ };
+ };
+ };
+ };
+
+ tpiu@f8803000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0xf8803000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint = <&replicator_out_port0>;
+ };
+ };
+ };
+ };
+
+ funnel@f8804000 {
+ compatible = "arm,coresight-static-funnel", "arm,primecell";
+ reg = <0xf8804000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ /* funnel output ports */
+ out-ports {
+ port {
+ funnel_out_port: endpoint {
+ remote-endpoint =
+ <&replicator_in_port0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel input ports */
+ port@0 {
+ reg = <0>;
+ funnel0_in_port0: endpoint {
+ remote-endpoint = <&ptm0_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel0_in_port1: endpoint {
+ remote-endpoint = <&ptm1_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel0_in_port2: endpoint {
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel0_in_port3: endpoint {
+ remote-endpoint = <&itm_out_port>;
+ };
+ };
+ /* The other input ports are not connect to anything */
+ };
+ };
+
+ /* ITM is not supported by kernel, only leave device node here */
+ itm@f8805000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0xf8805000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ out-ports {
+ port {
+ itm_out_port: endpoint {
+ remote-endpoint = <&funnel0_in_port3>;
+ };
+ };
+ };
+ };
+
+ ptm@f889c000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0xf889c000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ cpu = <&cpu0>;
+ out-ports {
+ port {
+ ptm0_out_port: endpoint {
+ remote-endpoint = <&funnel0_in_port0>;
+ };
+ };
+ };
+ };
+
+ ptm@f889d000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0xf889d000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ cpu = <&cpu1>;
+ out-ports {
+ port {
+ ptm1_out_port: endpoint {
+ remote-endpoint = <&funnel0_in_port1>;
+ };
+ };
+ };
+ };
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] ARM: dts: zynq: enablement of coresight topology
2019-10-09 14:07 [PATCH] ARM: dts: zynq: enablement of coresight topology Michal Simek
@ 2019-10-10 7:35 ` qwang2
2019-10-23 17:32 ` Mathieu Poirier
1 sibling, 0 replies; 4+ messages in thread
From: qwang2 @ 2019-10-10 7:35 UTC (permalink / raw)
To: Michal Simek, linux-kernel, monstr, git
Cc: Zumeng Chen, Mark Rutland, Peter Crosthwaite, Rob Herring,
Rob Herring, Rob Herring, Steffen Trumtrar, devicetree,
linux-arm-kernel, u-boot
On 10/9/19 10:07 PM, Michal Simek wrote:
> From: Zumeng Chen <zumeng.chen@windriver.com>
>
> This patch is to build the coresight topology structure of zynq-7000
> series according to the docs of coresight and userguide of zynq-7000.
>
> Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
> Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> arch/arm/boot/dts/zynq-7000.dtsi | 158 +++++++++++++++++++++++++++++++
> 1 file changed, 158 insertions(+)
>
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> index ca6425ad794c..86430ad76fee 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -59,6 +59,40 @@
> regulator-always-on;
> };
>
> + replicator {
> + compatible = "arm,coresight-static-replicator";
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* replicator output ports */
> + port@0 {
> + reg = <0>;
> + replicator_out_port0: endpoint {
> + remote-endpoint = <&tpiu_in_port>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + replicator_out_port1: endpoint {
> + remote-endpoint = <&etb_in_port>;
> + };
> + };
> + };
> + in-ports {
> + /* replicator input port */
> + port {
> + replicator_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&funnel_out_port>;
> + };
> + };
> + };
> + };
> +
> amba: amba {
> compatible = "simple-bus";
> #address-cells = <1>;
> @@ -365,5 +399,129 @@
> reg = <0xf8005000 0x1000>;
> timeout-sec = <10>;
> };
> +
> + etb@f8801000 {
> + compatible = "arm,coresight-etb10", "arm,primecell";
> + reg = <0xf8801000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + in-ports {
> + port {
> + etb_in_port: endpoint {
> + remote-endpoint = <&replicator_out_port1>;
> + };
> + };
> + };
> + };
> +
> + tpiu@f8803000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0xf8803000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + in-ports {
> + port {
> + tpiu_in_port: endpoint {
> + remote-endpoint = <&replicator_out_port0>;
> + };
> + };
> + };
> + };
> +
> + funnel@f8804000 {
> + compatible = "arm,coresight-static-funnel", "arm,primecell";
> + reg = <0xf8804000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +
> + /* funnel output ports */
> + out-ports {
> + port {
> + funnel_out_port: endpoint {
> + remote-endpoint =
> + <&replicator_in_port0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* funnel input ports */
> + port@0 {
> + reg = <0>;
> + funnel0_in_port0: endpoint {
> + remote-endpoint = <&ptm0_out_port>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + funnel0_in_port1: endpoint {
> + remote-endpoint = <&ptm1_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + funnel0_in_port2: endpoint {
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + funnel0_in_port3: endpoint {
> + remote-endpoint = <&itm_out_port>;
> + };
> + };
> + /* The other input ports are not connect to anything */
> + };
> + };
> +
> + /* ITM is not supported by kernel, only leave device node here */
> + itm@f8805000 {
> + compatible = "arm,coresight-etm3x", "arm,primecell";
The "arm,coresight-etm3x" shouldn't be the compatible property for ITM.
Had better remove it.
Thanks,
Quanyang
> + reg = <0xf8805000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + out-ports {
> + port {
> + itm_out_port: endpoint {
> + remote-endpoint = <&funnel0_in_port3>;
> + };
> + };
> + };
> + };
> +
> + ptm@f889c000 {
> + compatible = "arm,coresight-etm3x", "arm,primecell";
> + reg = <0xf889c000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + cpu = <&cpu0>;
> + out-ports {
> + port {
> + ptm0_out_port: endpoint {
> + remote-endpoint = <&funnel0_in_port0>;
> + };
> + };
> + };
> + };
> +
> + ptm@f889d000 {
> + compatible = "arm,coresight-etm3x", "arm,primecell";
> + reg = <0xf889d000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + cpu = <&cpu1>;
> + out-ports {
> + port {
> + ptm1_out_port: endpoint {
> + remote-endpoint = <&funnel0_in_port1>;
> + };
> + };
> + };
> + };
> };
> };
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] ARM: dts: zynq: enablement of coresight topology
2019-10-09 14:07 [PATCH] ARM: dts: zynq: enablement of coresight topology Michal Simek
2019-10-10 7:35 ` qwang2
@ 2019-10-23 17:32 ` Mathieu Poirier
2019-10-24 7:05 ` Michal Simek
1 sibling, 1 reply; 4+ messages in thread
From: Mathieu Poirier @ 2019-10-23 17:32 UTC (permalink / raw)
To: Michal Simek
Cc: Linux Kernel Mailing List, Michal Simek, git, Zumeng Chen,
Quanyang Wang, Mark Rutland, Peter Crosthwaite, Rob Herring,
Rob Herring, Rob Herring, Steffen Trumtrar, devicetree,
linux-arm-kernel, u-boot
Hi Michal,
I was not CC'ed on the original post so I just noticed this today,
hence the late reply. I don't know if you were looking for feedback
or already picked up the patch but here it is anyway.
On Wed, 9 Oct 2019 at 08:07, Michal Simek <michal.simek@xilinx.com> wrote:
>
> From: Zumeng Chen <zumeng.chen@windriver.com>
>
> This patch is to build the coresight topology structure of zynq-7000
> series according to the docs of coresight and userguide of zynq-7000.
>
> Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
> Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> arch/arm/boot/dts/zynq-7000.dtsi | 158 +++++++++++++++++++++++++++++++
> 1 file changed, 158 insertions(+)
>
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> index ca6425ad794c..86430ad76fee 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -59,6 +59,40 @@
> regulator-always-on;
> };
>
> + replicator {
> + compatible = "arm,coresight-static-replicator";
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* replicator output ports */
> + port@0 {
> + reg = <0>;
> + replicator_out_port0: endpoint {
> + remote-endpoint = <&tpiu_in_port>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + replicator_out_port1: endpoint {
> + remote-endpoint = <&etb_in_port>;
> + };
> + };
> + };
> + in-ports {
> + /* replicator input port */
> + port {
> + replicator_in_port0: endpoint {
> + slave-mode;
The slave-mode property is no longer required and probably an
oversight since it doesn't appear elsewhere in this patch.
> + remote-endpoint = <&funnel_out_port>;
> + };
> + };
> + };
> + };
> +
> amba: amba {
> compatible = "simple-bus";
> #address-cells = <1>;
> @@ -365,5 +399,129 @@
> reg = <0xf8005000 0x1000>;
> timeout-sec = <10>;
> };
> +
> + etb@f8801000 {
> + compatible = "arm,coresight-etb10", "arm,primecell";
> + reg = <0xf8801000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + in-ports {
> + port {
> + etb_in_port: endpoint {
> + remote-endpoint = <&replicator_out_port1>;
> + };
> + };
> + };
> + };
> +
> + tpiu@f8803000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0xf8803000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + in-ports {
> + port {
> + tpiu_in_port: endpoint {
> + remote-endpoint = <&replicator_out_port0>;
> + };
> + };
> + };
> + };
> +
> + funnel@f8804000 {
> + compatible = "arm,coresight-static-funnel", "arm,primecell";
> + reg = <0xf8804000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +
> + /* funnel output ports */
> + out-ports {
> + port {
> + funnel_out_port: endpoint {
> + remote-endpoint =
> + <&replicator_in_port0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* funnel input ports */
> + port@0 {
> + reg = <0>;
> + funnel0_in_port0: endpoint {
> + remote-endpoint = <&ptm0_out_port>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + funnel0_in_port1: endpoint {
> + remote-endpoint = <&ptm1_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + funnel0_in_port2: endpoint {
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + funnel0_in_port3: endpoint {
> + remote-endpoint = <&itm_out_port>;
> + };
> + };
> + /* The other input ports are not connect to anything */
> + };
> + };
> +
> + /* ITM is not supported by kernel, only leave device node here */
> + itm@f8805000 {
> + compatible = "arm,coresight-etm3x", "arm,primecell";
If I remember correctly ITM and ETMv3 are quite different - please
remove entirely.
> + reg = <0xf8805000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + out-ports {
> + port {
> + itm_out_port: endpoint {
> + remote-endpoint = <&funnel0_in_port3>;
> + };
> + };
> + };
> + };
> +
> + ptm@f889c000 {
> + compatible = "arm,coresight-etm3x", "arm,primecell";
> + reg = <0xf889c000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + cpu = <&cpu0>;
> + out-ports {
> + port {
> + ptm0_out_port: endpoint {
> + remote-endpoint = <&funnel0_in_port0>;
> + };
> + };
> + };
> + };
> +
> + ptm@f889d000 {
> + compatible = "arm,coresight-etm3x", "arm,primecell";
> + reg = <0xf889d000 0x1000>;
> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + cpu = <&cpu1>;
> + out-ports {
> + port {
> + ptm1_out_port: endpoint {
> + remote-endpoint = <&funnel0_in_port1>;
> + };
> + };
> + };
> + };
With the above:
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> };
> };
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] ARM: dts: zynq: enablement of coresight topology
2019-10-23 17:32 ` Mathieu Poirier
@ 2019-10-24 7:05 ` Michal Simek
0 siblings, 0 replies; 4+ messages in thread
From: Michal Simek @ 2019-10-24 7:05 UTC (permalink / raw)
To: Mathieu Poirier, Michal Simek
Cc: Linux Kernel Mailing List, Michal Simek, git, Zumeng Chen,
Quanyang Wang, Mark Rutland, Peter Crosthwaite, Rob Herring,
Rob Herring, Rob Herring, Steffen Trumtrar, devicetree,
linux-arm-kernel, u-boot
Hi Mathieu,
On 23. 10. 19 19:32, Mathieu Poirier wrote:
> Hi Michal,
>
> I was not CC'ed on the original post so I just noticed this today,
> hence the late reply. I don't know if you were looking for feedback
> or already picked up the patch but here it is anyway.
I haven't put the patch to my zynq/dt branch yet. And definitely any
feedback on this is welcome.
>
> On Wed, 9 Oct 2019 at 08:07, Michal Simek <michal.simek@xilinx.com> wrote:
>>
>> From: Zumeng Chen <zumeng.chen@windriver.com>
>>
>> This patch is to build the coresight topology structure of zynq-7000
>> series according to the docs of coresight and userguide of zynq-7000.
>>
>> Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
>> Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>> arch/arm/boot/dts/zynq-7000.dtsi | 158 +++++++++++++++++++++++++++++++
>> 1 file changed, 158 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
>> index ca6425ad794c..86430ad76fee 100644
>> --- a/arch/arm/boot/dts/zynq-7000.dtsi
>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
>> @@ -59,6 +59,40 @@
>> regulator-always-on;
>> };
>>
>> + replicator {
>> + compatible = "arm,coresight-static-replicator";
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> +
>> + out-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* replicator output ports */
>> + port@0 {
>> + reg = <0>;
>> + replicator_out_port0: endpoint {
>> + remote-endpoint = <&tpiu_in_port>;
>> + };
>> + };
>> + port@1 {
>> + reg = <1>;
>> + replicator_out_port1: endpoint {
>> + remote-endpoint = <&etb_in_port>;
>> + };
>> + };
>> + };
>> + in-ports {
>> + /* replicator input port */
>> + port {
>> + replicator_in_port0: endpoint {
>> + slave-mode;
>
> The slave-mode property is no longer required and probably an
> oversight since it doesn't appear elsewhere in this patch.
likely yes. I will remove it.
>
>> + remote-endpoint = <&funnel_out_port>;
>> + };
>> + };
>> + };
>> + };
>> +
>> amba: amba {
>> compatible = "simple-bus";
>> #address-cells = <1>;
>> @@ -365,5 +399,129 @@
>> reg = <0xf8005000 0x1000>;
>> timeout-sec = <10>;
>> };
>> +
>> + etb@f8801000 {
>> + compatible = "arm,coresight-etb10", "arm,primecell";
>> + reg = <0xf8801000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + in-ports {
>> + port {
>> + etb_in_port: endpoint {
>> + remote-endpoint = <&replicator_out_port1>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + tpiu@f8803000 {
>> + compatible = "arm,coresight-tpiu", "arm,primecell";
>> + reg = <0xf8803000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + in-ports {
>> + port {
>> + tpiu_in_port: endpoint {
>> + remote-endpoint = <&replicator_out_port0>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@f8804000 {
>> + compatible = "arm,coresight-static-funnel", "arm,primecell";
>> + reg = <0xf8804000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> +
>> + /* funnel output ports */
>> + out-ports {
>> + port {
>> + funnel_out_port: endpoint {
>> + remote-endpoint =
>> + <&replicator_in_port0>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* funnel input ports */
>> + port@0 {
>> + reg = <0>;
>> + funnel0_in_port0: endpoint {
>> + remote-endpoint = <&ptm0_out_port>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + funnel0_in_port1: endpoint {
>> + remote-endpoint = <&ptm1_out_port>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <2>;
>> + funnel0_in_port2: endpoint {
>> + };
>> + };
>> +
>> + port@3 {
>> + reg = <3>;
>> + funnel0_in_port3: endpoint {
>> + remote-endpoint = <&itm_out_port>;
>> + };
>> + };
>> + /* The other input ports are not connect to anything */
>> + };
>> + };
>> +
>> + /* ITM is not supported by kernel, only leave device node here */
>> + itm@f8805000 {
>> + compatible = "arm,coresight-etm3x", "arm,primecell";
>
> If I remember correctly ITM and ETMv3 are quite different - please
> remove entirely.
This was commented already. Definitely "arm,coresight-etm3x" should be
removed. arm,primecell could stay there.
Do you think that make sense to remove it completely because I expect
that connection to funnel should be aligned with others.
>
>> + reg = <0xf8805000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + out-ports {
>> + port {
>> + itm_out_port: endpoint {
>> + remote-endpoint = <&funnel0_in_port3>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + ptm@f889c000 {
>> + compatible = "arm,coresight-etm3x", "arm,primecell";
>> + reg = <0xf889c000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + cpu = <&cpu0>;
>> + out-ports {
>> + port {
>> + ptm0_out_port: endpoint {
>> + remote-endpoint = <&funnel0_in_port0>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + ptm@f889d000 {
>> + compatible = "arm,coresight-etm3x", "arm,primecell";
>> + reg = <0xf889d000 0x1000>;
>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + cpu = <&cpu1>;
>> + out-ports {
>> + port {
>> + ptm1_out_port: endpoint {
>> + remote-endpoint = <&funnel0_in_port1>;
>> + };
>> + };
>> + };
>> + };
>
> With the above:
>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Let's discuss that ITM part first and definitely thanks for review.
Thanks,
Michal
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-10-24 7:05 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2019-10-09 14:07 [PATCH] ARM: dts: zynq: enablement of coresight topology Michal Simek
2019-10-10 7:35 ` qwang2
2019-10-23 17:32 ` Mathieu Poirier
2019-10-24 7:05 ` Michal Simek
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