* [PATCH V4 0/3] Convert QUP bindings to YAML and add ICC, pin swap doc @ 2020-02-17 9:36 Akash Asthana 2020-02-17 9:36 ` [PATCH V4 1/3] dt-bindings: geni-se: Convert QUP geni-se bindings to YAML Akash Asthana ` (2 more replies) 0 siblings, 3 replies; 12+ messages in thread From: Akash Asthana @ 2020-02-17 9:36 UTC (permalink / raw) To: robh+dt, agross, mark.rutland Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd, Akash Asthana Changes in V4: - Add interconnect binding patch. - Add UART pin swap binding patch. Akash Asthana (3): dt-bindings: geni-se: Convert QUP geni-se bindings to YAML dt-bindings: geni-se: Add interconnect binding for GENI QUP dt-bindings: geni-se: Add binding for UART pin swap .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 94 --------- .../devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 227 +++++++++++++++++++++ 2 files changed, 227 insertions(+), 94 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH V4 1/3] dt-bindings: geni-se: Convert QUP geni-se bindings to YAML 2020-02-17 9:36 [PATCH V4 0/3] Convert QUP bindings to YAML and add ICC, pin swap doc Akash Asthana @ 2020-02-17 9:36 ` Akash Asthana 2020-02-18 21:19 ` Rob Herring 2020-02-25 18:20 ` Stephen Boyd 2020-02-17 9:36 ` [PATCH V4 2/3] dt-bindings: geni-se: Add interconnect binding for GENI QUP Akash Asthana 2020-02-17 9:36 ` [PATCH V4 3/3] dt-bindings: geni-se: Add binding for UART pin swap Akash Asthana 2 siblings, 2 replies; 12+ messages in thread From: Akash Asthana @ 2020-02-17 9:36 UTC (permalink / raw) To: robh+dt, agross, mark.rutland Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd, Akash Asthana Convert QUP geni-se bindings to DT schema format using json-schema. Signed-off-by: Akash Asthana <akashast@codeaurora.org> --- Changes in V2: - As per Stephen's comment corrected defintion of interrupts for UART node. Any valid UART node must contain atleast 1 interrupts. Changes in V3: - As per Rob's comment, added number of reg entries for reg property. - As per Rob's comment, corrected unit address to hex. - As per Rob's comment, created a pattern which matches everything common to geni based I2C, SPI and UART controller and then one pattern for each. - As per Rob's comment, restored original example. Changes in V4: - Resolve below compilation error reported from bot. /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/ qcom,geni-se.yaml: properties:clocks:minItems: False schema does not allow 2 /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/ qcom,geni-se.yaml: properties:clocks:maxItems: False schema does not allow 2 Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dts' failed make[1]: *** [Documentation/devicetree/bindings/soc/qcom/ qcom,geni-se.example.dts] Error 1 Makefile:1263: recipe for target 'dt_binding_check' failed make: *** [dt_binding_check] Error 2 .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 94 --------- .../devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 209 +++++++++++++++++++++ 2 files changed, 209 insertions(+), 94 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt deleted file mode 100644 index dab7ca9..0000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt +++ /dev/null @@ -1,94 +0,0 @@ -Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller - -Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper -is a programmable module for supporting a wide range of serial interfaces -like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial -Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP -Wrapper controller is modeled as a node with zero or more child nodes each -representing a serial engine. - -Required properties: -- compatible: Must be "qcom,geni-se-qup". -- reg: Must contain QUP register address and length. -- clock-names: Must contain "m-ahb" and "s-ahb". -- clocks: AHB clocks needed by the device. - -Required properties if child node exists: -- #address-cells: Must be <1> for Serial Engine Address -- #size-cells: Must be <1> for Serial Engine Address Size -- ranges: Must be present - -Properties for children: - -A GENI based QUP wrapper controller node can contain 0 or more child nodes -representing serial devices. These serial devices can be a QCOM UART, I2C -controller, SPI controller, or some combination of aforementioned devices. -Please refer below the child node definitions for the supported serial -interface protocols. - -Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller - -Required properties: -- compatible: Must be "qcom,geni-i2c". -- reg: Must contain QUP register address and length. -- interrupts: Must contain I2C interrupt. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. -- #address-cells: Must be <1> for I2C device address. -- #size-cells: Must be <0> as I2C addresses have no size component. - -Optional property: -- clock-frequency: Desired I2C bus clock frequency in Hz. - When missing default to 100000Hz. - -Child nodes should conform to I2C bus binding as described in i2c.txt. - -Qualcomm Technologies Inc. GENI Serial Engine based UART Controller - -Required properties: -- compatible: Must be "qcom,geni-debug-uart" or "qcom,geni-uart". -- reg: Must contain UART register location and length. -- interrupts: Must contain UART core interrupts. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. - -Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller -node binding is described in -Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt. - -Example: - geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x8c0000 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - i2c0: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0xa94000 0x4000>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_i2c_5_active>; - pinctrl-1 = <&qup_1_i2c_5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@a88000 { - compatible = "qcom,geni-debug-uart"; - reg = <0xa88000 0x7000>; - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_uart_3_active>; - pinctrl-1 = <&qup_1_uart_3_sleep>; - }; - - } diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml new file mode 100644 index 0000000..23282ab --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -0,0 +1,209 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: GENI Serial Engine QUP Wrapper Controller + +maintainers: + - Mukesh Savaliya <msavaliy@codeaurora.org> + - Akash Asthana <akashast@codeaurora.org> + +description: | + Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper + is a programmable module for supporting a wide range of serial interfaces + like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial + Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP + Wrapper controller is modeled as a node with zero or more child nodes each + representing a serial engine. + +properties: + compatible: + enum: + - qcom,geni-se-qup + + reg: + description: QUP wrapper common register address and length. + maxItems: 1 + + clock-names: + items: + - const: m-ahb + - const: s-ahb + + clocks: + items: + - description: Master AHB Clock + - description: Slave AHB Clock + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +required: + - compatible + - reg + - clock-names + - clocks + - "#address-cells" + - "#size-cells" + - ranges + +patternProperties: + "^.*@[0-9a-f]+$": + type: object + description: Common properties for GENI Serial Engine based I2C, SPI and + UART controller. + + properties: + reg: + description: GENI Serial Engine register address and length. + maxItems: 1 + + clock-names: + const: se + + clocks: + description: Serial engine core clock needed by the device. + maxItems: 1 + + required: + - reg + - clock-names + - clocks + + "spi@[0-9a-f]+$": + type: object + description: GENI serial engine based SPI controller. SPI in master mode + supports up to 50MHz, up to four chip selects, programmable + data path from 4 bits to 32 bits and numerous protocol + variants. + allOf: + - $ref: /spi/spi-controller.yaml# + + properties: + compatible: + enum: + - qcom,geni-spi + + interrupts: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + required: + - compatible + - interrupts + - "#address-cells" + - "#size-cells" + + "i2c@[0-9a-f]+$": + type: object + description: GENI serial engine based I2C controller. + allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + + properties: + compatible: + enum: + - qcom,geni-i2c + + interrupts: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clock-frequency: + description: Desired I2C bus clock frequency in Hz. + default: 100000 + + required: + - compatible + - interrupts + - "#address-cells" + - "#size-cells" + + "serial@[0-9a-f]+$": + type: object + description: GENI Serial Engine based UART Controller. + allOf: + - $ref: /schemas/serial.yaml# + + properties: + compatible: + enum: + - qcom,geni-uart + - qcom,geni-debug-uart + + interrupts: + minItems: 1 + maxItems: 2 + items: + - description: UART core irq + - description: Wakeup irq (RX GPIO) + + required: + - compatible + - interrupts + + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + + geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0xa94000 0 0x4000>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_i2c_5_active>; + pinctrl-1 = <&qup_1_i2c_5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0 0xa88000 0 0x7000>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_uart_3_active>; + pinctrl-1 = <&qup_1_uart_3_sleep>; + }; + }; + }; + +... -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH V4 1/3] dt-bindings: geni-se: Convert QUP geni-se bindings to YAML 2020-02-17 9:36 ` [PATCH V4 1/3] dt-bindings: geni-se: Convert QUP geni-se bindings to YAML Akash Asthana @ 2020-02-18 21:19 ` Rob Herring 2020-02-25 18:20 ` Stephen Boyd 1 sibling, 0 replies; 12+ messages in thread From: Rob Herring @ 2020-02-18 21:19 UTC (permalink / raw) To: Akash Asthana Cc: robh+dt, agross, mark.rutland, linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd, Akash Asthana On Mon, 17 Feb 2020 15:06:50 +0530, Akash Asthana wrote: > Convert QUP geni-se bindings to DT schema format using json-schema. > > Signed-off-by: Akash Asthana <akashast@codeaurora.org> > --- > Changes in V2: > - As per Stephen's comment corrected defintion of interrupts for UART node. > Any valid UART node must contain atleast 1 interrupts. > > Changes in V3: > - As per Rob's comment, added number of reg entries for reg property. > - As per Rob's comment, corrected unit address to hex. > - As per Rob's comment, created a pattern which matches everything common > to geni based I2C, SPI and UART controller and then one pattern for each. > - As per Rob's comment, restored original example. > > Changes in V4: > - Resolve below compilation error reported from bot. > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/ > qcom,geni-se.yaml: properties:clocks:minItems: False schema does not allow 2 > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/ > qcom,geni-se.yaml: properties:clocks:maxItems: False schema does not allow 2 > Documentation/devicetree/bindings/Makefile:12: recipe for target > 'Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dts' failed > make[1]: *** [Documentation/devicetree/bindings/soc/qcom/ > qcom,geni-se.example.dts] Error 1 > Makefile:1263: recipe for target 'dt_binding_check' failed > make: *** [dt_binding_check] Error 2 > > .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 94 --------- > .../devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 209 +++++++++++++++++++++ > 2 files changed, 209 insertions(+), 94 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt > create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V4 1/3] dt-bindings: geni-se: Convert QUP geni-se bindings to YAML 2020-02-17 9:36 ` [PATCH V4 1/3] dt-bindings: geni-se: Convert QUP geni-se bindings to YAML Akash Asthana 2020-02-18 21:19 ` Rob Herring @ 2020-02-25 18:20 ` Stephen Boyd 1 sibling, 0 replies; 12+ messages in thread From: Stephen Boyd @ 2020-02-25 18:20 UTC (permalink / raw) To: Akash Asthana, agross, mark.rutland, robh+dt Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, Akash Asthana Quoting Akash Asthana (2020-02-17 01:36:50) > Convert QUP geni-se bindings to DT schema format using json-schema. > > Signed-off-by: Akash Asthana <akashast@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH V4 2/3] dt-bindings: geni-se: Add interconnect binding for GENI QUP 2020-02-17 9:36 [PATCH V4 0/3] Convert QUP bindings to YAML and add ICC, pin swap doc Akash Asthana 2020-02-17 9:36 ` [PATCH V4 1/3] dt-bindings: geni-se: Convert QUP geni-se bindings to YAML Akash Asthana @ 2020-02-17 9:36 ` Akash Asthana 2020-02-18 21:19 ` Rob Herring 2020-02-25 18:21 ` Stephen Boyd 2020-02-17 9:36 ` [PATCH V4 3/3] dt-bindings: geni-se: Add binding for UART pin swap Akash Asthana 2 siblings, 2 replies; 12+ messages in thread From: Akash Asthana @ 2020-02-17 9:36 UTC (permalink / raw) To: robh+dt, agross, mark.rutland Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd, Akash Asthana Add documentation for the interconnect and interconnect-names properties for the GENI QUP. Signed-off-by: Akash Asthana <akashast@codeaurora.org> --- Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index 23282ab..11530df 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -73,6 +73,15 @@ patternProperties: description: Serial engine core clock needed by the device. maxItems: 1 + interconnects: + maxItems: 3 + + interconnect-names: + items: + - const: qup-core + - const: qup-config + - const: qup-memory + required: - reg - clock-names -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH V4 2/3] dt-bindings: geni-se: Add interconnect binding for GENI QUP 2020-02-17 9:36 ` [PATCH V4 2/3] dt-bindings: geni-se: Add interconnect binding for GENI QUP Akash Asthana @ 2020-02-18 21:19 ` Rob Herring 2020-02-25 18:21 ` Stephen Boyd 1 sibling, 0 replies; 12+ messages in thread From: Rob Herring @ 2020-02-18 21:19 UTC (permalink / raw) To: Akash Asthana Cc: robh+dt, agross, mark.rutland, linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd, Akash Asthana On Mon, 17 Feb 2020 15:06:51 +0530, Akash Asthana wrote: > Add documentation for the interconnect and interconnect-names properties > for the GENI QUP. > > Signed-off-by: Akash Asthana <akashast@codeaurora.org> > --- > Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 9 +++++++++ > 1 file changed, 9 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V4 2/3] dt-bindings: geni-se: Add interconnect binding for GENI QUP 2020-02-17 9:36 ` [PATCH V4 2/3] dt-bindings: geni-se: Add interconnect binding for GENI QUP Akash Asthana 2020-02-18 21:19 ` Rob Herring @ 2020-02-25 18:21 ` Stephen Boyd 1 sibling, 0 replies; 12+ messages in thread From: Stephen Boyd @ 2020-02-25 18:21 UTC (permalink / raw) To: Akash Asthana, agross, mark.rutland, robh+dt Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, Akash Asthana Quoting Akash Asthana (2020-02-17 01:36:51) > Add documentation for the interconnect and interconnect-names properties > for the GENI QUP. > > Signed-off-by: Akash Asthana <akashast@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH V4 3/3] dt-bindings: geni-se: Add binding for UART pin swap 2020-02-17 9:36 [PATCH V4 0/3] Convert QUP bindings to YAML and add ICC, pin swap doc Akash Asthana 2020-02-17 9:36 ` [PATCH V4 1/3] dt-bindings: geni-se: Convert QUP geni-se bindings to YAML Akash Asthana 2020-02-17 9:36 ` [PATCH V4 2/3] dt-bindings: geni-se: Add interconnect binding for GENI QUP Akash Asthana @ 2020-02-17 9:36 ` Akash Asthana 2020-02-18 19:07 ` Matthias Kaehlcke 2 siblings, 1 reply; 12+ messages in thread From: Akash Asthana @ 2020-02-17 9:36 UTC (permalink / raw) To: robh+dt, agross, mark.rutland Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd, Akash Asthana Add documentation to support RX/TX/CTS/RTS pin swap in HW. Signed-off-by: Akash Asthana <akashast@codeaurora.org> --- Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index 11530df..7e4b9af 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -165,6 +165,15 @@ patternProperties: - description: UART core irq - description: Wakeup irq (RX GPIO) + rx-tx-swap: + description: RX and TX pins are swap. + + cts-rts-swap: + description: CTS and RTS pins are swap. + + rx-tx-cts-rts-swap: + description: RX-TX and CTS-RTS both pairs are swap. + required: - compatible - interrupts -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH V4 3/3] dt-bindings: geni-se: Add binding for UART pin swap 2020-02-17 9:36 ` [PATCH V4 3/3] dt-bindings: geni-se: Add binding for UART pin swap Akash Asthana @ 2020-02-18 19:07 ` Matthias Kaehlcke 2020-02-19 13:21 ` Akash Asthana 0 siblings, 1 reply; 12+ messages in thread From: Matthias Kaehlcke @ 2020-02-18 19:07 UTC (permalink / raw) To: Akash Asthana Cc: robh+dt, agross, mark.rutland, linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd Hi Akash, I didn't see a patch that implements the binding, did you post it? On Mon, Feb 17, 2020 at 03:06:52PM +0530, Akash Asthana wrote: > Add documentation to support RX/TX/CTS/RTS pin swap in HW. > > Signed-off-by: Akash Asthana <akashast@codeaurora.org> > --- > Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml > index 11530df..7e4b9af 100644 > --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml > +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml > @@ -165,6 +165,15 @@ patternProperties: > - description: UART core irq > - description: Wakeup irq (RX GPIO) > > + rx-tx-swap: > + description: RX and TX pins are swap. s/swap/swapped/ > + > + cts-rts-swap: > + description: CTS and RTS pins are swap. s/swap/swapped/ > + > + rx-tx-cts-rts-swap: > + description: RX-TX and CTS-RTS both pairs are swap. I don't think this option adds much value, if both pairs are swapped the above two properties can be set. > + > required: > - compatible > - interrupts > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V4 3/3] dt-bindings: geni-se: Add binding for UART pin swap 2020-02-18 19:07 ` Matthias Kaehlcke @ 2020-02-19 13:21 ` Akash Asthana 2020-03-10 21:57 ` Matthias Kaehlcke 0 siblings, 1 reply; 12+ messages in thread From: Akash Asthana @ 2020-02-19 13:21 UTC (permalink / raw) To: Matthias Kaehlcke Cc: robh+dt, agross, mark.rutland, linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd Hi Matthias, On 2/19/2020 12:37 AM, Matthias Kaehlcke wrote: > Hi Akash, > > I didn't see a patch that implements the binding, did you post it? We haven't posted any update on patch@ https://patchwork.kernel.org/cover/11313817/ [tty: serial: qcom_geni_serial: Configure UART_IO_MACRO_CTRL register]. We will spin it ASAP. > > > On Mon, Feb 17, 2020 at 03:06:52PM +0530, Akash Asthana wrote: >> Add documentation to support RX/TX/CTS/RTS pin swap in HW. >> >> Signed-off-by: Akash Asthana <akashast@codeaurora.org> >> --- >> Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml >> index 11530df..7e4b9af 100644 >> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml >> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml >> @@ -165,6 +165,15 @@ patternProperties: >> - description: UART core irq >> - description: Wakeup irq (RX GPIO) >> >> + rx-tx-swap: >> + description: RX and TX pins are swap. > s/swap/swapped/ Ok > >> + >> + cts-rts-swap: >> + description: CTS and RTS pins are swap. > s/swap/swapped/ Ok > >> + >> + rx-tx-cts-rts-swap: >> + description: RX-TX and CTS-RTS both pairs are swap. > I don't think this option adds much value, if both pairs are swapped > the above two properties can be set. Yeah ok, It is possible to derive value for rx-tx-cts-rts if above 2 properties are set. > >> + >> required: >> - compatible >> - interrupts >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project Thanks for reviewing, Regards, Akash -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V4 3/3] dt-bindings: geni-se: Add binding for UART pin swap 2020-02-19 13:21 ` Akash Asthana @ 2020-03-10 21:57 ` Matthias Kaehlcke 2020-03-11 13:04 ` Akash Asthana 0 siblings, 1 reply; 12+ messages in thread From: Matthias Kaehlcke @ 2020-03-10 21:57 UTC (permalink / raw) To: Akash Asthana Cc: robh+dt, agross, mark.rutland, linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd Hi Akash, The patch that implements the binding landed in tty/tty-next: 9fa3c4b1fa379 tty: serial: qcom_geni_serial: Fix GPIO swapping with workaround The binding needs a re-spin to match the implementation. Thanks Matthias On Wed, Feb 19, 2020 at 06:51:35PM +0530, Akash Asthana wrote: > Hi Matthias, > > On 2/19/2020 12:37 AM, Matthias Kaehlcke wrote: > > Hi Akash, > > > > I didn't see a patch that implements the binding, did you post it? > > We haven't posted any update on patch@ > https://patchwork.kernel.org/cover/11313817/ > > [tty: serial: qcom_geni_serial: Configure UART_IO_MACRO_CTRL register]. We > will spin it ASAP. > > > > > > > On Mon, Feb 17, 2020 at 03:06:52PM +0530, Akash Asthana wrote: > > > Add documentation to support RX/TX/CTS/RTS pin swap in HW. > > > > > > Signed-off-by: Akash Asthana <akashast@codeaurora.org> > > > --- > > > Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 9 +++++++++ > > > 1 file changed, 9 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml > > > index 11530df..7e4b9af 100644 > > > --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml > > > +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml > > > @@ -165,6 +165,15 @@ patternProperties: > > > - description: UART core irq > > > - description: Wakeup irq (RX GPIO) > > > + rx-tx-swap: > > > + description: RX and TX pins are swap. > > s/swap/swapped/ > Ok > > > > > + > > > + cts-rts-swap: > > > + description: CTS and RTS pins are swap. > > s/swap/swapped/ > Ok > > > > > + > > > + rx-tx-cts-rts-swap: > > > + description: RX-TX and CTS-RTS both pairs are swap. > > I don't think this option adds much value, if both pairs are swapped > > the above two properties can be set. > > Yeah ok, It is possible to derive value for rx-tx-cts-rts if above 2 > properties are set. > > > > > > + > > > required: > > > - compatible > > > - interrupts > > > -- > > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project > > Thanks for reviewing, > > > Regards, > > Akash > > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V4 3/3] dt-bindings: geni-se: Add binding for UART pin swap 2020-03-10 21:57 ` Matthias Kaehlcke @ 2020-03-11 13:04 ` Akash Asthana 0 siblings, 0 replies; 12+ messages in thread From: Akash Asthana @ 2020-03-11 13:04 UTC (permalink / raw) To: Matthias Kaehlcke Cc: robh+dt, agross, mark.rutland, linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd On 3/11/2020 3:27 AM, Matthias Kaehlcke wrote: > Hi Akash, > > The patch that implements the binding landed in tty/tty-next: > > 9fa3c4b1fa379 tty: serial: qcom_geni_serial: Fix GPIO swapping with workaround > > The binding needs a re-spin to match the implementation. > > Thanks > > Matthias > Hi Matthias, I will re-spin this binding patches. Regards, Akash > > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-03-11 13:04 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-02-17 9:36 [PATCH V4 0/3] Convert QUP bindings to YAML and add ICC, pin swap doc Akash Asthana 2020-02-17 9:36 ` [PATCH V4 1/3] dt-bindings: geni-se: Convert QUP geni-se bindings to YAML Akash Asthana 2020-02-18 21:19 ` Rob Herring 2020-02-25 18:20 ` Stephen Boyd 2020-02-17 9:36 ` [PATCH V4 2/3] dt-bindings: geni-se: Add interconnect binding for GENI QUP Akash Asthana 2020-02-18 21:19 ` Rob Herring 2020-02-25 18:21 ` Stephen Boyd 2020-02-17 9:36 ` [PATCH V4 3/3] dt-bindings: geni-se: Add binding for UART pin swap Akash Asthana 2020-02-18 19:07 ` Matthias Kaehlcke 2020-02-19 13:21 ` Akash Asthana 2020-03-10 21:57 ` Matthias Kaehlcke 2020-03-11 13:04 ` Akash Asthana
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