From: Christophe Leroy <christophe.leroy@csgroup.eu>
To: Michael Ellerman <mpe@ellerman.id.au>,
Nicholas Piggin <npiggin@gmail.com>,
"Naveen N. Rao" <naveen.n.rao@linux.ibm.com>
Cc: Christophe Leroy <christophe.leroy@csgroup.eu>,
linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
bpf@vger.kernel.org, Alexei Starovoitov <ast@kernel.org>,
Daniel Borkmann <daniel@iogearbox.net>,
Andrii Nakryiko <andrii@kernel.org>,
Martin KaFai Lau <martin.lau@linux.dev>,
Song Liu <song@kernel.org>, Yonghong Song <yhs@fb.com>,
John Fastabend <john.fastabend@gmail.com>,
KP Singh <kpsingh@kernel.org>,
Stanislav Fomichev <sdf@google.com>, Hao Luo <haoluo@google.com>,
Jiri Olsa <jolsa@kernel.org>
Subject: [PATCH v1 07/10] powerpc/bpf: Only pad length-variable code at initial pass
Date: Thu, 1 Dec 2022 08:56:32 +0100 [thread overview]
Message-ID: <ee5253722c2a1e26b8bec3691166d7081538c7cb.1669881248.git.christophe.leroy@csgroup.eu> (raw)
In-Reply-To: <fa025537f584599c0271fc129c5cf4f57fbe7505.1669881248.git.christophe.leroy@csgroup.eu>
Now that two real additional passes are performed in case of extra pass
requested by BPF core, padding is not needed anymore except during
initial pass done before memory allocation to count maximum possible
program size.
So, only do the padding when 'image' is NULL.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/net/bpf_jit_comp32.c | 8 +++-----
arch/powerpc/net/bpf_jit_comp64.c | 12 +++++++-----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c
index 7c129fe810f5..6c45d953d4e8 100644
--- a/arch/powerpc/net/bpf_jit_comp32.c
+++ b/arch/powerpc/net/bpf_jit_comp32.c
@@ -206,9 +206,6 @@ int bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func
if (image && rel < 0x2000000 && rel >= -0x2000000) {
PPC_BL(func);
- EMIT(PPC_RAW_NOP());
- EMIT(PPC_RAW_NOP());
- EMIT(PPC_RAW_NOP());
} else {
/* Load function address into r0 */
EMIT(PPC_RAW_LIS(_R0, IMM_H(func)));
@@ -973,8 +970,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
PPC_LI32(dst_reg_h, (u32)insn[i + 1].imm);
PPC_LI32(dst_reg, (u32)insn[i].imm);
/* padding to allow full 4 instructions for later patching */
- for (j = ctx->idx - tmp_idx; j < 4; j++)
- EMIT(PPC_RAW_NOP());
+ if (!image)
+ for (j = ctx->idx - tmp_idx; j < 4; j++)
+ EMIT(PPC_RAW_NOP());
/* Adjust for two bpf instructions */
addrs[++i] = ctx->idx * 4;
break;
diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c
index 29ee306d6302..1c2931b4bc15 100644
--- a/arch/powerpc/net/bpf_jit_comp64.c
+++ b/arch/powerpc/net/bpf_jit_comp64.c
@@ -240,13 +240,14 @@ int bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func
* load the callee's address, but this may optimize the number of
* instructions required based on the nature of the address.
*
- * Since we don't want the number of instructions emitted to change,
+ * Since we don't want the number of instructions emitted to increase,
* we pad the optimized PPC_LI64() call with NOPs to guarantee that
* we always have a five-instruction sequence, which is the maximum
* that PPC_LI64() can emit.
*/
- for (i = ctx->idx - ctx_idx; i < 5; i++)
- EMIT(PPC_RAW_NOP());
+ if (!image)
+ for (i = ctx->idx - ctx_idx; i < 5; i++)
+ EMIT(PPC_RAW_NOP());
EMIT(PPC_RAW_MTCTR(_R12));
EMIT(PPC_RAW_BCTRL());
@@ -938,8 +939,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
tmp_idx = ctx->idx;
PPC_LI64(dst_reg, imm64);
/* padding to allow full 5 instructions for later patching */
- for (j = ctx->idx - tmp_idx; j < 5; j++)
- EMIT(PPC_RAW_NOP());
+ if (!image)
+ for (j = ctx->idx - tmp_idx; j < 5; j++)
+ EMIT(PPC_RAW_NOP());
/* Adjust for two bpf instructions */
addrs[++i] = ctx->idx * 4;
break;
--
2.38.1
next prev parent reply other threads:[~2022-12-01 7:57 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 7:56 [PATCH v1 01/10] powerpc/bpf/32: Fix Oops on tail call tests Christophe Leroy
2022-12-01 7:56 ` [PATCH v1 02/10] powerpc: Remove __kernel_text_address() in show_instructions() Christophe Leroy
2022-12-01 7:56 ` [PATCH v1 03/10] powerpc/bpf/32: No need to zeroise r4 when not doing tail call Christophe Leroy
2022-12-01 7:56 ` [PATCH v1 04/10] powerpc/bpf/32: Only set a stack frame when necessary Christophe Leroy
2022-12-01 7:56 ` [PATCH v1 05/10] powerpc/bpf/32: BPF prog is never called with more than one arg Christophe Leroy
2022-12-01 7:56 ` [PATCH v1 06/10] powerpc/bpf: Perform complete extra passes to update addresses Christophe Leroy
2022-12-13 10:23 ` Naveen N. Rao
2022-12-19 19:06 ` Christophe Leroy
2023-01-10 8:44 ` Naveen N. Rao
2023-01-31 9:52 ` Christophe Leroy
2022-12-01 7:56 ` Christophe Leroy [this message]
2022-12-01 7:56 ` [PATCH v1 08/10] powerpc/bpf/32: Optimise some particular const operations Christophe Leroy
2022-12-01 7:56 ` [PATCH v1 09/10] powerpc/bpf/32: introduce a second source register for ALU operations Christophe Leroy
2022-12-01 7:56 ` [PATCH v1 10/10] powerpc/bpf/32: perform three operands " Christophe Leroy
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