* [PATCH 2/2] hwmon: (k10temp): Load the driver on models A0h-AFh
2022-06-01 17:21 [PATCH 1/2] x86/amd_nb: Add AMD Family 19h A0-AF IDs Mario Limonciello
@ 2022-06-01 17:21 ` Mario Limonciello
2022-06-02 21:05 ` Guenter Roeck
2022-06-01 22:30 ` [PATCH 1/2] x86/amd_nb: Add AMD Family 19h A0-AF IDs Bjorn Helgaas
2022-06-07 12:56 ` Guenter Roeck
2 siblings, 1 reply; 7+ messages in thread
From: Mario Limonciello @ 2022-06-01 17:21 UTC (permalink / raw)
To: Clemens Ladisch, Jean Delvare, Guenter Roeck, Babu Moger,
open list:K10TEMP HARDWARE MONITORING DRIVER, open list
Cc: linux-hwmon, Gabriel Craciunescu, yazen.ghannam, linux-kernel,
x86, Mario Limonciello
commit 8bb050cd5cf4 ("hwmon: (k10temp) Support up to 12 CCDs on AMD
Family of processors") added the CCD offsets for models A0h-AFh but
didn't add the PCI device ID for the device.
Add the missing ID so the driver works on these models.
Fixes: 8bb050cd5cf4 ("hwmon: (k10temp) Support up to 12 CCDs on AMD Family of processors")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/hwmon/k10temp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index 4e239bd75b1d..80a489f89aa2 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -493,6 +493,7 @@ static const struct pci_device_id k10temp_id_table[] = {
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3) },
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
{}
};
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 2/2] hwmon: (k10temp): Load the driver on models A0h-AFh
2022-06-01 17:21 ` [PATCH 2/2] hwmon: (k10temp): Load the driver on models A0h-AFh Mario Limonciello
@ 2022-06-02 21:05 ` Guenter Roeck
0 siblings, 0 replies; 7+ messages in thread
From: Guenter Roeck @ 2022-06-02 21:05 UTC (permalink / raw)
To: Mario Limonciello, Clemens Ladisch, Jean Delvare, Babu Moger,
open list:K10TEMP HARDWARE MONITORING DRIVER, open list
Cc: Gabriel Craciunescu, yazen.ghannam, x86
On 6/1/22 10:21, Mario Limonciello wrote:
> commit 8bb050cd5cf4 ("hwmon: (k10temp) Support up to 12 CCDs on AMD
> Family of processors") added the CCD offsets for models A0h-AFh but
> didn't add the PCI device ID for the device.
>
> Add the missing ID so the driver works on these models.
>
> Fixes: 8bb050cd5cf4 ("hwmon: (k10temp) Support up to 12 CCDs on AMD Family of processors")
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
I can not apply this patch without the context patch (which I wasn't
copied on), so I assume the idea is to push this through the x86
tree. This is ok with me.
Acked-by: Guenter Roeck <linux@roeck-us.net>
> ---
> drivers/hwmon/k10temp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
> index 4e239bd75b1d..80a489f89aa2 100644
> --- a/drivers/hwmon/k10temp.c
> +++ b/drivers/hwmon/k10temp.c
> @@ -493,6 +493,7 @@ static const struct pci_device_id k10temp_id_table[] = {
> { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
> { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
> { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
> + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3) },
> { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
> {}
> };
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] x86/amd_nb: Add AMD Family 19h A0-AF IDs
2022-06-01 17:21 [PATCH 1/2] x86/amd_nb: Add AMD Family 19h A0-AF IDs Mario Limonciello
2022-06-01 17:21 ` [PATCH 2/2] hwmon: (k10temp): Load the driver on models A0h-AFh Mario Limonciello
@ 2022-06-01 22:30 ` Bjorn Helgaas
2022-06-01 23:47 ` Mario Limonciello
2022-06-07 12:56 ` Guenter Roeck
2 siblings, 1 reply; 7+ messages in thread
From: Bjorn Helgaas @ 2022-06-01 22:30 UTC (permalink / raw)
To: Mario Limonciello
Cc: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
H. Peter Anvin, Bjorn Helgaas, Guenter Roeck, Yazen Ghannam,
Krzysztof Wilczyński,
open list:X86 ARCHITECTURE (32-BIT AND 64-BIT),
open list:PCI SUBSYSTEM, linux-hwmon, Gabriel Craciunescu,
babu.moger
On Wed, Jun 01, 2022 at 12:21:18PM -0500, Mario Limonciello wrote:
> commit 4fb0abfee424 ("x86/amd_nb: Add AMD Family 19h Models (10h-1Fh)
> and (A0h-AFh) PCI IDs") had claimed to add the IDs for models A0h-AFh,
> but it appears to only have added the models 10h-1Fh.
>
> Add the actual IDs for A0-AF which are needed for SMN communication to
> work properly in amd_nb.
>
> Fixes: 4fb0abfee424 ("x86/amd_nb: Add AMD Family 19h Models (10h-1Fh) and (A0h-AFh) PCI IDs")
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
> arch/x86/kernel/amd_nb.c | 5 +++++
> include/linux/pci_ids.h | 1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
> index 190e0f763375..cc8c7cfa9068 100644
> --- a/arch/x86/kernel/amd_nb.c
> +++ b/arch/x86/kernel/amd_nb.c
> @@ -25,11 +25,13 @@
> #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
> #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
> #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
> +#define PCI_DEVICE_ID_AMD_19H_MA0H_ROOT 0x14b5
> #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
> #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
> #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
> #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
> #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
> +#define PCI_DEVICE_ID_AMD_19H_MA0H_DF_F4 0x1728
>
> /* Protect the PCI config register pairs used for SMN. */
> static DEFINE_MUTEX(smn_mutex);
> @@ -43,6 +45,7 @@ static const struct pci_device_id amd_root_ids[] = {
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
> + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_ROOT) },
> {}
> };
>
> @@ -67,6 +70,7 @@ static const struct pci_device_id amd_nb_misc_ids[] = {
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
> + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3) },
> {}
> };
>
> @@ -85,6 +89,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
> + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_DF_F4) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
> {}
> };
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 0178823ce8c2..05b4c67a8a2a 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -560,6 +560,7 @@
> #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 0x14b0
> #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 0x167c
> #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d
> +#define PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3 0x1727
This file is nominally sorted by numeric device ID inside the vendor
section, but that has really deteriorated over time.
I can't quite figure out the rationale for deciding whether to put
things in amd_nb.c vs pci_ids.h. The IDs in amd_nb.c look basically
the same as this one.
Normally we put things in pci_ids.h if they are used more than one
place. PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3 looks like it's only used in
one place.
> #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
> #define PCI_DEVICE_ID_AMD_LANCE 0x2000
> #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/2] x86/amd_nb: Add AMD Family 19h A0-AF IDs
2022-06-01 22:30 ` [PATCH 1/2] x86/amd_nb: Add AMD Family 19h A0-AF IDs Bjorn Helgaas
@ 2022-06-01 23:47 ` Mario Limonciello
2022-06-02 1:57 ` Bjorn Helgaas
0 siblings, 1 reply; 7+ messages in thread
From: Mario Limonciello @ 2022-06-01 23:47 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
H. Peter Anvin, Bjorn Helgaas, Guenter Roeck, Yazen Ghannam,
Krzysztof Wilczyński,
open list:X86 ARCHITECTURE (32-BIT AND 64-BIT),
open list:PCI SUBSYSTEM, linux-hwmon, Gabriel Craciunescu,
babu.moger
On 6/1/22 17:30, Bjorn Helgaas wrote:
> On Wed, Jun 01, 2022 at 12:21:18PM -0500, Mario Limonciello wrote:
>> commit 4fb0abfee424 ("x86/amd_nb: Add AMD Family 19h Models (10h-1Fh)
>> and (A0h-AFh) PCI IDs") had claimed to add the IDs for models A0h-AFh,
>> but it appears to only have added the models 10h-1Fh.
>>
>> Add the actual IDs for A0-AF which are needed for SMN communication to
>> work properly in amd_nb.
>>
>> Fixes: 4fb0abfee424 ("x86/amd_nb: Add AMD Family 19h Models (10h-1Fh) and (A0h-AFh) PCI IDs")
>> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
>> ---
>> arch/x86/kernel/amd_nb.c | 5 +++++
>> include/linux/pci_ids.h | 1 +
>> 2 files changed, 6 insertions(+)
>>
>> diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
>> index 190e0f763375..cc8c7cfa9068 100644
>> --- a/arch/x86/kernel/amd_nb.c
>> +++ b/arch/x86/kernel/amd_nb.c
>> @@ -25,11 +25,13 @@
>> #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
>> #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
>> #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
>> +#define PCI_DEVICE_ID_AMD_19H_MA0H_ROOT 0x14b5
>> #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
>> #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
>> #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
>> #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
>> #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
>> +#define PCI_DEVICE_ID_AMD_19H_MA0H_DF_F4 0x1728
>>
>> /* Protect the PCI config register pairs used for SMN. */
>> static DEFINE_MUTEX(smn_mutex);
>> @@ -43,6 +45,7 @@ static const struct pci_device_id amd_root_ids[] = {
>> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
>> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
>> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
>> + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_ROOT) },
>> {}
>> };
>>
>> @@ -67,6 +70,7 @@ static const struct pci_device_id amd_nb_misc_ids[] = {
>> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
>> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
>> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
>> + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3) },
>> {}
>> };
>>
>> @@ -85,6 +89,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
>> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
>> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
>> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
>> + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_DF_F4) },
>> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
>> {}
>> };
>> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
>> index 0178823ce8c2..05b4c67a8a2a 100644
>> --- a/include/linux/pci_ids.h
>> +++ b/include/linux/pci_ids.h
>> @@ -560,6 +560,7 @@
>> #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 0x14b0
>> #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 0x167c
>> #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d
>> +#define PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3 0x1727
>
> This file is nominally sorted by numeric device ID inside the vendor
> section, but that has really deteriorated over time.
It seemed like it was more oriented to be sorted by the macro definition
than the ID.
>
> I can't quite figure out the rationale for deciding whether to put
> things in amd_nb.c vs pci_ids.h. The IDs in amd_nb.c look basically
> the same as this one.
>
> Normally we put things in pci_ids.h if they are used more than one
> place. PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3 looks like it's only used in
> one place.
I suppose you weren't on CC for patch 2/2 in this series (thanks
scripts/get_maintainer.pl), so it's not obvious to you that this ID is
used in a second place in patch 2. I didn't want to ping pong in/out
from amd_nb.c in the series.
Here is a lore link to it:
https://lore.kernel.org/linux-kernel/20220601172121.18612-2-mario.limonciello@amd.com/
>
>> #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
>> #define PCI_DEVICE_ID_AMD_LANCE 0x2000
>> #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
>> --
>> 2.34.1
>>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/2] x86/amd_nb: Add AMD Family 19h A0-AF IDs
2022-06-01 23:47 ` Mario Limonciello
@ 2022-06-02 1:57 ` Bjorn Helgaas
0 siblings, 0 replies; 7+ messages in thread
From: Bjorn Helgaas @ 2022-06-02 1:57 UTC (permalink / raw)
To: Mario Limonciello
Cc: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
H. Peter Anvin, Bjorn Helgaas, Guenter Roeck, Yazen Ghannam,
Krzysztof Wilczyński,
open list:X86 ARCHITECTURE (32-BIT AND 64-BIT),
open list:PCI SUBSYSTEM, linux-hwmon, Gabriel Craciunescu,
babu.moger
On Wed, Jun 01, 2022 at 06:47:40PM -0500, Mario Limonciello wrote:
> On 6/1/22 17:30, Bjorn Helgaas wrote:
> > On Wed, Jun 01, 2022 at 12:21:18PM -0500, Mario Limonciello wrote:
> > > commit 4fb0abfee424 ("x86/amd_nb: Add AMD Family 19h Models (10h-1Fh)
> > > and (A0h-AFh) PCI IDs") had claimed to add the IDs for models A0h-AFh,
> > > but it appears to only have added the models 10h-1Fh.
> > >
> > > Add the actual IDs for A0-AF which are needed for SMN communication to
> > > work properly in amd_nb.
> > >
> > > Fixes: 4fb0abfee424 ("x86/amd_nb: Add AMD Family 19h Models (10h-1Fh) and (A0h-AFh) PCI IDs")
> > > Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> > > ---
> > > arch/x86/kernel/amd_nb.c | 5 +++++
> > > include/linux/pci_ids.h | 1 +
> > > 2 files changed, 6 insertions(+)
> > >
> > > diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
> > > index 190e0f763375..cc8c7cfa9068 100644
> > > --- a/arch/x86/kernel/amd_nb.c
> > > +++ b/arch/x86/kernel/amd_nb.c
> > > @@ -25,11 +25,13 @@
> > > #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
> > > #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
> > > #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
> > > +#define PCI_DEVICE_ID_AMD_19H_MA0H_ROOT 0x14b5
> > > #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
> > > #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
> > > #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
> > > #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
> > > #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
> > > +#define PCI_DEVICE_ID_AMD_19H_MA0H_DF_F4 0x1728
> > > /* Protect the PCI config register pairs used for SMN. */
> > > static DEFINE_MUTEX(smn_mutex);
> > > @@ -43,6 +45,7 @@ static const struct pci_device_id amd_root_ids[] = {
> > > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
> > > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
> > > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
> > > + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_ROOT) },
> > > {}
> > > };
> > > @@ -67,6 +70,7 @@ static const struct pci_device_id amd_nb_misc_ids[] = {
> > > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
> > > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
> > > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
> > > + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3) },
> > > {}
> > > };
> > > @@ -85,6 +89,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
> > > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
> > > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
> > > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
> > > + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_DF_F4) },
> > > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
> > > {}
> > > };
> > > diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> > > index 0178823ce8c2..05b4c67a8a2a 100644
> > > --- a/include/linux/pci_ids.h
> > > +++ b/include/linux/pci_ids.h
> > > @@ -560,6 +560,7 @@
> > > #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 0x14b0
> > > #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 0x167c
> > > #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d
> > > +#define PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3 0x1727
> >
> > This file is nominally sorted by numeric device ID inside the vendor
> > section, but that has really deteriorated over time.
>
> It seemed like it was more oriented to be sorted by the macro definition
> than the ID.
Yeah, it's kind of a mess. Not really clear which way.
> > I can't quite figure out the rationale for deciding whether to put
> > things in amd_nb.c vs pci_ids.h. The IDs in amd_nb.c look basically
> > the same as this one.
> >
> > Normally we put things in pci_ids.h if they are used more than one
> > place. PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3 looks like it's only used in
> > one place.
>
> I suppose you weren't on CC for patch 2/2 in this series (thanks
> scripts/get_maintainer.pl), so it's not obvious to you that this ID is used
> in a second place in patch 2. I didn't want to ping pong in/out from
> amd_nb.c in the series.
>
> Here is a lore link to it:
> https://lore.kernel.org/linux-kernel/20220601172121.18612-2-mario.limonciello@amd.com/
>
> >
> > > #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
> > > #define PCI_DEVICE_ID_AMD_LANCE 0x2000
> > > #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
> > > --
> > > 2.34.1
> > >
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] x86/amd_nb: Add AMD Family 19h A0-AF IDs
2022-06-01 17:21 [PATCH 1/2] x86/amd_nb: Add AMD Family 19h A0-AF IDs Mario Limonciello
2022-06-01 17:21 ` [PATCH 2/2] hwmon: (k10temp): Load the driver on models A0h-AFh Mario Limonciello
2022-06-01 22:30 ` [PATCH 1/2] x86/amd_nb: Add AMD Family 19h A0-AF IDs Bjorn Helgaas
@ 2022-06-07 12:56 ` Guenter Roeck
2 siblings, 0 replies; 7+ messages in thread
From: Guenter Roeck @ 2022-06-07 12:56 UTC (permalink / raw)
To: Mario Limonciello
Cc: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
H. Peter Anvin, Bjorn Helgaas, Yazen Ghannam,
Krzysztof Wilczyński,
open list:X86 ARCHITECTURE (32-BIT AND 64-BIT),
open list:PCI SUBSYSTEM, linux-hwmon, Gabriel Craciunescu,
babu.moger
On Wed, Jun 01, 2022 at 12:21:18PM -0500, Mario Limonciello wrote:
> commit 4fb0abfee424 ("x86/amd_nb: Add AMD Family 19h Models (10h-1Fh)
> and (A0h-AFh) PCI IDs") had claimed to add the IDs for models A0h-AFh,
> but it appears to only have added the models 10h-1Fh.
>
> Add the actual IDs for A0-AF which are needed for SMN communication to
> work properly in amd_nb.
>
> Fixes: 4fb0abfee424 ("x86/amd_nb: Add AMD Family 19h Models (10h-1Fh) and (A0h-AFh) PCI IDs")
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> arch/x86/kernel/amd_nb.c | 5 +++++
I'll need an Ack from a x86 maintainer to apply this series,
or it needs to be applied through x86. I sent an Ack for patch 2/2,
so the latter would be fine with me.
Thanks,
Guenter
> include/linux/pci_ids.h | 1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
> index 190e0f763375..cc8c7cfa9068 100644
> --- a/arch/x86/kernel/amd_nb.c
> +++ b/arch/x86/kernel/amd_nb.c
> @@ -25,11 +25,13 @@
> #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
> #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
> #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
> +#define PCI_DEVICE_ID_AMD_19H_MA0H_ROOT 0x14b5
> #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
> #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
> #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
> #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
> #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
> +#define PCI_DEVICE_ID_AMD_19H_MA0H_DF_F4 0x1728
>
> /* Protect the PCI config register pairs used for SMN. */
> static DEFINE_MUTEX(smn_mutex);
> @@ -43,6 +45,7 @@ static const struct pci_device_id amd_root_ids[] = {
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
> + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_ROOT) },
> {}
> };
>
> @@ -67,6 +70,7 @@ static const struct pci_device_id amd_nb_misc_ids[] = {
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
> + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3) },
> {}
> };
>
> @@ -85,6 +89,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
> + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_MA0H_DF_F4) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
> {}
> };
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 0178823ce8c2..05b4c67a8a2a 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -560,6 +560,7 @@
> #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 0x14b0
> #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 0x167c
> #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d
> +#define PCI_DEVICE_ID_AMD_19H_MA0H_DF_F3 0x1727
> #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
> #define PCI_DEVICE_ID_AMD_LANCE 0x2000
> #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
^ permalink raw reply [flat|nested] 7+ messages in thread