From: Heiner Kallweit <hkallweit1@gmail.com>
To: DENG Qingfang <dqfext@gmail.com>
Cc: "David S. Miller" <davem@davemloft.net>,
"Andrew Lunn" <andrew@lunn.ch>,
"Florian Fainelli" <f.fainelli@gmail.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Landen Chao" <Landen.Chao@mediatek.com>,
"Marc Zyngier" <maz@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Russell King" <linux@armlinux.org.uk>,
"Sean Wang" <sean.wang@mediatek.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Vivien Didelot" <vivien.didelot@gmail.com>,
"Vladimir Oltean" <olteanv@gmail.com>,
linux-kernel@vger.kernel.org, netdev <netdev@vger.kernel.org>,
"Weijie Gao" <weijie.gao@mediatek.com>,
"Chuanhong Guo" <gch981213@gmail.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"René van Dorst" <opensource@vdorst.com>
Subject: Re: Registering IRQ for MT7530 internal PHYs
Date: Wed, 30 Dec 2020 10:12:03 +0100 [thread overview]
Message-ID: <fa7951e1-4a98-8488-d724-3eda9b97e376@gmail.com> (raw)
In-Reply-To: <CALW65jbV-RwbmmiGjfq8P-ZcApOW0YyN6Ez5FvhhP4dgaA+VjQ@mail.gmail.com>
On 30.12.2020 10:07, DENG Qingfang wrote:
> Hi Heiner,
> Thanks for your reply.
>
> On Wed, Dec 30, 2020 at 3:39 PM Heiner Kallweit <hkallweit1@gmail.com> wrote:
>> I don't think that's the best option.
>
> I'm well aware of that.
>
>> You may want to add a PHY driver for your chip. Supposedly it
>> supports at least PHY suspend/resume. You can use the RTL8366RB
>> PHY driver as template.
>
> There's no MediaTek PHY driver yet. Do we really need a new one just
> for the interrupts?
>
Not only for the interrupts. The genphy driver e.g. doesn't support
PHY suspend/resume. And the PHY driver needs basically no code,
just set the proper callbacks.
>>> + dev_info_ratelimited(priv->dev, "interrupt status: 0x%08x\n", val);
>>> + dev_info_ratelimited(priv->dev, "interrupt enable: 0x%08x\n", mt7530_read(priv, MT7530_SYS_INT_EN));
>>> +
>> This is debug code to be removed in the final version?
>
> Yes.
>
>>> + for (phy = 0; phy < MT7530_NUM_PHYS; phy++) {
>>> + if (val & BIT(phy)) {
>>> + unsigned int child_irq;
>>> +
>>> + child_irq = irq_find_mapping(priv->irq_domain, phy);
>>> + handle_nested_irq(child_irq);
>>> + handled = true;
>>> + }
>>> + }
>>> +
>>> + return handled ? IRQ_HANDLED : IRQ_NONE;
>>
>> IRQ_RETVAL() could be used here.
>
> Good to know :)
>
>>
>>> +}
>>> +
>>> +static void mt7530_irq_mask(struct irq_data *d)
>>> +{
>>> + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
>>> +
>>> + priv->irq_enable &= ~BIT(d->hwirq);
>>
>> Here you don't actually do something. HW doesn't support masking
>> interrupt generation for a port?
>
> priv->irq_enable will be written to MT7530_SYS_INT_EN in
> mt7530_irq_bus_sync_unlock. You can think of it as an inverted mask.
>
next prev parent reply other threads:[~2020-12-30 9:13 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-30 4:22 Registering IRQ for MT7530 internal PHYs DENG Qingfang
2020-12-30 7:39 ` Heiner Kallweit
2020-12-30 9:07 ` DENG Qingfang
2020-12-30 9:12 ` Heiner Kallweit [this message]
2020-12-30 16:15 ` Florian Fainelli
2020-12-30 16:53 ` Heiner Kallweit
2020-12-30 9:42 ` Marc Zyngier
2020-12-30 15:11 ` Andrew Lunn
2020-12-30 15:23 ` Andrew Lunn
2021-01-06 8:54 ` DENG Qingfang
2021-01-18 13:27 ` Landen Chao
2020-12-30 15:16 ` Andrew Lunn
2020-12-30 16:17 ` Florian Fainelli
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