linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Palmer Dabbelt <palmer@dabbelt.com>
To: Atish Patra <Atish.Patra@wdc.com>
Cc: linux-kernel@vger.kernel.org, Atish Patra <Atish.Patra@wdc.com>,
	aou@eecs.berkeley.edu,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <Anup.Patel@wdc.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	robh+dt@kernel.org, padmarao.begari@microchip.com,
	daire.mcnamara@microchip.com, Cyril.Jean@microchip.com
Subject: Re: [RFC PATCH 0/3] Add Microchip PolarFire Soc Support
Date: Thu, 05 Nov 2020 23:14:36 -0800 (PST)	[thread overview]
Message-ID: <mhng-3a4619db-fe42-4ae0-a521-4032f23591ee@palmerdabbelt-glaptop1> (raw)
In-Reply-To: <20201028232759.1928479-1-atish.patra@wdc.com>

On Wed, 28 Oct 2020 16:27:56 PDT (-0700), Atish Patra wrote:
> This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
> It is rebased on v5.10-rc1 and depends on clock support.
> Only MMC and ethernet drivers are enabled via this series.
> The idea here is to add the foundational patches so that other drivers
> can be added to on top of this.
>
> This series has been tested on Qemu and Polar Fire Soc Icicle kit.
> The following qemu series is necessary to test it on Qemu.
>
> The series can also be found at the following github repo.
>
> I noticed the latest version of mmc driver[2] hangs on the board with
> the latest clock driver. That's why, I have tested with the old clock
> driver available in the above github repo.

OK, I guess that's why it's an RFC?

> [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html
> [2] https://www.spinics.net/lists/devicetree/msg383626.html

Looks like this one hasn't been merged yet.  IDK if something is broken with my
mail client but I'm not seeing any github repos.  If this depends on
not-yet-merged drivers then it's certainly RFC material, but aside from the DT
stuff (which should be straight-forward) it seems fine to me.

Since you posted this an an RFC I'm going to assume you're going to re-spin it.

Thanks!

>
> Atish Patra (3):
> RISC-V: Add Microchip PolarFire SoC kconfig option
> RISC-V: Initial DTS for Microchip ICICLE board
> RISC-V: Enable Microchip PolarFire ICICLE SoC
>
> arch/riscv/Kconfig.socs                       |   7 +
> arch/riscv/boot/dts/Makefile                  |   1 +
> arch/riscv/boot/dts/microchip/Makefile        |   2 +
> .../microchip/microchip-icicle-kit-a000.dts   | 313 ++++++++++++++++++
> arch/riscv/configs/defconfig                  |   4 +
> 5 files changed, 327 insertions(+)
> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts

  parent reply	other threads:[~2020-11-06  7:14 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-28 23:27 [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Atish Patra
2020-10-28 23:27 ` [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
2020-10-30  9:08   ` Anup Patel
2020-11-03  9:55   ` Bin Meng
2020-11-06  7:14   ` Palmer Dabbelt
2020-10-28 23:27 ` [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
2020-10-29 10:24   ` Ben Dooks
2020-10-30  7:11     ` Atish Patra
2020-10-30 21:19       ` Ben Dooks
2020-11-03 15:07         ` Atish Patra
2020-11-03 15:19           ` Ben Dooks
2020-11-03 18:10           ` Cyril.Jean
2020-11-03 18:28             ` Ben Dooks
2020-11-03 18:36               ` Atish Patra
2020-11-03 18:39                 ` Ben Dooks
2020-11-03 18:45                   ` Atish Patra
2020-11-03 18:40               ` Cyril.Jean
2020-11-03 18:46                 ` Ben Dooks
2020-11-04  2:41     ` Bin Meng
2020-10-30  9:05   ` Anup Patel
2020-10-30 20:27     ` Atish Patra
2020-11-03 10:59       ` Ben Dooks
2020-11-03 15:08         ` Atish Patra
2020-10-30 21:20     ` Ben Dooks
2020-11-03 10:00     ` Bin Meng
2020-11-03 18:19       ` Cyril.Jean
2020-11-03 18:38         ` Atish Patra
2020-11-03 18:50           ` Cyril.Jean
2020-11-03 19:02             ` Atish Patra
2020-11-06  7:14   ` Palmer Dabbelt
2020-10-28 23:27 ` [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
2020-10-30  9:09   ` Anup Patel
2020-10-30 21:21     ` Ben Dooks
2020-11-03 10:03   ` Bin Meng
2020-11-06  7:14   ` Palmer Dabbelt
2020-11-06  7:14 ` Palmer Dabbelt [this message]
2020-11-06  7:37   ` [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Atish Patra
2020-11-06  8:11     ` Palmer Dabbelt

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=mhng-3a4619db-fe42-4ae0-a521-4032f23591ee@palmerdabbelt-glaptop1 \
    --to=palmer@dabbelt.com \
    --cc=Alistair.Francis@wdc.com \
    --cc=Anup.Patel@wdc.com \
    --cc=Atish.Patra@wdc.com \
    --cc=Cyril.Jean@microchip.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=daire.mcnamara@microchip.com \
    --cc=devicetree@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=padmarao.begari@microchip.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).