[PATCH 00/12] Initial support for Nuclei DemoSoC w/ UX600

[PATCH 00/12] Initial support for Nuclei DemoSoC w/ UX600

[Icenowy Zheng]

This patchset adds support for Nuclei DemoSoC (which is an evaluation
platform made with Nuclei CPU cores and mainly peripherals in original
Hummingbird E203 project, running on FPGA) with UX600 CPU cores.

Most patches are for DT bindings, the remaining ones are adding a
Kconfig option and some DTS/DTSI files. The last one is a workaround for
a severe bug in currently released versions of UX600, which is found
in 5.17 kernel, in which Sv48 support is added to Linux.

Two non-technical patches are in this patchset too, for MAINTAINERS
and .mailmap items.

Icenowy Zheng (12):
  dt-bindings: vendor-prefixes: add Nuclei
  RISC-V: add Nuclei SoC Kconfig option
  dt-bindings: riscv: add compatible strings for Nuclei UX600 series
  dt-bindings: timer: add compatible for Nuclei UX600 CLINT-compat timer
  dt-bindings: interrupt-controller: add compatible string for UX600
    PLIC
  dt-bindings: serial: add compatible string for Nuclei DemoSoC UART
  dt-bindings: spi: add compatible string for Nuclei DemoSoC SPI
  dt-bindings: riscv: add binding for Nuclei platform boards
  riscv: dts: add device tree for Nuclei DemoSoC w/ UX600 on DDR200T
  RISC-V: workaround Nuclei UX600 cores with broken SATP CSR
  MAINTAINERS: add myself as Nuclei SoCs/CPUs supporter
  mailmap: add Icenowy Zheng's Nuclei mail addresses

 .mailmap                                      |  1 +
 .../sifive,plic-1.0.0.yaml                    |  1 +
 .../devicetree/bindings/riscv/cpus.yaml       |  7 ++
 .../devicetree/bindings/riscv/nuclei.yaml     | 27 ++++++++
 .../bindings/serial/sifive-serial.yaml        |  1 +
 .../devicetree/bindings/spi/spi-sifive.yaml   |  1 +
 .../bindings/timer/sifive,clint.yaml          |  1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
 MAINTAINERS                                   |  7 ++
 arch/riscv/Kconfig.socs                       |  6 ++
 arch/riscv/boot/dts/Makefile                  |  1 +
 arch/riscv/boot/dts/nuclei/Makefile           |  2 +
 .../dts/nuclei/nuclei-demosoc-ddr200t.dtsi    | 41 ++++++++++++
 .../nuclei/nuclei-demosoc-ux600-ddr200t.dts   | 13 ++++
 .../boot/dts/nuclei/nuclei-demosoc-ux600.dtsi | 49 ++++++++++++++
 .../riscv/boot/dts/nuclei/nuclei-demosoc.dtsi | 67 +++++++++++++++++++
 arch/riscv/include/asm/vendorid_list.h        |  1 +
 arch/riscv/mm/init.c                          | 17 +++++
 18 files changed, 245 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/nuclei.yaml
 create mode 100644 arch/riscv/boot/dts/nuclei/Makefile
 create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ddr200t.dtsi
 create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-ddr200t.dts
 create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600.dtsi
 create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi

-- 
2.30.2

[PATCH 01/12] dt-bindings: vendor-prefixes: add Nuclei

[Icenowy Zheng]

Nuclei System Technology is a RISC-V CPU IP core vendor.

Add vendor prefix for it.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 294093d45a23..8d786367b093 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -842,6 +842,8 @@ patternProperties:
     description: Nordic Semiconductor
   "^novtech,.*":
     description: NovTech, Inc.
+  "^nuclei,.*":
+    description: Nuclei System Technology
   "^nutsboard,.*":
     description: NutsBoard
   "^nuvoton,.*":
-- 
2.30.2

Re: [PATCH 01/12] dt-bindings: vendor-prefixes: add Nuclei

[Rob Herring]

On Thu, 27 Jan 2022 23:16:36 +0800, Icenowy Zheng wrote:
> Nuclei System Technology is a RISC-V CPU IP core vendor.
> 
> Add vendor prefix for it.
> 
> Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 02/12] RISC-V: add Nuclei SoC Kconfig option

[Icenowy Zheng]

As a CPU core vendor, Nuclei has some "DemoSoCs" that uses Nuclei CPU
cores and modified peripherals from Hummingbird E203.

Add a Kconfig option for this.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 arch/riscv/Kconfig.socs | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6ec44a22278a..e4488ac8c72b 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -7,6 +7,12 @@ config SOC_MICROCHIP_POLARFIRE
 	help
 	  This enables support for Microchip PolarFire SoC platforms.
 
+config SOC_NUCLEI
+	bool "Nuclei SoCs"
+	select SIFIVE_PLIC
+	help
+	  This enables support for Nuclei SoC platform hardware.
+
 config SOC_SIFIVE
 	bool "SiFive SoCs"
 	select SERIAL_SIFIVE if TTY
-- 
2.30.2

[PATCH 03/12] dt-bindings: riscv: add compatible strings for Nuclei UX600 series

[Icenowy Zheng]

Nuclei UX600 series are 64-bit, MMU-equipped CPUs, which can run Linux.

Add compatible strings for these CPU cores.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index aa5fb64d57eb..f50f5c3dcc06 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -45,6 +45,13 @@ properties:
               - sifive,u54-mc
           - const: sifive,rocket0
           - const: riscv
+      - items:
+          - enum:
+              - nuclei,ux605
+              - nuclei,ux607
+              - nuclei,ux608
+          - const: nuclei,ux600
+          - const: riscv
       - const: riscv    # Simulator only
     description:
       Identifies that the hart uses the RISC-V instruction set
-- 
2.30.2

Re: [PATCH 03/12] dt-bindings: riscv: add compatible strings for Nuclei UX600 series

[Rob Herring]

On Thu, 27 Jan 2022 23:16:38 +0800, Icenowy Zheng wrote:
> Nuclei UX600 series are 64-bit, MMU-equipped CPUs, which can run Linux.
> 
> Add compatible strings for these CPU cores.
> 
> Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 04/12] dt-bindings: timer: add compatible for Nuclei UX600 CLINT-compat timer

[Icenowy Zheng]

Nuclei UX600's timer has a part which is compatible with CLINT.

Add a DT compatible string for it.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 8d5f4687add9..61a8bd8bde91 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -27,6 +27,7 @@ properties:
           - sifive,fu540-c000-clint
           - starfive,jh7100-clint
           - canaan,k210-clint
+          - nuclei,ux600-clint
       - const: sifive,clint0
 
     description:
-- 
2.30.2

Re: [PATCH 04/12] dt-bindings: timer: add compatible for Nuclei UX600 CLINT-compat timer

[Rob Herring]

On Thu, 27 Jan 2022 23:16:39 +0800, Icenowy Zheng wrote:
> Nuclei UX600's timer has a part which is compatible with CLINT.
> 
> Add a DT compatible string for it.
> 
> Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 05/12] dt-bindings: interrupt-controller: add compatible string for UX600 PLIC

[Icenowy Zheng]

Nuclei UX600 series CPU has an optional PLIC (recommended when running
Linux).

Add a compatible string for it.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 28b6b17fe4b2..70f5bd6cb879 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -47,6 +47,7 @@ properties:
           - sifive,fu540-c000-plic
           - starfive,jh7100-plic
           - canaan,k210-plic
+          - nuclei,ux600-plic
       - const: sifive,plic-1.0.0
 
   reg:
-- 
2.30.2

Re: [PATCH 05/12] dt-bindings: interrupt-controller: add compatible string for UX600 PLIC

[Rob Herring]

On Thu, 27 Jan 2022 23:16:40 +0800, Icenowy Zheng wrote:
> Nuclei UX600 series CPU has an optional PLIC (recommended when running
> Linux).
> 
> Add a compatible string for it.
> 
> Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
> ---
>  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 06/12] dt-bindings: serial: add compatible string for Nuclei DemoSoC UART

[Icenowy Zheng]

Nuclei DemoSoC design integrates the UART controller from SiFive.

Add a compatible string for it.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 Documentation/devicetree/bindings/serial/sifive-serial.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
index 09aae43f65a7..329341a3648f 100644
--- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml
+++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
@@ -21,6 +21,7 @@ properties:
           - sifive,fu540-c000-uart
           - sifive,fu740-c000-uart
           - canaan,k210-uarths
+          - nuclei,demosoc-uart
       - const: sifive,uart0
 
     description:
-- 
2.30.2

Re: [PATCH 06/12] dt-bindings: serial: add compatible string for Nuclei DemoSoC UART

[Rob Herring]

On Thu, 27 Jan 2022 23:16:41 +0800, Icenowy Zheng wrote:
> Nuclei DemoSoC design integrates the UART controller from SiFive.
> 
> Add a compatible string for it.
> 
> Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
> ---
>  Documentation/devicetree/bindings/serial/sifive-serial.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 07/12] dt-bindings: spi: add compatible string for Nuclei DemoSoC SPI

[Icenowy Zheng]

Nuclei DemoSoC design integrates SPI controllers from SiFive.

Add a compatible string for these SPI controllers.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 Documentation/devicetree/bindings/spi/spi-sifive.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
index 6e7e394fc1e4..60a24f31a928 100644
--- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
@@ -20,6 +20,7 @@ properties:
       - enum:
           - sifive,fu540-c000-spi
           - sifive,fu740-c000-spi
+          - nuclei,demosoc-spi
       - const: sifive,spi0
 
     description:
-- 
2.30.2

Re: [PATCH 07/12] dt-bindings: spi: add compatible string for Nuclei DemoSoC SPI

[Rob Herring]

On Thu, 27 Jan 2022 23:16:42 +0800, Icenowy Zheng wrote:
> Nuclei DemoSoC design integrates SPI controllers from SiFive.
> 
> Add a compatible string for these SPI controllers.
> 
> Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
> ---
>  Documentation/devicetree/bindings/spi/spi-sifive.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 08/12] dt-bindings: riscv: add binding for Nuclei platform boards

[Icenowy Zheng]

As we added support for RISC-V SoCs from Nuclei, add device tree binding
for the currently supported board-bitstream combo (DemoSoC with UX600 on
DDR200T board).

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 .../devicetree/bindings/riscv/nuclei.yaml     | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/nuclei.yaml

diff --git a/Documentation/devicetree/bindings/riscv/nuclei.yaml b/Documentation/devicetree/bindings/riscv/nuclei.yaml
new file mode 100644
index 000000000000..4760568c7bde
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/nuclei.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/nuclei.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuclei SoC-based boards
+
+maintainers:
+  - Icenowy Zheng <icenowy@nucleisys.com>
+
+description:
+  Nuclei SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - const: nuclei,demosoc-ux600-ddr200t
+          - const: nuclei,demosoc-ux600
+          - const: nuclei,demosoc
+
+additionalProperties: true
+
+...
-- 
2.30.2

Re: [PATCH 08/12] dt-bindings: riscv: add binding for Nuclei platform boards

[Rob Herring]

On Thu, 27 Jan 2022 23:16:43 +0800, Icenowy Zheng wrote:
> As we added support for RISC-V SoCs from Nuclei, add device tree binding
> for the currently supported board-bitstream combo (DemoSoC with UX600 on
> DDR200T board).
> 
> Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
> ---
>  .../devicetree/bindings/riscv/nuclei.yaml     | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/nuclei.yaml
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 09/12] riscv: dts: add device tree for Nuclei DemoSoC w/ UX600 on DDR200T

[Icenowy Zheng]

As we're supporting Nuclei DemoSoC for UX600 CPU cores on DDR200T FPGA
prototyping board, add device tree files for it, including DTSI files
for basic DemoSoC structure, DemoSoC with UX600 and DemoSoC running on
DDR200T for further reusing.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 arch/riscv/boot/dts/Makefile                  |  1 +
 arch/riscv/boot/dts/nuclei/Makefile           |  2 +
 .../dts/nuclei/nuclei-demosoc-ddr200t.dtsi    | 41 ++++++++++++
 .../nuclei/nuclei-demosoc-ux600-ddr200t.dts   | 13 ++++
 .../boot/dts/nuclei/nuclei-demosoc-ux600.dtsi | 49 ++++++++++++++
 .../riscv/boot/dts/nuclei/nuclei-demosoc.dtsi | 67 +++++++++++++++++++
 6 files changed, 173 insertions(+)
 create mode 100644 arch/riscv/boot/dts/nuclei/Makefile
 create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ddr200t.dtsi
 create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-ddr200t.dts
 create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600.dtsi
 create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..fd31084986da 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,5 +3,6 @@ subdir-y += sifive
 subdir-y += starfive
 subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
 subdir-y += microchip
+subdir-y += nuclei
 
 obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/nuclei/Makefile b/arch/riscv/boot/dts/nuclei/Makefile
new file mode 100644
index 000000000000..57970aabf01d
--- /dev/null
+++ b/arch/riscv/boot/dts/nuclei/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_NUCLEI) += nuclei-demosoc-ux600-ddr200t.dtb
diff --git a/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ddr200t.dtsi b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ddr200t.dtsi
new file mode 100644
index 000000000000..4f44c6b564bb
--- /dev/null
+++ b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ddr200t.dtsi
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Nuclei System Technology */
+
+/ {
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@a0000000 {
+		device_type = "memory";
+		reg = <0xa0000000 0xe000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	spi_nor: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <8000000>;
+	};
+};
+
+&qspi2 {
+	status = "okay";
+
+	spi_mmc: mmc@0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		spi-max-frequency = <8000000>;
+	};
+};
diff --git a/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-ddr200t.dts b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-ddr200t.dts
new file mode 100644
index 000000000000..cd15ec2c1376
--- /dev/null
+++ b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-ddr200t.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Nuclei System Technology */
+
+/dts-v1/;
+
+#include "nuclei-demosoc-ux600.dtsi"
+#include "nuclei-demosoc-ddr200t.dtsi"
+
+/ {
+	model = "Nuclei DemoSoC with UX600 on DDR200T";
+	compatible = "nuclei,demosoc-ux600-ddr200t",
+		     "nuclei,demosoc-ux600", "nuclei,demosoc";
+};
diff --git a/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600.dtsi b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600.dtsi
new file mode 100644
index 000000000000..f3588907ce3f
--- /dev/null
+++ b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Nuclei System Technology */
+
+#include "nuclei-demosoc.dtsi"
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		/* The counting clock of the timer is the LF clock */
+		timebase-frequency = <32768>;
+
+		cpu0: cpu@0 {
+			compatible = "nuclei,ux607", "nuclei,ux600", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			clock-frequency = <16000000>;
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	clint: clint@2001000 {
+		compatible = "nuclei,ux600-clint", "sifive,clint0";
+		reg = <0x02001000 0xc000>;
+		interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+	};
+
+	plic: plic@8000000 {
+		compatible = "nuclei,ux600-plic", "sifive,plic-1.0.0";
+		reg = <0x08000000 0x4000000>;
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		interrupts-extended =
+			<&cpu0_intc 11>, <&cpu0_intc 9>;
+		riscv,ndev = <52>;
+	};
+};
+
+&ppi {
+	interrupt-parent = <&plic>;
+};
diff --git a/arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi b/arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi
new file mode 100644
index 000000000000..85a4f713d3d9
--- /dev/null
+++ b/arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Nuclei System Technology */
+
+/ {
+	/*
+	 * Nuclei DemoSoC is a 32-bit design even if 64-bit CPU core is
+	 * integrated into it.
+	 */
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	clocks {
+		/* For most of the SoC */
+		hfclk: hfclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <16000000>;
+		};
+
+		/* For always-on zone */
+		lfclk: lfclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
+	/*
+	 * The interrupt controller and all peripherals' interrupt parent
+	 * are to be defined in individual CPU cores' DemoSoC DT.
+	 */
+	ppi: ppi {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: serial@10010000 {
+			compatible = "nuclei,demosoc-uart", "sifive,uart0";
+			reg = <0x10013000 0x1000>;
+			clocks = <&hfclk>;
+			interrupts = <33>;
+			status = "disabled";
+		};
+
+		qspi0: spi@10014000 {
+			compatible = "nuclei,demosoc-spi", "sifive,spi0";
+			reg = <0x10014000 0x1000>,
+			      <0x20000000 0x20000000>;
+			interrupts = <35>;
+			clocks = <&hfclk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		qspi2: spi@10034000 {
+			compatible = "nuclei,demosoc-spi", "sifive,spi0";
+			reg = <0x10034000 0x1000>;
+			interrupts = <37>;
+			clocks = <&hfclk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.30.2

[PATCH 10/12] RISC-V: workaround Nuclei UX600 cores with broken SATP CSR

[Icenowy Zheng]

Current release of Nuclei UX600 CPU cores have two errata against RISC-V
Privledged Specification 1.10: one is left over mvendorid value (not the
JEDEC ID), the other, which is a more breaking one that needs to be
workaround in software, is that satp will accept written value with
MODE=9 (Sv48, which is not supported by UX600), and silently change it
to MODE=8 (Sv39). As current kernel MMU initialization code relies on
the behavior defined on the spec (reject write request with unsupported
MODE value and do not change the CSR's value at all) to detect the
existence of Sv48, the erratum breaks the Sv48 detection code.

As both two errata are to be fixed in the next revision, use the first
to detect the existence of the second at runtime, and force Sv39 when
these errata are detected.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 arch/riscv/include/asm/vendorid_list.h |  1 +
 arch/riscv/mm/init.c                   | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index 9d934215b3c8..47ff43795d70 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -6,5 +6,6 @@
 #define ASM_VENDOR_LIST_H
 
 #define SIFIVE_VENDOR_ID	0x489
+#define NUCLEI_OLD_VENDOR_ID	0x2d33
 
 #endif
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index cf4d018b7d66..0085b14ae265 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -28,6 +28,8 @@
 #include <asm/io.h>
 #include <asm/ptdump.h>
 #include <asm/numa.h>
+#include <asm/sbi.h>
+#include <asm/vendorid_list.h>
 
 #include "../kernel/head.h"
 
@@ -591,6 +593,21 @@ static __init void set_satp_mode(void)
 	u64 identity_satp, hw_satp;
 	uintptr_t set_satp_mode_pmd;
 
+	if (sbi_get_mvendorid() == NUCLEI_OLD_VENDOR_ID) {
+		/*
+		 * Old Nuclei UX600 processor releases have broken
+		 * implementation of SATP register which prevents
+		 * proper runtime detection of Sv48 existence. In
+		 * addition these processor releases have an old
+		 * vendor id instead of proper JEDEC ID.
+		 *
+		 * As these releases do not support Sv48 at all,
+		 * force Sv39 on them.
+		 */
+		disable_pgtable_l4();
+		return;
+	}
+
 	set_satp_mode_pmd = ((unsigned long)set_satp_mode) & PMD_MASK;
 	create_pgd_mapping(early_pg_dir,
 			   set_satp_mode_pmd, (uintptr_t)early_pud,
-- 
2.30.2

[PATCH 11/12] MAINTAINERS: add myself as Nuclei SoCs/CPUs supporter

[Icenowy Zheng]

Currently I am working on mainlining Nuclei SoCs/CPUs Linux support.

Add myself as a supporter of this.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index ea3e6c914384..499450d14625 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13733,6 +13733,13 @@ F:	drivers/nubus/
 F:	include/linux/nubus.h
 F:	include/uapi/linux/nubus.h
 
+NUCLEI RISCV CORES AND SOCS
+M:	Icenowy Zheng <icenowy@nucleisys.com>
+L:	linux-riscv@lists.infradead.org
+S:	Supported
+N:	nuclei
+K:	[^@]nuclei
+
 NVIDIA (rivafb and nvidiafb) FRAMEBUFFER DRIVER
 M:	Antonino Daplas <adaplas@gmail.com>
 L:	linux-fbdev@vger.kernel.org
-- 
2.30.2

[PATCH 12/12] mailmap: add Icenowy Zheng's Nuclei mail addresses

[Icenowy Zheng]

A mail address is assigned to Icenowy under @nucleisys.com for
supporting Nuclei SoCs/CPUs in Linux (and other open source projects).

Add it to the .mailmap file.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 .mailmap | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.mailmap b/.mailmap
index b157f88ce26a..4bacaef7b06d 100644
--- a/.mailmap
+++ b/.mailmap
@@ -144,6 +144,7 @@ Henrik Rydberg <rydberg@bitmath.org>
 Herbert Xu <herbert@gondor.apana.org.au>
 Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
 Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
+Icenowy Zheng <icenowy@aosc.io> <icenowy@nucleisys.com>
 Jacob Shin <Jacob.Shin@amd.com>
 Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@google.com>
 Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk.kim@samsung.com>
-- 
2.30.2

Re: [PATCH 00/12] Initial support for Nuclei DemoSoC w/ UX600

[Icenowy Zheng]

在 2022-01-27星期四的 23:16 +0800，Icenowy Zheng写道：
> This patchset adds support for Nuclei DemoSoC (which is an evaluation
> platform made with Nuclei CPU cores and mainly peripherals in
> original
> Hummingbird E203 project, running on FPGA) with UX600 CPU cores.
> 
> Most patches are for DT bindings, the remaining ones are adding a
> Kconfig option and some DTS/DTSI files. The last one is a workaround
> for
> a severe bug in currently released versions of UX600, which is found
> in 5.17 kernel, in which Sv48 support is added to Linux.
> 
> Two non-technical patches are in this patchset too, for MAINTAINERS
> and .mailmap items.

Ping, could any RISC-V maintainers review these patches, especially the
SATP workaround one?

> 
> Icenowy Zheng (12):
>   dt-bindings: vendor-prefixes: add Nuclei
>   RISC-V: add Nuclei SoC Kconfig option
>   dt-bindings: riscv: add compatible strings for Nuclei UX600 series
>   dt-bindings: timer: add compatible for Nuclei UX600 CLINT-compat
> timer
>   dt-bindings: interrupt-controller: add compatible string for UX600
>     PLIC
>   dt-bindings: serial: add compatible string for Nuclei DemoSoC UART
>   dt-bindings: spi: add compatible string for Nuclei DemoSoC SPI
>   dt-bindings: riscv: add binding for Nuclei platform boards
>   riscv: dts: add device tree for Nuclei DemoSoC w/ UX600 on DDR200T
>   RISC-V: workaround Nuclei UX600 cores with broken SATP CSR
>   MAINTAINERS: add myself as Nuclei SoCs/CPUs supporter
>   mailmap: add Icenowy Zheng's Nuclei mail addresses
> 
>  .mailmap                                      |  1 +
>  .../sifive,plic-1.0.0.yaml                    |  1 +
>  .../devicetree/bindings/riscv/cpus.yaml       |  7 ++
>  .../devicetree/bindings/riscv/nuclei.yaml     | 27 ++++++++
>  .../bindings/serial/sifive-serial.yaml        |  1 +
>  .../devicetree/bindings/spi/spi-sifive.yaml   |  1 +
>  .../bindings/timer/sifive,clint.yaml          |  1 +
>  .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
>  MAINTAINERS                                   |  7 ++
>  arch/riscv/Kconfig.socs                       |  6 ++
>  arch/riscv/boot/dts/Makefile                  |  1 +
>  arch/riscv/boot/dts/nuclei/Makefile           |  2 +
>  .../dts/nuclei/nuclei-demosoc-ddr200t.dtsi    | 41 ++++++++++++
>  .../nuclei/nuclei-demosoc-ux600-ddr200t.dts   | 13 ++++
>  .../boot/dts/nuclei/nuclei-demosoc-ux600.dtsi | 49 ++++++++++++++
>  .../riscv/boot/dts/nuclei/nuclei-demosoc.dtsi | 67
> +++++++++++++++++++
>  arch/riscv/include/asm/vendorid_list.h        |  1 +
>  arch/riscv/mm/init.c                          | 17 +++++
>  18 files changed, 245 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/riscv/nuclei.yaml
>  create mode 100644 arch/riscv/boot/dts/nuclei/Makefile
>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-
> ddr200t.dtsi
>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-
> ddr200t.dts
>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-
> ux600.dtsi
>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi
> 

Re: [PATCH 00/12] Initial support for Nuclei DemoSoC w/ UX600

[Palmer Dabbelt]

On Sat, 19 Feb 2022 06:45:43 PST (-0800), icenowy@nucleisys.com wrote:
> 在 2022-01-27星期四的 23:16 +0800，Icenowy Zheng写道：
>> This patchset adds support for Nuclei DemoSoC (which is an evaluation
>> platform made with Nuclei CPU cores and mainly peripherals in
>> original
>> Hummingbird E203 project, running on FPGA) with UX600 CPU cores.
>>
>> Most patches are for DT bindings, the remaining ones are adding a
>> Kconfig option and some DTS/DTSI files. The last one is a workaround
>> for
>> a severe bug in currently released versions of UX600, which is found
>> in 5.17 kernel, in which Sv48 support is added to Linux.
>>
>> Two non-technical patches are in this patchset too, for MAINTAINERS
>> and .mailmap items.
>
> Ping, could any RISC-V maintainers review these patches, especially the
> SATP workaround one?

Sorry, I remember having written this but I guess it got lost.  IIRC my 
main worry here was that, at least as far as I can tell, DemoSOC is an 
FPGA development board.  If this is actually in production somewhere 
then it's a different story, but IIUC the general rule is not to accept 
code for development hardware that can be updated.

Assuming DemoSOC can be updated, I'd also argue that we should have some 
sort of version attached to it in DT entries.  Without some versioning 
we'll end up lost when trying to later determine what we're actually 
running on.

As far as the errata goes: it looks fine to me, but I'd like to see some 
sort of description of what the errata actually is (ie, some 
documentation from the manufacturer).  I know that's not always 
possible, but without some desciption of what the bug is it gets tricky 
to mainain this sort of stuff.  For example: we've got sv57 patches 
now, so how do I know what to do with them on this target?

>
>>
>> Icenowy Zheng (12):
>>   dt-bindings: vendor-prefixes: add Nuclei
>>   RISC-V: add Nuclei SoC Kconfig option
>>   dt-bindings: riscv: add compatible strings for Nuclei UX600 series
>>   dt-bindings: timer: add compatible for Nuclei UX600 CLINT-compat
>> timer
>>   dt-bindings: interrupt-controller: add compatible string for UX600
>>     PLIC
>>   dt-bindings: serial: add compatible string for Nuclei DemoSoC UART
>>   dt-bindings: spi: add compatible string for Nuclei DemoSoC SPI
>>   dt-bindings: riscv: add binding for Nuclei platform boards
>>   riscv: dts: add device tree for Nuclei DemoSoC w/ UX600 on DDR200T
>>   RISC-V: workaround Nuclei UX600 cores with broken SATP CSR
>>   MAINTAINERS: add myself as Nuclei SoCs/CPUs supporter
>>   mailmap: add Icenowy Zheng's Nuclei mail addresses
>>
>>  .mailmap                                      |  1 +
>>  .../sifive,plic-1.0.0.yaml                    |  1 +
>>  .../devicetree/bindings/riscv/cpus.yaml       |  7 ++
>>  .../devicetree/bindings/riscv/nuclei.yaml     | 27 ++++++++
>>  .../bindings/serial/sifive-serial.yaml        |  1 +
>>  .../devicetree/bindings/spi/spi-sifive.yaml   |  1 +
>>  .../bindings/timer/sifive,clint.yaml          |  1 +
>>  .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
>>  MAINTAINERS                                   |  7 ++
>>  arch/riscv/Kconfig.socs                       |  6 ++
>>  arch/riscv/boot/dts/Makefile                  |  1 +
>>  arch/riscv/boot/dts/nuclei/Makefile           |  2 +
>>  .../dts/nuclei/nuclei-demosoc-ddr200t.dtsi    | 41 ++++++++++++
>>  .../nuclei/nuclei-demosoc-ux600-ddr200t.dts   | 13 ++++
>>  .../boot/dts/nuclei/nuclei-demosoc-ux600.dtsi | 49 ++++++++++++++
>>  .../riscv/boot/dts/nuclei/nuclei-demosoc.dtsi | 67
>> +++++++++++++++++++
>>  arch/riscv/include/asm/vendorid_list.h        |  1 +
>>  arch/riscv/mm/init.c                          | 17 +++++
>>  18 files changed, 245 insertions(+)
>>  create mode 100644
>> Documentation/devicetree/bindings/riscv/nuclei.yaml
>>  create mode 100644 arch/riscv/boot/dts/nuclei/Makefile
>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-
>> ddr200t.dtsi
>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-
>> ddr200t.dts
>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-
>> ux600.dtsi
>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi
>>

Re: [PATCH 00/12] Initial support for Nuclei DemoSoC w/ UX600

[Palmer Dabbelt]

On Tue, 22 Feb 2022 08:56:42 PST (-0800), Palmer Dabbelt wrote:
> On Sat, 19 Feb 2022 06:45:43 PST (-0800), icenowy@nucleisys.com wrote:
>> 在 2022-01-27星期四的 23:16 +0800，Icenowy Zheng写道：
>>> This patchset adds support for Nuclei DemoSoC (which is an evaluation
>>> platform made with Nuclei CPU cores and mainly peripherals in
>>> original
>>> Hummingbird E203 project, running on FPGA) with UX600 CPU cores.
>>>
>>> Most patches are for DT bindings, the remaining ones are adding a
>>> Kconfig option and some DTS/DTSI files. The last one is a workaround
>>> for
>>> a severe bug in currently released versions of UX600, which is found
>>> in 5.17 kernel, in which Sv48 support is added to Linux.
>>>
>>> Two non-technical patches are in this patchset too, for MAINTAINERS
>>> and .mailmap items.
>>
>> Ping, could any RISC-V maintainers review these patches, especially the
>> SATP workaround one?
>
> Sorry, I remember having written this but I guess it got lost.  IIRC my
> main worry here was that, at least as far as I can tell, DemoSOC is an
> FPGA development board.  If this is actually in production somewhere
> then it's a different story, but IIUC the general rule is not to accept
> code for development hardware that can be updated.
>
> Assuming DemoSOC can be updated, I'd also argue that we should have some
> sort of version attached to it in DT entries.  Without some versioning
> we'll end up lost when trying to later determine what we're actually
> running on.
>
> As far as the errata goes: it looks fine to me, but I'd like to see some
> sort of description of what the errata actually is (ie, some
> documentation from the manufacturer).  I know that's not always
> possible, but without some desciption of what the bug is it gets tricky
> to mainain this sort of stuff.  For example: we've got sv57 patches
> now, so how do I know what to do with them on this target?

Just following up on this one.  Not sure if I missed it, but I can't 
find a reply.

>
>>
>>>
>>> Icenowy Zheng (12):
>>>   dt-bindings: vendor-prefixes: add Nuclei
>>>   RISC-V: add Nuclei SoC Kconfig option
>>>   dt-bindings: riscv: add compatible strings for Nuclei UX600 series
>>>   dt-bindings: timer: add compatible for Nuclei UX600 CLINT-compat
>>> timer
>>>   dt-bindings: interrupt-controller: add compatible string for UX600
>>>     PLIC
>>>   dt-bindings: serial: add compatible string for Nuclei DemoSoC UART
>>>   dt-bindings: spi: add compatible string for Nuclei DemoSoC SPI
>>>   dt-bindings: riscv: add binding for Nuclei platform boards
>>>   riscv: dts: add device tree for Nuclei DemoSoC w/ UX600 on DDR200T
>>>   RISC-V: workaround Nuclei UX600 cores with broken SATP CSR
>>>   MAINTAINERS: add myself as Nuclei SoCs/CPUs supporter
>>>   mailmap: add Icenowy Zheng's Nuclei mail addresses
>>>
>>>  .mailmap                                      |  1 +
>>>  .../sifive,plic-1.0.0.yaml                    |  1 +
>>>  .../devicetree/bindings/riscv/cpus.yaml       |  7 ++
>>>  .../devicetree/bindings/riscv/nuclei.yaml     | 27 ++++++++
>>>  .../bindings/serial/sifive-serial.yaml        |  1 +
>>>  .../devicetree/bindings/spi/spi-sifive.yaml   |  1 +
>>>  .../bindings/timer/sifive,clint.yaml          |  1 +
>>>  .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
>>>  MAINTAINERS                                   |  7 ++
>>>  arch/riscv/Kconfig.socs                       |  6 ++
>>>  arch/riscv/boot/dts/Makefile                  |  1 +
>>>  arch/riscv/boot/dts/nuclei/Makefile           |  2 +
>>>  .../dts/nuclei/nuclei-demosoc-ddr200t.dtsi    | 41 ++++++++++++
>>>  .../nuclei/nuclei-demosoc-ux600-ddr200t.dts   | 13 ++++
>>>  .../boot/dts/nuclei/nuclei-demosoc-ux600.dtsi | 49 ++++++++++++++
>>>  .../riscv/boot/dts/nuclei/nuclei-demosoc.dtsi | 67
>>> +++++++++++++++++++
>>>  arch/riscv/include/asm/vendorid_list.h        |  1 +
>>>  arch/riscv/mm/init.c                          | 17 +++++
>>>  18 files changed, 245 insertions(+)
>>>  create mode 100644
>>> Documentation/devicetree/bindings/riscv/nuclei.yaml
>>>  create mode 100644 arch/riscv/boot/dts/nuclei/Makefile
>>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-
>>> ddr200t.dtsi
>>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-
>>> ddr200t.dts
>>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-
>>> ux600.dtsi
>>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi
>>>

Re: [PATCH 00/12] Initial support for Nuclei DemoSoC w/ UX600

[Palmer Dabbelt]

On Mon, 21 Mar 2022 17:05:45 PDT (-0700), Palmer Dabbelt wrote:
> On Tue, 22 Feb 2022 08:56:42 PST (-0800), Palmer Dabbelt wrote:
>> On Sat, 19 Feb 2022 06:45:43 PST (-0800), icenowy@nucleisys.com wrote:
>>> 在 2022-01-27星期四的 23:16 +0800，Icenowy Zheng写道：
>>>> This patchset adds support for Nuclei DemoSoC (which is an evaluation
>>>> platform made with Nuclei CPU cores and mainly peripherals in
>>>> original
>>>> Hummingbird E203 project, running on FPGA) with UX600 CPU cores.
>>>>
>>>> Most patches are for DT bindings, the remaining ones are adding a
>>>> Kconfig option and some DTS/DTSI files. The last one is a workaround
>>>> for
>>>> a severe bug in currently released versions of UX600, which is found
>>>> in 5.17 kernel, in which Sv48 support is added to Linux.
>>>>
>>>> Two non-technical patches are in this patchset too, for MAINTAINERS
>>>> and .mailmap items.
>>>
>>> Ping, could any RISC-V maintainers review these patches, especially the
>>> SATP workaround one?
>>
>> Sorry, I remember having written this but I guess it got lost.  IIRC my
>> main worry here was that, at least as far as I can tell, DemoSOC is an
>> FPGA development board.  If this is actually in production somewhere
>> then it's a different story, but IIUC the general rule is not to accept
>> code for development hardware that can be updated.
>>
>> Assuming DemoSOC can be updated, I'd also argue that we should have some
>> sort of version attached to it in DT entries.  Without some versioning
>> we'll end up lost when trying to later determine what we're actually
>> running on.
>>
>> As far as the errata goes: it looks fine to me, but I'd like to see some
>> sort of description of what the errata actually is (ie, some
>> documentation from the manufacturer).  I know that's not always
>> possible, but without some desciption of what the bug is it gets tricky
>> to mainain this sort of stuff.  For example: we've got sv57 patches
>> now, so how do I know what to do with them on this target?
>
> Just following up on this one.  Not sure if I missed it, but I can't
> find a reply.

Checking up on this one more time, I still can't find any replies.  It's 
at the top of my queue, but I'm going to drop it until the questions get 
resolved.

>
>>
>>>
>>>>
>>>> Icenowy Zheng (12):
>>>>   dt-bindings: vendor-prefixes: add Nuclei
>>>>   RISC-V: add Nuclei SoC Kconfig option
>>>>   dt-bindings: riscv: add compatible strings for Nuclei UX600 series
>>>>   dt-bindings: timer: add compatible for Nuclei UX600 CLINT-compat
>>>> timer
>>>>   dt-bindings: interrupt-controller: add compatible string for UX600
>>>>     PLIC
>>>>   dt-bindings: serial: add compatible string for Nuclei DemoSoC UART
>>>>   dt-bindings: spi: add compatible string for Nuclei DemoSoC SPI
>>>>   dt-bindings: riscv: add binding for Nuclei platform boards
>>>>   riscv: dts: add device tree for Nuclei DemoSoC w/ UX600 on DDR200T
>>>>   RISC-V: workaround Nuclei UX600 cores with broken SATP CSR
>>>>   MAINTAINERS: add myself as Nuclei SoCs/CPUs supporter
>>>>   mailmap: add Icenowy Zheng's Nuclei mail addresses
>>>>
>>>>  .mailmap                                      |  1 +
>>>>  .../sifive,plic-1.0.0.yaml                    |  1 +
>>>>  .../devicetree/bindings/riscv/cpus.yaml       |  7 ++
>>>>  .../devicetree/bindings/riscv/nuclei.yaml     | 27 ++++++++
>>>>  .../bindings/serial/sifive-serial.yaml        |  1 +
>>>>  .../devicetree/bindings/spi/spi-sifive.yaml   |  1 +
>>>>  .../bindings/timer/sifive,clint.yaml          |  1 +
>>>>  .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
>>>>  MAINTAINERS                                   |  7 ++
>>>>  arch/riscv/Kconfig.socs                       |  6 ++
>>>>  arch/riscv/boot/dts/Makefile                  |  1 +
>>>>  arch/riscv/boot/dts/nuclei/Makefile           |  2 +
>>>>  .../dts/nuclei/nuclei-demosoc-ddr200t.dtsi    | 41 ++++++++++++
>>>>  .../nuclei/nuclei-demosoc-ux600-ddr200t.dts   | 13 ++++
>>>>  .../boot/dts/nuclei/nuclei-demosoc-ux600.dtsi | 49 ++++++++++++++
>>>>  .../riscv/boot/dts/nuclei/nuclei-demosoc.dtsi | 67
>>>> +++++++++++++++++++
>>>>  arch/riscv/include/asm/vendorid_list.h        |  1 +
>>>>  arch/riscv/mm/init.c                          | 17 +++++
>>>>  18 files changed, 245 insertions(+)
>>>>  create mode 100644
>>>> Documentation/devicetree/bindings/riscv/nuclei.yaml
>>>>  create mode 100644 arch/riscv/boot/dts/nuclei/Makefile
>>>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-
>>>> ddr200t.dtsi
>>>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-
>>>> ddr200t.dts
>>>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-
>>>> ux600.dtsi
>>>>  create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi
>>>>