[PATCH v1 0/2] vpopcntdq support

[PATCH v1 0/2] vpopcntdq support

[Piotr Luc]

Hi,

This patchset adds the support for new CPUID feature bit that announces the
vector population count instructions for dwords and qwords.

The path 1/2 adds new feature flags and handles clearing the feature bit in
case xsave is not enabled.

The patch 2/2 enables passing the feature bit to a kvm/quemu guest.

The patchset is based on v4.10-rc3.

Regards,
Piotr

Piotr Luc (2):
  x86/cpufeature: Add AVX512_VPOPCNTDQ feature
  kvm: x86: Expose Intel VPOPCNTDQ feature to guest

 arch/x86/include/asm/cpufeatures.h       | 2 +-
 arch/x86/kernel/fpu/xstate.c             | 1 +
 arch/x86/kvm/cpuid.c                     | 2 +-
 tools/arch/x86/include/asm/cpufeatures.h | 1 +
 4 files changed, 4 insertions(+), 2 deletions(-)

-- 
2.10.1

[PATCH v1 1/2] x86/cpufeature: Add AVX512_VPOPCNTDQ feature

[Piotr Luc]

Vector population count instructions for dwords and qwords are to be
used in future Intel Xeon & Xeon Phi processors. The bit 14 of
CPUID[level:0x07, ECX] indicates that the new instructions are
supported by a processor.

The spec can be found in the Intel Software Developer Manual (SDM)
or in the Instruction Set Extensions Programming Reference (ISE).

Define new feature flag to enumerate the new instructions set in
/proc/cpuinfo according to new CPUID bit.
Clear the feature bit in case xsave is disabled.

Signed-off-by: Piotr Luc <piotr.luc@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
---
 arch/x86/include/asm/cpufeatures.h       | 2 +-
 arch/x86/kernel/fpu/xstate.c             | 1 +
 tools/arch/x86/include/asm/cpufeatures.h | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index eafee31..19a1e10 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -288,6 +288,7 @@
 #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
 #define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */
 #define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */
+#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
 #define X86_FEATURE_RDPID	(16*32+ 22) /* RDPID instruction */
 
 /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
@@ -320,5 +321,4 @@
 #define X86_BUG_SWAPGS_FENCE	X86_BUG(11) /* SWAPGS without input dep on GS */
 #define X86_BUG_MONITOR		X86_BUG(12) /* IPI required to wake up remote CPU */
 #define X86_BUG_AMD_E400	X86_BUG(13) /* CPU is among the affected by Erratum 400 */
-
 #endif /* _ASM_X86_CPUFEATURES_H */
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index 1d77704..35f7024 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -78,6 +78,7 @@ void fpu__xstate_clear_all_cpu_caps(void)
 	setup_clear_cpu_cap(X86_FEATURE_PKU);
 	setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW);
 	setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS);
+	setup_clear_cpu_cap(X86_FEATURE_AVX512_VPOPCNTDQ);
 }
 
 /*
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index cddd5d0..f44ec38 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -280,6 +280,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */
 #define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */
 #define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */
+#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
 
 /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
 #define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */
-- 
2.10.1

[PATCH v1 2/2] kvm: x86: Expose Intel VPOPCNTDQ feature to guest

[Piotr Luc]

Vector population count instructions for dwords and qwords are to be
used in future Intel Xeon & Xeon Phi processors. The bit 14 of
CPUID[level:0x07, ECX] indicates that the new instructions are
supported by a processor.

The spec can be found in the Intel Software Developer Manual (SDM)
or in the Instruction Set Extensions Programming Reference (ISE).

Signed-off-by: Piotr Luc <piotr.luc@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: x86@kernel.org
Cc: kvm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 arch/x86/kvm/cpuid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index e85f6bd..09c2ac7 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -383,7 +383,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 
 	/* cpuid 7.0.ecx*/
 	const u32 kvm_cpuid_7_0_ecx_x86_features =
-		F(AVX512VBMI) | F(PKU) | 0 /*OSPKE*/;
+		F(AVX512VBMI) | F(PKU) | 0 /*OSPKE*/ | F(AVX512_VPOPCNTDQ);
 
 	/* cpuid 7.0.edx*/
 	const u32 kvm_cpuid_7_0_edx_x86_features =
-- 
2.10.1

Re: [PATCH v1 0/2] vpopcntdq support

[Paolo Bonzini]

On 10/01/2017 18:34, Piotr Luc wrote:
> Hi,
> 
> This patchset adds the support for new CPUID feature bit that announces the
> vector population count instructions for dwords and qwords.
> 
> The path 1/2 adds new feature flags and handles clearing the feature bit in
> case xsave is not enabled.
> 
> The patch 2/2 enables passing the feature bit to a kvm/quemu guest.
> 
> The patchset is based on v4.10-rc3.

Thanks.  I can use a topic branch for patch 1 to apply patch 2.

Regards,

Paolo

> Regards,
> Piotr
> 
> Piotr Luc (2):
>   x86/cpufeature: Add AVX512_VPOPCNTDQ feature
>   kvm: x86: Expose Intel VPOPCNTDQ feature to guest
> 
>  arch/x86/include/asm/cpufeatures.h       | 2 +-
>  arch/x86/kernel/fpu/xstate.c             | 1 +
>  arch/x86/kvm/cpuid.c                     | 2 +-
>  tools/arch/x86/include/asm/cpufeatures.h | 1 +
>  4 files changed, 4 insertions(+), 2 deletions(-)
> 

Re: [PATCH v1 0/2] vpopcntdq support

[Luc, Piotr]

On Tue, 2017-01-10 at 18:39 +0100, Paolo Bonzini wrote:
> > The path 1/2 adds new feature flags and handles clearing the
> > feature bit in
> > case xsave is not enabled.
> > 
> > The patch 2/2 enables passing the feature bit to a kvm/quemu guest.
> > 
> > The patchset is based on v4.10-rc3.
> 
> Thanks.  I can use a topic branch for patch 1 to apply patch 2.

OK, let's wait for path 1 to be picked up.

Regards,
Piotr

> 
> Regards,
> 
> Paolo

Re: [PATCH v1 1/2] x86/cpufeature: Add AVX512_VPOPCNTDQ feature

[Borislav Petkov]

On Tue, Jan 10, 2017 at 06:34:02PM +0100, Piotr Luc wrote:
> Vector population count instructions for dwords and qwords are to be
> used in future Intel Xeon & Xeon Phi processors. The bit 14 of
> CPUID[level:0x07, ECX] indicates that the new instructions are
> supported by a processor.
> 
> The spec can be found in the Intel Software Developer Manual (SDM)
> or in the Instruction Set Extensions Programming Reference (ISE).
> 
> Define new feature flag to enumerate the new instructions set in
> /proc/cpuinfo according to new CPUID bit.
> Clear the feature bit in case xsave is disabled.
> 
> Signed-off-by: Piotr Luc <piotr.luc@intel.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: H. Peter Anvin <hpa@zytor.com>
> Cc: x86@kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---

Reviewed-by: Borislav Petkov <bp@suse.de>

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

[tip:x86/cpufeature] x86/cpufeature: Add AVX512_VPOPCNTDQ feature

[tip-bot for Piotr Luc]

Commit-ID:  06b35d93af0a5904aa832f58733be84ddbfe2e04
Gitweb:     http://git.kernel.org/tip/06b35d93af0a5904aa832f58733be84ddbfe2e04
Author:     Piotr Luc <piotr.luc@intel.com>
AuthorDate: Tue, 10 Jan 2017 18:34:02 +0100
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Mon, 16 Jan 2017 20:40:53 +0100

x86/cpufeature: Add AVX512_VPOPCNTDQ feature

Vector population count instructions for dwords and qwords are going to be
available in future Intel Xeon & Xeon Phi processors. Bit 14 of
CPUID[level:0x07, ECX] indicates that the instructions are supported by a
processor.

The specification can be found in the Intel Software Developer Manual (SDM)
and in the Instruction Set Extensions Programming Reference (ISE).

Populate the feature bit and clear it when xsave is disabled.

Signed-off-by: Piotr Luc <piotr.luc@intel.com>
Reviewed-by: Borislav Petkov <bp@suse.de>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org
Cc: Radim Krčmář <rkrcmar@redhat.com>
Link: http://lkml.kernel.org/r/20170110173403.6010-2-piotr.luc@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

---
 arch/x86/include/asm/cpufeatures.h       | 2 +-
 arch/x86/kernel/fpu/xstate.c             | 1 +
 tools/arch/x86/include/asm/cpufeatures.h | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index eafee31..d9d7136 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -288,6 +288,7 @@
 #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
 #define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */
 #define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */
+#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
 #define X86_FEATURE_RDPID	(16*32+ 22) /* RDPID instruction */
 
 /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
@@ -320,5 +321,4 @@
 #define X86_BUG_SWAPGS_FENCE	X86_BUG(11) /* SWAPGS without input dep on GS */
 #define X86_BUG_MONITOR		X86_BUG(12) /* IPI required to wake up remote CPU */
 #define X86_BUG_AMD_E400	X86_BUG(13) /* CPU is among the affected by Erratum 400 */
-
 #endif /* _ASM_X86_CPUFEATURES_H */
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index 1d77704..35f7024 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -78,6 +78,7 @@ void fpu__xstate_clear_all_cpu_caps(void)
 	setup_clear_cpu_cap(X86_FEATURE_PKU);
 	setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW);
 	setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS);
+	setup_clear_cpu_cap(X86_FEATURE_AVX512_VPOPCNTDQ);
 }
 
 /*
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index cddd5d0..3603556 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -280,6 +280,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */
 #define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */
 #define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */
+#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
 
 /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
 #define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */

Re: [PATCH v1 0/2] vpopcntdq support

[Thomas Gleixner]

Paolo,

On Tue, 10 Jan 2017, Paolo Bonzini wrote:
> On 10/01/2017 18:34, Piotr Luc wrote:
> > Hi,
> > 
> > This patchset adds the support for new CPUID feature bit that announces the
> > vector population count instructions for dwords and qwords.
> > 
> > The path 1/2 adds new feature flags and handles clearing the feature bit in
> > case xsave is not enabled.
> > 
> > The patch 2/2 enables passing the feature bit to a kvm/quemu guest.
> > 
> > The patchset is based on v4.10-rc3.
> 
> Thanks.  I can use a topic branch for patch 1 to apply patch 2.

  git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/cpufeature

contains that patch now (nothing else for now):

	 06b35d93af0a: x86/cpufeature: Add AVX512_VPOPCNTDQ feature

So you can pull that into your tree as a base for the other one.

Thanks,

	tglx

Re: [PATCH v1 2/2] kvm: x86: Expose Intel VPOPCNTDQ feature to guest

[Radim Krčmář]

2017-01-10 18:34+0100, Piotr Luc:
> Vector population count instructions for dwords and qwords are to be
> used in future Intel Xeon & Xeon Phi processors. The bit 14 of
> CPUID[level:0x07, ECX] indicates that the new instructions are
> supported by a processor.
> 
> The spec can be found in the Intel Software Developer Manual (SDM)
> or in the Instruction Set Extensions Programming Reference (ISE).
> 
> Signed-off-by: Piotr Luc <piotr.luc@intel.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Radim Krčmář <rkrcmar@redhat.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: H. Peter Anvin <hpa@zytor.com>
> Cc: x86@kernel.org
> Cc: kvm@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---

Applied on top of tglx's branch in kvm/next,
thanks to both.