* [PATCH 1/1] x86/cpu/intel: enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
@ 2015-10-08 15:56 Andy Shevchenko
2015-10-11 19:12 ` [tip:x86/cpufeature] x86/cpu/intel: Enable " tip-bot for Andy Shevchenko
2015-11-07 9:42 ` [tip:x86/urgent] " tip-bot for Andy Shevchenko
0 siblings, 2 replies; 3+ messages in thread
From: Andy Shevchenko @ 2015-10-08 15:56 UTC (permalink / raw)
To: linux-kernel, Thomas Gleixner, Ingo Molnar, H. Peter Anvin, x86
Cc: Andy Shevchenko
The Intel Merrifield SoC is a successor of the Intel MID line of SoCs. Let's
set the neccessary capability for that chip. See commit c54fdbb2823d (x86: Add
cpu capability flag X86_FEATURE_NONSTOP_TSC_S3) for the details.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/kernel/cpu/intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 98a13db..209ac1e 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -97,6 +97,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
switch (c->x86_model) {
case 0x27: /* Penwell */
case 0x35: /* Cloverview */
+ case 0x4a: /* Merrifield */
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
break;
default:
--
2.5.3
^ permalink raw reply related [flat|nested] 3+ messages in thread* [tip:x86/cpufeature] x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
2015-10-08 15:56 [PATCH 1/1] x86/cpu/intel: enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield Andy Shevchenko
@ 2015-10-11 19:12 ` tip-bot for Andy Shevchenko
2015-11-07 9:42 ` [tip:x86/urgent] " tip-bot for Andy Shevchenko
1 sibling, 0 replies; 3+ messages in thread
From: tip-bot for Andy Shevchenko @ 2015-10-11 19:12 UTC (permalink / raw)
To: linux-tip-commits; +Cc: mingo, tglx, hpa, linux-kernel, andriy.shevchenko
Commit-ID: 1cc0166752d598a69f6bb99381d828cbfb5fa9a5
Gitweb: http://git.kernel.org/tip/1cc0166752d598a69f6bb99381d828cbfb5fa9a5
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Thu, 8 Oct 2015 18:56:26 +0300
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Sun, 11 Oct 2015 21:07:26 +0200
x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
The Intel Merrifield SoC is a successor of the Intel MID line of
SoCs. Let's set the neccessary capability for that chip. See commit
c54fdbb2823d (x86: Add cpu capability flag X86_FEATURE_NONSTOP_TSC_S3)
for the details.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: http://lkml.kernel.org/r/1444319786-36125-1-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/kernel/cpu/intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 98a13db..209ac1e 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -97,6 +97,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
switch (c->x86_model) {
case 0x27: /* Penwell */
case 0x35: /* Cloverview */
+ case 0x4a: /* Merrifield */
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
break;
default:
^ permalink raw reply related [flat|nested] 3+ messages in thread* [tip:x86/urgent] x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
2015-10-08 15:56 [PATCH 1/1] x86/cpu/intel: enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield Andy Shevchenko
2015-10-11 19:12 ` [tip:x86/cpufeature] x86/cpu/intel: Enable " tip-bot for Andy Shevchenko
@ 2015-11-07 9:42 ` tip-bot for Andy Shevchenko
1 sibling, 0 replies; 3+ messages in thread
From: tip-bot for Andy Shevchenko @ 2015-11-07 9:42 UTC (permalink / raw)
To: linux-tip-commits; +Cc: linux-kernel, hpa, andriy.shevchenko, tglx, mingo
Commit-ID: 354dbaa7ff5b53a0ed1c0f7a9773d5953b3a1bb9
Gitweb: http://git.kernel.org/tip/354dbaa7ff5b53a0ed1c0f7a9773d5953b3a1bb9
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Thu, 8 Oct 2015 18:56:26 +0300
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Sat, 7 Nov 2015 10:37:30 +0100
x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
The Intel Merrifield SoC is a successor of the Intel MID line of
SoCs. Let's set the neccessary capability for that chip. See commit
c54fdbb2823d (x86: Add cpu capability flag X86_FEATURE_NONSTOP_TSC_S3)
for the details.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: http://lkml.kernel.org/r/1444319786-36125-1-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/kernel/cpu/intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 98a13db..209ac1e 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -97,6 +97,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
switch (c->x86_model) {
case 0x27: /* Penwell */
case 0x35: /* Cloverview */
+ case 0x4a: /* Merrifield */
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
break;
default:
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2015-11-07 9:43 UTC | newest]
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