* [PATCH 0/3] x86/CPU: Report correct cpu/cache topo for Centaur CPUs and some minor changes
@ 2018-05-03 2:32 David Wang
2018-05-03 2:32 ` [PATCH 1/3] x86/CPU: Replace intel_num_cpu_cores with detect_num_cpu_cores David Wang
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: David Wang @ 2018-05-03 2:32 UTC (permalink / raw)
To: tglx, mingo, hpa, gregkh, x86, linux-kernel
Cc: brucechang, cooperyan, qiyuanwang, benjaminpan, lukelin, timguo,
David Wang
There are three patches:
The first patch define detect_num_cpu_cores() in common.c to replace the
original intel_num_cpu_cores() which is defined in intel.c;
The second patch is used to include the legacy cpu_detect_cache_sizes()
into the init_intel_cacheinfo() function;
The third patch is used to report correct CPU/Cache topology by using the
functions defined in the first and the second patch;
David Wang (3):
x86/CPU: Replace intel_num_cpu_cores with detect_num_cpu_cores
x86/cpu/intel_cacheinfo: include cpu_detect_cache_size in
init_intel_cacheinfo
x86/Centaur: Report correct CPU/cache topology
arch/x86/include/asm/processor.h | 1 +
arch/x86/kernel/cpu/centaur.c | 5 +++++
arch/x86/kernel/cpu/common.c | 14 ++++++++++++++
arch/x86/kernel/cpu/intel.c | 28 ++--------------------------
arch/x86/kernel/cpu/intel_cacheinfo.c | 6 ++++++
5 files changed, 28 insertions(+), 26 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/3] x86/CPU: Replace intel_num_cpu_cores with detect_num_cpu_cores 2018-05-03 2:32 [PATCH 0/3] x86/CPU: Report correct cpu/cache topo for Centaur CPUs and some minor changes David Wang @ 2018-05-03 2:32 ` David Wang 2018-05-13 12:01 ` [tip:x86/cpu] x86/CPU: Make intel_num_cpu_cores() generic tip-bot for David Wang 2018-05-03 2:32 ` [PATCH 2/3] x86/cpu: Include cpu_detect_cache_sizes in init_intel_cacheinfo David Wang 2018-05-03 2:32 ` [PATCH 3/3] x86/Centaur: Report correct CPU/cache topology David Wang 2 siblings, 1 reply; 9+ messages in thread From: David Wang @ 2018-05-03 2:32 UTC (permalink / raw) To: tglx, mingo, hpa, gregkh, x86, linux-kernel Cc: brucechang, cooperyan, qiyuanwang, benjaminpan, lukelin, timguo, David Wang intel_num_cpu_cores() is a static defination in intel.c which can't be used by other files. Define another function called detect_num_cpu_cores() in common.c to replace this function. Signed-off-by: David Wang <davidwang@zhaoxin.com> --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/common.c | 14 ++++++++++++++ arch/x86/kernel/cpu/intel.c | 20 +------------------- 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index e56fe7c..b0553f6 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -192,6 +192,7 @@ extern u32 get_scattered_cpuid_leaf(unsigned int level, enum cpuid_regs_idx reg); extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); +extern int detect_num_cpu_cores(struct cpuinfo_x86 *c); extern void detect_extended_topology(struct cpuinfo_x86 *c); extern void detect_ht(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 8a5b185..0c80d50 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -577,6 +577,20 @@ static void get_model_name(struct cpuinfo_x86 *c) *(s + 1) = '\0'; } +int detect_num_cpu_cores(struct cpuinfo_x86 *c) +{ + unsigned int eax, ebx, ecx, edx; + + if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) + return 1; + + cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); + if (eax & 0x1f) + return (eax >> 26) + 1; + else + return 1; +} + void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) { unsigned int n, dummy, ebx, ecx, edx, l2size; diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 60d1897..f683f7d 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -453,24 +453,6 @@ static void srat_detect_node(struct cpuinfo_x86 *c) #endif } -/* - * find out the number of processor cores on the die - */ -static int intel_num_cpu_cores(struct cpuinfo_x86 *c) -{ - unsigned int eax, ebx, ecx, edx; - - if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) - return 1; - - /* Intel has a non-standard dependency on %ecx for this CPUID level. */ - cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); - if (eax & 0x1f) - return (eax >> 26) + 1; - else - return 1; -} - static void detect_vmx_virtcap(struct cpuinfo_x86 *c) { /* Intel VMX MSR indicated features */ @@ -671,7 +653,7 @@ static void init_intel(struct cpuinfo_x86 *c) * let's use the legacy cpuid vector 0x1 and 0x4 for topology * detection. */ - c->x86_max_cores = intel_num_cpu_cores(c); + c->x86_max_cores = detect_num_cpu_cores(c); #ifdef CONFIG_X86_32 detect_ht(c); #endif -- 1.9.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [tip:x86/cpu] x86/CPU: Make intel_num_cpu_cores() generic 2018-05-03 2:32 ` [PATCH 1/3] x86/CPU: Replace intel_num_cpu_cores with detect_num_cpu_cores David Wang @ 2018-05-13 12:01 ` tip-bot for David Wang 0 siblings, 0 replies; 9+ messages in thread From: tip-bot for David Wang @ 2018-05-13 12:01 UTC (permalink / raw) To: linux-tip-commits; +Cc: davidwang, linux-kernel, tglx, mingo, hpa Commit-ID: 2cc61be60e37b1856a97ccbdcca3e86e593bf06a Gitweb: https://git.kernel.org/tip/2cc61be60e37b1856a97ccbdcca3e86e593bf06a Author: David Wang <davidwang@zhaoxin.com> AuthorDate: Thu, 3 May 2018 10:32:44 +0800 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Sun, 13 May 2018 12:06:12 +0200 x86/CPU: Make intel_num_cpu_cores() generic intel_num_cpu_cores() is a static function in intel.c which can't be used by other files. Define another function called detect_num_cpu_cores() in common.c to replace this function so it can be reused. Signed-off-by: David Wang <davidwang@zhaoxin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: lukelin@viacpu.com Cc: qiyuanwang@zhaoxin.com Cc: gregkh@linuxfoundation.org Cc: brucechang@via-alliance.com Cc: timguo@zhaoxin.com Cc: cooperyan@zhaoxin.com Cc: hpa@zytor.com Cc: benjaminpan@viatech.com Link: https://lkml.kernel.org/r/1525314766-18910-2-git-send-email-davidwang@zhaoxin.com --- arch/x86/kernel/cpu/common.c | 14 ++++++++++++++ arch/x86/kernel/cpu/cpu.h | 1 + arch/x86/kernel/cpu/intel.c | 20 +------------------- 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 37c7c8334a00..6993842e788c 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -584,6 +584,20 @@ static void get_model_name(struct cpuinfo_x86 *c) *(s + 1) = '\0'; } +int detect_num_cpu_cores(struct cpuinfo_x86 *c) +{ + unsigned int eax, ebx, ecx, edx; + + if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) + return 1; + + cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); + if (eax & 0x1f) + return (eax >> 26) + 1; + else + return 1; +} + void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) { unsigned int n, dummy, ebx, ecx, edx, l2size; diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index c415f99e9599..efd6ef8ad14e 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -54,6 +54,7 @@ extern u32 get_scattered_cpuid_leaf(unsigned int level, extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); +extern int detect_num_cpu_cores(struct cpuinfo_x86 *c); extern int detect_extended_topology(struct cpuinfo_x86 *c); extern void detect_ht(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index b9693b80fc21..b54535be254a 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -453,24 +453,6 @@ static void srat_detect_node(struct cpuinfo_x86 *c) #endif } -/* - * find out the number of processor cores on the die - */ -static int intel_num_cpu_cores(struct cpuinfo_x86 *c) -{ - unsigned int eax, ebx, ecx, edx; - - if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) - return 1; - - /* Intel has a non-standard dependency on %ecx for this CPUID level. */ - cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); - if (eax & 0x1f) - return (eax >> 26) + 1; - else - return 1; -} - static void detect_vmx_virtcap(struct cpuinfo_x86 *c) { /* Intel VMX MSR indicated features */ @@ -671,7 +653,7 @@ static void init_intel(struct cpuinfo_x86 *c) * let's use the legacy cpuid vector 0x1 and 0x4 for topology * detection. */ - c->x86_max_cores = intel_num_cpu_cores(c); + c->x86_max_cores = detect_num_cpu_cores(c); #ifdef CONFIG_X86_32 detect_ht(c); #endif ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] x86/cpu: Include cpu_detect_cache_sizes in init_intel_cacheinfo 2018-05-03 2:32 [PATCH 0/3] x86/CPU: Report correct cpu/cache topo for Centaur CPUs and some minor changes David Wang 2018-05-03 2:32 ` [PATCH 1/3] x86/CPU: Replace intel_num_cpu_cores with detect_num_cpu_cores David Wang @ 2018-05-03 2:32 ` David Wang 2018-05-13 12:01 ` [tip:x86/cpu] x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo() tip-bot for David Wang 2018-05-13 14:18 ` tip-bot for David Wang 2018-05-03 2:32 ` [PATCH 3/3] x86/Centaur: Report correct CPU/cache topology David Wang 2 siblings, 2 replies; 9+ messages in thread From: David Wang @ 2018-05-03 2:32 UTC (permalink / raw) To: tglx, mingo, hpa, gregkh, x86, linux-kernel Cc: brucechang, cooperyan, qiyuanwang, benjaminpan, lukelin, timguo, David Wang Clean up the silly cpu_detect_cache_sizes() calling by including the cpu_detect_cache_sizes() inside the init_intel_cacheinfo(). Signed-off-by: David Wang <davidwang@zhaoxin.com> --- arch/x86/kernel/cpu/intel.c | 8 +------- arch/x86/kernel/cpu/intel_cacheinfo.c | 6 ++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index f683f7d..56e3259 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -659,13 +659,7 @@ static void init_intel(struct cpuinfo_x86 *c) #endif } - l2 = init_intel_cacheinfo(c); - - /* Detect legacy cache sizes if init_intel_cacheinfo did not */ - if (l2 == 0) { - cpu_detect_cache_sizes(c); - l2 = c->x86_cache_size; - } + init_intel_cacheinfo(c); if (c->cpuid_level > 9) { unsigned eax = cpuid_eax(10); diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 54d04d5..2a0597c 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -20,6 +20,8 @@ #include <asm/amd_nb.h> #include <asm/smp.h> +#include "cpu.h" + #define LVL_1_INST 1 #define LVL_1_DATA 2 #define LVL_2 3 @@ -802,6 +804,10 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c) c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); + if (!l2) { + cpu_detect_cache_sizes(c); + l2 = c->x86_cache_size; + } return l2; } -- 1.9.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [tip:x86/cpu] x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo() 2018-05-03 2:32 ` [PATCH 2/3] x86/cpu: Include cpu_detect_cache_sizes in init_intel_cacheinfo David Wang @ 2018-05-13 12:01 ` tip-bot for David Wang 2018-05-13 14:18 ` tip-bot for David Wang 1 sibling, 0 replies; 9+ messages in thread From: tip-bot for David Wang @ 2018-05-13 12:01 UTC (permalink / raw) To: linux-tip-commits; +Cc: tglx, hpa, mingo, linux-kernel, davidwang Commit-ID: 606e20959ef49f22cddb611f2cefef8e6501e3dd Gitweb: https://git.kernel.org/tip/606e20959ef49f22cddb611f2cefef8e6501e3dd Author: David Wang <davidwang@zhaoxin.com> AuthorDate: Thu, 3 May 2018 10:32:45 +0800 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Sun, 13 May 2018 12:06:12 +0200 x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo() There is no point in having the conditional cpu_detect_cache_sizes() call at the callsite of init_intel_cacheinfo(). Move it into init_intel_cacheinfo() and make init_intel_cacheinfo() void. [ tglx: Made the init_intel_cacheinfo() void as the return value was pointless. Adjust changelog accordingly ] Signed-off-by: David Wang <davidwang@zhaoxin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: lukelin@viacpu.com Cc: qiyuanwang@zhaoxin.com Cc: gregkh@linuxfoundation.org Cc: brucechang@via-alliance.com Cc: timguo@zhaoxin.com Cc: cooperyan@zhaoxin.com Cc: hpa@zytor.com Cc: benjaminpan@viatech.com Link: https://lkml.kernel.org/r/1525314766-18910-3-git-send-email-davidwang@zhaoxin.com --- arch/x86/kernel/cpu/cacheinfo.c | 5 +++-- arch/x86/kernel/cpu/cpu.h | 2 +- arch/x86/kernel/cpu/intel.c | 13 +++---------- 3 files changed, 7 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c index 58d472c84ba2..38354c66df81 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -691,7 +691,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) } } -unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c) +void init_intel_cacheinfo(struct cpuinfo_x86 *c) { /* Cache sizes */ unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; @@ -843,7 +843,8 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c) c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); - return l2; + if (!l2) + cpu_detect_cache_sizes(c); } static int __cache_amd_cpumap_setup(unsigned int cpu, int index, diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index efd6ef8ad14e..49bf8a080105 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -51,7 +51,7 @@ extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); extern u32 get_scattered_cpuid_leaf(unsigned int level, unsigned int sub_leaf, enum cpuid_regs_idx reg); -extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); +extern void init_intel_cacheinfo(struct cpuinfo_x86 *c); extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); extern int detect_num_cpu_cores(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index b54535be254a..615870420be2 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -635,8 +635,6 @@ static void init_intel_misc_features(struct cpuinfo_x86 *c) static void init_intel(struct cpuinfo_x86 *c) { - unsigned int l2 = 0; - early_init_intel(c); intel_workarounds(c); @@ -659,13 +657,7 @@ static void init_intel(struct cpuinfo_x86 *c) #endif } - l2 = init_intel_cacheinfo(c); - - /* Detect legacy cache sizes if init_intel_cacheinfo did not */ - if (l2 == 0) { - cpu_detect_cache_sizes(c); - l2 = c->x86_cache_size; - } + init_intel_cacheinfo(c); if (c->cpuid_level > 9) { unsigned eax = cpuid_eax(10); @@ -678,7 +670,8 @@ static void init_intel(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); if (boot_cpu_has(X86_FEATURE_DS)) { - unsigned int l1; + unsigned int l1, l2; + rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); if (!(l1 & (1<<11))) set_cpu_cap(c, X86_FEATURE_BTS); ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [tip:x86/cpu] x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo() 2018-05-03 2:32 ` [PATCH 2/3] x86/cpu: Include cpu_detect_cache_sizes in init_intel_cacheinfo David Wang 2018-05-13 12:01 ` [tip:x86/cpu] x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo() tip-bot for David Wang @ 2018-05-13 14:18 ` tip-bot for David Wang 1 sibling, 0 replies; 9+ messages in thread From: tip-bot for David Wang @ 2018-05-13 14:18 UTC (permalink / raw) To: linux-tip-commits; +Cc: mingo, linux-kernel, davidwang, tglx, hpa Commit-ID: 807e9bc8e2fe6b4907f9f77fd073f7ef5073af29 Gitweb: https://git.kernel.org/tip/807e9bc8e2fe6b4907f9f77fd073f7ef5073af29 Author: David Wang <davidwang@zhaoxin.com> AuthorDate: Thu, 3 May 2018 10:32:45 +0800 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Sun, 13 May 2018 16:14:24 +0200 x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo() There is no point in having the conditional cpu_detect_cache_sizes() call at the callsite of init_intel_cacheinfo(). Move it into init_intel_cacheinfo() and make init_intel_cacheinfo() void. [ tglx: Made the init_intel_cacheinfo() void as the return value was pointless. Adjust changelog accordingly ] Signed-off-by: David Wang <davidwang@zhaoxin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: lukelin@viacpu.com Cc: qiyuanwang@zhaoxin.com Cc: gregkh@linuxfoundation.org Cc: brucechang@via-alliance.com Cc: timguo@zhaoxin.com Cc: cooperyan@zhaoxin.com Cc: hpa@zytor.com Cc: benjaminpan@viatech.com Link: https://lkml.kernel.org/r/1525314766-18910-3-git-send-email-davidwang@zhaoxin.com --- arch/x86/kernel/cpu/cacheinfo.c | 5 +++-- arch/x86/kernel/cpu/cpu.h | 2 +- arch/x86/kernel/cpu/intel.c | 14 ++++---------- 3 files changed, 8 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c index 58d472c84ba2..38354c66df81 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -691,7 +691,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) } } -unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c) +void init_intel_cacheinfo(struct cpuinfo_x86 *c) { /* Cache sizes */ unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; @@ -843,7 +843,8 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c) c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); - return l2; + if (!l2) + cpu_detect_cache_sizes(c); } static int __cache_amd_cpumap_setup(unsigned int cpu, int index, diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index efd6ef8ad14e..49bf8a080105 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -51,7 +51,7 @@ extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); extern u32 get_scattered_cpuid_leaf(unsigned int level, unsigned int sub_leaf, enum cpuid_regs_idx reg); -extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); +extern void init_intel_cacheinfo(struct cpuinfo_x86 *c); extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); extern int detect_num_cpu_cores(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index b54535be254a..ca141d159be1 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -635,8 +635,6 @@ static void init_intel_misc_features(struct cpuinfo_x86 *c) static void init_intel(struct cpuinfo_x86 *c) { - unsigned int l2 = 0; - early_init_intel(c); intel_workarounds(c); @@ -659,13 +657,7 @@ static void init_intel(struct cpuinfo_x86 *c) #endif } - l2 = init_intel_cacheinfo(c); - - /* Detect legacy cache sizes if init_intel_cacheinfo did not */ - if (l2 == 0) { - cpu_detect_cache_sizes(c); - l2 = c->x86_cache_size; - } + init_intel_cacheinfo(c); if (c->cpuid_level > 9) { unsigned eax = cpuid_eax(10); @@ -678,7 +670,8 @@ static void init_intel(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); if (boot_cpu_has(X86_FEATURE_DS)) { - unsigned int l1; + unsigned int l1, l2; + rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); if (!(l1 & (1<<11))) set_cpu_cap(c, X86_FEATURE_BTS); @@ -706,6 +699,7 @@ static void init_intel(struct cpuinfo_x86 *c) * Dixon is NOT a Celeron. */ if (c->x86 == 6) { + unsigned int l2 = c->x86_cache_size; char *p = NULL; switch (c->x86_model) { ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] x86/Centaur: Report correct CPU/cache topology 2018-05-03 2:32 [PATCH 0/3] x86/CPU: Report correct cpu/cache topo for Centaur CPUs and some minor changes David Wang 2018-05-03 2:32 ` [PATCH 1/3] x86/CPU: Replace intel_num_cpu_cores with detect_num_cpu_cores David Wang 2018-05-03 2:32 ` [PATCH 2/3] x86/cpu: Include cpu_detect_cache_sizes in init_intel_cacheinfo David Wang @ 2018-05-03 2:32 ` David Wang 2018-05-13 12:02 ` [tip:x86/cpu] " tip-bot for David Wang 2018-05-13 14:19 ` tip-bot for David Wang 2 siblings, 2 replies; 9+ messages in thread From: David Wang @ 2018-05-03 2:32 UTC (permalink / raw) To: tglx, mingo, hpa, gregkh, x86, linux-kernel Cc: brucechang, cooperyan, qiyuanwang, benjaminpan, lukelin, timguo, David Wang Centaur CPUs enumerate the cache topology in the same way as Intel CPUs, but the function is unused so for. The Centaur init code also missies to initialize x86_info::max_cores, so the CPU topology can't be described correctly. Initialize x86_info::max_cores and invoke init_intel_cacheinfo() to make CPU and cache topology information available and correct. Signed-off-by: David Wang <davidwang@zhaoxin.com> --- arch/x86/kernel/cpu/centaur.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 80d5110..c265494 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -160,6 +160,11 @@ static void init_centaur(struct cpuinfo_x86 *c) clear_cpu_cap(c, 0*32+31); #endif early_init_centaur(c); + init_intel_cacheinfo(c); + c->x86_max_cores = detect_num_cpu_cores(c); +#ifdef CONFIG_X86_32 + detect_ht(c); +#endif if (c->cpuid_level > 9) { unsigned int eax = cpuid_eax(10); -- 1.9.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [tip:x86/cpu] x86/Centaur: Report correct CPU/cache topology 2018-05-03 2:32 ` [PATCH 3/3] x86/Centaur: Report correct CPU/cache topology David Wang @ 2018-05-13 12:02 ` tip-bot for David Wang 2018-05-13 14:19 ` tip-bot for David Wang 1 sibling, 0 replies; 9+ messages in thread From: tip-bot for David Wang @ 2018-05-13 12:02 UTC (permalink / raw) To: linux-tip-commits; +Cc: mingo, tglx, linux-kernel, davidwang, hpa Commit-ID: 5a19009043fcffd1591b04a588d53336a66855d5 Gitweb: https://git.kernel.org/tip/5a19009043fcffd1591b04a588d53336a66855d5 Author: David Wang <davidwang@zhaoxin.com> AuthorDate: Thu, 3 May 2018 10:32:46 +0800 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Sun, 13 May 2018 12:06:13 +0200 x86/Centaur: Report correct CPU/cache topology Centaur CPUs enumerate the cache topology in the same way as Intel CPUs, but the function is unused so for. The Centaur init code also misses to initialize x86_info::max_cores, so the CPU topology can't be described correctly. Initialize x86_info::max_cores and invoke init_cacheinfo() to make CPU and cache topology information available and correct. Signed-off-by: David Wang <davidwang@zhaoxin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: lukelin@viacpu.com Cc: qiyuanwang@zhaoxin.com Cc: gregkh@linuxfoundation.org Cc: brucechang@via-alliance.com Cc: timguo@zhaoxin.com Cc: cooperyan@zhaoxin.com Cc: hpa@zytor.com Cc: benjaminpan@viatech.com Link: https://lkml.kernel.org/r/1525314766-18910-4-git-send-email-davidwang@zhaoxin.com --- arch/x86/kernel/cpu/centaur.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 80d5110481ec..c265494234e6 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -160,6 +160,11 @@ static void init_centaur(struct cpuinfo_x86 *c) clear_cpu_cap(c, 0*32+31); #endif early_init_centaur(c); + init_intel_cacheinfo(c); + c->x86_max_cores = detect_num_cpu_cores(c); +#ifdef CONFIG_X86_32 + detect_ht(c); +#endif if (c->cpuid_level > 9) { unsigned int eax = cpuid_eax(10); ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [tip:x86/cpu] x86/Centaur: Report correct CPU/cache topology 2018-05-03 2:32 ` [PATCH 3/3] x86/Centaur: Report correct CPU/cache topology David Wang 2018-05-13 12:02 ` [tip:x86/cpu] " tip-bot for David Wang @ 2018-05-13 14:19 ` tip-bot for David Wang 1 sibling, 0 replies; 9+ messages in thread From: tip-bot for David Wang @ 2018-05-13 14:19 UTC (permalink / raw) To: linux-tip-commits; +Cc: tglx, hpa, linux-kernel, davidwang, mingo Commit-ID: a2aa578fec8c29436bce5e6c15e1e31729d539a3 Gitweb: https://git.kernel.org/tip/a2aa578fec8c29436bce5e6c15e1e31729d539a3 Author: David Wang <davidwang@zhaoxin.com> AuthorDate: Thu, 3 May 2018 10:32:46 +0800 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Sun, 13 May 2018 16:14:24 +0200 x86/Centaur: Report correct CPU/cache topology Centaur CPUs enumerate the cache topology in the same way as Intel CPUs, but the function is unused so for. The Centaur init code also misses to initialize x86_info::max_cores, so the CPU topology can't be described correctly. Initialize x86_info::max_cores and invoke init_cacheinfo() to make CPU and cache topology information available and correct. Signed-off-by: David Wang <davidwang@zhaoxin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: lukelin@viacpu.com Cc: qiyuanwang@zhaoxin.com Cc: gregkh@linuxfoundation.org Cc: brucechang@via-alliance.com Cc: timguo@zhaoxin.com Cc: cooperyan@zhaoxin.com Cc: hpa@zytor.com Cc: benjaminpan@viatech.com Link: https://lkml.kernel.org/r/1525314766-18910-4-git-send-email-davidwang@zhaoxin.com --- arch/x86/kernel/cpu/centaur.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 80d5110481ec..c265494234e6 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -160,6 +160,11 @@ static void init_centaur(struct cpuinfo_x86 *c) clear_cpu_cap(c, 0*32+31); #endif early_init_centaur(c); + init_intel_cacheinfo(c); + c->x86_max_cores = detect_num_cpu_cores(c); +#ifdef CONFIG_X86_32 + detect_ht(c); +#endif if (c->cpuid_level > 9) { unsigned int eax = cpuid_eax(10); ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-05-13 14:19 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-05-03 2:32 [PATCH 0/3] x86/CPU: Report correct cpu/cache topo for Centaur CPUs and some minor changes David Wang 2018-05-03 2:32 ` [PATCH 1/3] x86/CPU: Replace intel_num_cpu_cores with detect_num_cpu_cores David Wang 2018-05-13 12:01 ` [tip:x86/cpu] x86/CPU: Make intel_num_cpu_cores() generic tip-bot for David Wang 2018-05-03 2:32 ` [PATCH 2/3] x86/cpu: Include cpu_detect_cache_sizes in init_intel_cacheinfo David Wang 2018-05-13 12:01 ` [tip:x86/cpu] x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo() tip-bot for David Wang 2018-05-13 14:18 ` tip-bot for David Wang 2018-05-03 2:32 ` [PATCH 3/3] x86/Centaur: Report correct CPU/cache topology David Wang 2018-05-13 12:02 ` [tip:x86/cpu] " tip-bot for David Wang 2018-05-13 14:19 ` tip-bot for David Wang
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).