* [PATCH] perf/x86/intel: Fix: Use u64 for limit_period
@ 2018-03-01 17:54 kan.liang
2018-03-09 9:07 ` [tip:perf/core] perf/x86/intel: Fix large period handling on Broadwell CPUs tip-bot for Kan Liang
0 siblings, 1 reply; 2+ messages in thread
From: kan.liang @ 2018-03-01 17:54 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
The large fixed period could be truncated on Broadwell.
For example, perf record -e cycles -c 10000000000.
The fixed period is 0x2540BE400. But the period which finally applied is
0x540BE400.
Because the limit_period is unsigned, which is 32bit. The higher 32bit
of the period will be truncated.
The issue is introduced since 'commit 294fe0f52a44 ("perf/x86/intel: Add
INST_RETIRED.ALL workarounds")
Although the 'left' is s64, the value of 'left' must be positive when
calling limit_period.
bdw_limit_period() only modify the lowest 6 bits. It doesn't touch the
higher 32bit.
So it's safe to use u64 to replace the unsigned.
Fixes: 294fe0f52a44 ("perf/x86/intel: Add INST_RETIRED.ALL workarounds")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 2 +-
arch/x86/events/perf_event.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 916b6e6..8e722e4 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3222,7 +3222,7 @@ glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
* Therefore the effective (average) period matches the requested period,
* despite coarser hardware granularity.
*/
-static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
+static u64 bdw_limit_period(struct perf_event *event, u64 left)
{
if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
X86_CONFIG(.event=0xc0, .umask=0x01)) {
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index b5352f1..810013d 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -561,7 +561,7 @@ struct x86_pmu {
struct x86_pmu_quirk *quirks;
int perfctr_second_write;
bool late_ack;
- unsigned (*limit_period)(struct perf_event *event, unsigned l);
+ u64 (*limit_period)(struct perf_event *event, u64 l);
/*
* sysfs attrs
--
2.4.11
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [tip:perf/core] perf/x86/intel: Fix large period handling on Broadwell CPUs
2018-03-01 17:54 [PATCH] perf/x86/intel: Fix: Use u64 for limit_period kan.liang
@ 2018-03-09 9:07 ` tip-bot for Kan Liang
0 siblings, 0 replies; 2+ messages in thread
From: tip-bot for Kan Liang @ 2018-03-09 9:07 UTC (permalink / raw)
To: linux-tip-commits
Cc: jolsa, linux-kernel, hpa, tglx, acme, torvalds, vincent.weaver,
mingo, peterz, kan.liang, alexander.shishkin, eranian
Commit-ID: f605cfca8c39ffa2b98c06d2b9f30ba64f1e54e3
Gitweb: https://git.kernel.org/tip/f605cfca8c39ffa2b98c06d2b9f30ba64f1e54e3
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Thu, 1 Mar 2018 12:54:54 -0500
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Fri, 9 Mar 2018 08:22:05 +0100
perf/x86/intel: Fix large period handling on Broadwell CPUs
Large fixed period values could be truncated on Broadwell, for example:
perf record -e cycles -c 10000000000
Here the fixed period is 0x2540BE400, but the period which finally applied is
0x540BE400 - which is wrong.
The reason is that x86_pmu::limit_period() uses an u32 parameter, so the
high 32 bits of 'period' get truncated.
This bug was introduced in:
commit 294fe0f52a44 ("perf/x86/intel: Add INST_RETIRED.ALL workarounds")
It's safe to use u64 instead of u32:
- Although the 'left' is s64, the value of 'left' must be positive when
calling limit_period().
- bdw_limit_period() only modifies the lowest 6 bits, it doesn't touch
the higher 32 bits.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Fixes: 294fe0f52a44 ("perf/x86/intel: Add INST_RETIRED.ALL workarounds")
Link: http://lkml.kernel.org/r/1519926894-3520-1-git-send-email-kan.liang@linux.intel.com
[ Rewrote unacceptably bad changelog. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/core.c | 2 +-
arch/x86/events/perf_event.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 56457cb73448..6b6c1717787d 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3188,7 +3188,7 @@ glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
* Therefore the effective (average) period matches the requested period,
* despite coarser hardware granularity.
*/
-static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
+static u64 bdw_limit_period(struct perf_event *event, u64 left)
{
if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
X86_CONFIG(.event=0xc0, .umask=0x01)) {
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 78f91ec1056e..6495ffd57e3e 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -557,7 +557,7 @@ struct x86_pmu {
struct x86_pmu_quirk *quirks;
int perfctr_second_write;
bool late_ack;
- unsigned (*limit_period)(struct perf_event *event, unsigned l);
+ u64 (*limit_period)(struct perf_event *event, u64 l);
/*
* sysfs attrs
^ permalink raw reply related [flat|nested] 2+ messages in thread
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2018-03-01 17:54 [PATCH] perf/x86/intel: Fix: Use u64 for limit_period kan.liang
2018-03-09 9:07 ` [tip:perf/core] perf/x86/intel: Fix large period handling on Broadwell CPUs tip-bot for Kan Liang
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