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From: Huacai Chen <chenhuacai@kernel.org>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Guo Ren <guoren@kernel.org>, Huacai Chen <chenhuacai@loongson.cn>,
	loongarch@lists.linux.dev,
	 linux-arch <linux-arch@vger.kernel.org>,
	Xuefeng Li <lixuefeng@loongson.cn>,
	 Xuerui Wang <kernel@xen0n.name>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>,
	 Peter Zijlstra <peterz@infradead.org>,
	Will Deacon <will@kernel.org>, Ingo Molnar <mingo@redhat.com>,
	 Rui Wang <wangrui@loongson.cn>
Subject: Re: [PATCH V2 2/2] LoongArch: Add qspinlock support
Date: Thu, 23 Jun 2022 21:05:05 +0800	[thread overview]
Message-ID: <CAAhV-H6MDm_jDFhcT-QBzJ-fLRc6VKoNbsoJC_BGN66sozdqfA@mail.gmail.com> (raw)
In-Reply-To: <CAK8P3a0pKc7=iLcFY028HqJXmGupacm=tV7Wqgx0+bYSqczoog@mail.gmail.com>

Hi, Arnd,

On Thu, Jun 23, 2022 at 4:26 PM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Thu, Jun 23, 2022 at 9:56 AM Huacai Chen <chenhuacai@kernel.org> wrote:
> > On Thu, Jun 23, 2022 at 1:45 PM Guo Ren <guoren@kernel.org> wrote:
> > >
> > > On Thu, Jun 23, 2022 at 12:46 PM Huacai Chen <chenhuacai@loongson.cn> wrote:
> > > >
> > > > On NUMA system, the performance of qspinlock is better than generic
> > > > spinlock. Below is the UnixBench test results on a 8 nodes (4 cores
> > > > per node, 32 cores in total) machine.
>
> You are still missing an explanation here about why this is safe to
> do. Is there are
> architectural guarantee for forward progress, or do you rely on
> specific microarchitectural
> behavior?
In my understanding, "guarantee for forward progress" means to avoid
many ll/sc happening at the same time and no one succeeds.
LoongArch uses "exclusive access (with timeout) of ll" to avoid
simultaneous ll (it also blocks other memory load/store on the same
address), and uses "random delay of sc" to avoid simultaneous sc
(introduced in CPUCFG3, bit 3 and bit 4 [1]). This mechanism can
guarantee forward progress in practice.

[1] https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_cpucfg



Huacai

>
> > > Could you base the patch on [1]?
> > >
> > > [1] https://lore.kernel.org/linux-riscv/20220621144920.2945595-2-guoren@kernel.org/raw
> > I found that whether we use qspinlock or tspinlock, we always use
> > qrwlock, so maybe it is better like this?
> >
> > #ifdef CONFIG_ARCH_USE_QUEUED_SPINLOCKS
> > #include <asm/qspinlock.h>
> > #else
> > #include <asm-generic/tspinlock.h>
> > #endif
> >
> > #include <asm/qrwlock.h>
>
> Yes, that seems better, but I would go one step further and include
> asm-generic/qspinlock.h
> in place of asm/qspinlock.h here: The two architectures that have a
> custom asm/qspinlock.h
> also have a custom asm/spinlock.h, so they have no need to include
> asm-generic/spinlock.h
> either.
>
>         Arnd

  parent reply	other threads:[~2022-06-23 13:05 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-23  4:47 [PATCH V2 1/2] LoongArch: Add subword xchg/cmpxchg emulation Huacai Chen
2022-06-23  4:47 ` [PATCH V2 2/2] LoongArch: Add qspinlock support Huacai Chen
2022-06-23  5:44   ` Guo Ren
2022-06-23  7:56     ` Huacai Chen
2022-06-23  8:26       ` Arnd Bergmann
2022-06-23  8:32         ` Guo Ren
2022-06-23 13:05         ` Huacai Chen [this message]
2022-06-23 14:04           ` Arnd Bergmann
2022-06-25  2:42             ` Guo Ren
2022-06-25  6:22               ` Arnd Bergmann
2022-06-25  6:54             ` Huacai Chen
2022-06-25 11:48               ` Arnd Bergmann
2022-06-25 14:25                 ` Huacai Chen
2022-06-23  6:49 ` [PATCH V2 1/2] LoongArch: Add subword xchg/cmpxchg emulation Guo Ren
2022-06-23  8:04   ` Huacai Chen
2022-06-23  8:43     ` Guo Ren

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