lttng-dev.lists.lttng.org archive mirror
 help / color / mirror / Atom feed
* [lttng-dev] [PATCH urcu 1/4] Cleanup: Move ARM specific code to urcu/arch/arm.h
@ 2020-12-15 16:28 Michael Jeanson via lttng-dev
  2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 2/4] Blacklist GCC 4.4.0, 4.4.1 and 4.4.2 on ARM Michael Jeanson via lttng-dev
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Michael Jeanson via lttng-dev @ 2020-12-15 16:28 UTC (permalink / raw)
  To: lttng-dev

Change-Id: I3e17308c5ae985789a2ac8361e9c9e958ff7d656
Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
---
 include/urcu/arch/arm.h | 13 +++++++++++++
 include/urcu/compiler.h | 13 -------------
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/include/urcu/arch/arm.h b/include/urcu/arch/arm.h
index cb8f28d..5d1c608 100644
--- a/include/urcu/arch/arm.h
+++ b/include/urcu/arch/arm.h
@@ -57,6 +57,19 @@ extern "C" {
 #define __NR_membarrier		389
 #endif
 
+/*
+ * Error out for compilers with known bugs.
+ */
+
+/*
+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58854
+ */
+#ifdef URCU_GCC_VERSION
+# if URCU_GCC_VERSION >= 40800 && URCU_GCC_VERSION <= 40802
+#  error Your gcc version produces clobbered frame accesses
+# endif
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/urcu/compiler.h b/include/urcu/compiler.h
index 511dbdf..4806ee3 100644
--- a/include/urcu/compiler.h
+++ b/include/urcu/compiler.h
@@ -108,23 +108,10 @@
 
 #define CAA_ARRAY_SIZE(x)	(sizeof(x) / sizeof((x)[0]))
 
-/*
- * Don't allow compiling with buggy compiler.
- */
-
 #ifdef __GNUC__
 # define URCU_GCC_VERSION	(__GNUC__ * 10000 \
 				+ __GNUC_MINOR__ * 100 \
 				+ __GNUC_PATCHLEVEL__)
-
-/*
- * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58854
- */
-# ifdef __ARMEL__
-#  if URCU_GCC_VERSION >= 40800 && URCU_GCC_VERSION <= 40802
-#   error Your gcc version produces clobbered frame accesses
-#  endif
-# endif
 #endif
 
 #endif /* _URCU_COMPILER_H */
-- 
2.29.2

_______________________________________________
lttng-dev mailing list
lttng-dev@lists.lttng.org
https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [lttng-dev] [PATCH urcu 2/4] Blacklist GCC 4.4.0, 4.4.1 and 4.4.2 on ARM
  2020-12-15 16:28 [lttng-dev] [PATCH urcu 1/4] Cleanup: Move ARM specific code to urcu/arch/arm.h Michael Jeanson via lttng-dev
@ 2020-12-15 16:28 ` Michael Jeanson via lttng-dev
  2020-12-17 13:29   ` Mathieu Desnoyers via lttng-dev
  2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 3/4] Use DMB only on ARMv7 Michael Jeanson via lttng-dev
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 9+ messages in thread
From: Michael Jeanson via lttng-dev @ 2020-12-15 16:28 UTC (permalink / raw)
  To: lttng-dev

GCC added __sync_synchronize() in 4.4.0 but it was broken on ARM until
4.4.3, see the GCC bug report for more details :

  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42263

Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
Change-Id: I629e3c8b4baaccb34b2311e220f30d0ad8b69a19
---
 include/urcu/arch/arm.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/urcu/arch/arm.h b/include/urcu/arch/arm.h
index 5d1c608..e904b06 100644
--- a/include/urcu/arch/arm.h
+++ b/include/urcu/arch/arm.h
@@ -70,6 +70,15 @@ extern "C" {
 # endif
 #endif
 
+/*
+ * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42263
+ */
+#ifdef URCU_GCC_VERSION
+# if URCU_GCC_VERSION >= 40400 && URCU_GCC_VERSION <= 40402
+#  error Your gcc version has a non-functional __sync_synchronize()
+# endif
+#endif
+
 #ifdef __cplusplus
 }
 #endif
-- 
2.29.2

_______________________________________________
lttng-dev mailing list
lttng-dev@lists.lttng.org
https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [lttng-dev] [PATCH urcu 3/4] Use DMB only on ARMv7
  2020-12-15 16:28 [lttng-dev] [PATCH urcu 1/4] Cleanup: Move ARM specific code to urcu/arch/arm.h Michael Jeanson via lttng-dev
  2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 2/4] Blacklist GCC 4.4.0, 4.4.1 and 4.4.2 on ARM Michael Jeanson via lttng-dev
@ 2020-12-15 16:28 ` Michael Jeanson via lttng-dev
  2020-12-17 13:29   ` Mathieu Desnoyers via lttng-dev
  2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 4/4] Don't force a target and optimization level " Michael Jeanson via lttng-dev
  2020-12-17 13:29 ` [lttng-dev] [PATCH urcu 1/4] Cleanup: Move ARM specific code to urcu/arch/arm.h Mathieu Desnoyers via lttng-dev
  3 siblings, 1 reply; 9+ messages in thread
From: Michael Jeanson via lttng-dev @ 2020-12-15 16:28 UTC (permalink / raw)
  To: lttng-dev; +Cc: Jason Wessel

Remove the configure time CONFIG_RCU_ARM_HAVE_DMB option and replace it
by compile time detection based on the ARM ISA version. This makes sure
we unconditionnaly use the DMB instruction only on ARMv7 where it's part
of the baseline ISA.

This will change the behavior on ARMv6 platform that possibly have this
instruction but it was probably already broken since we use the 'ISH'
option which doesn't seem to be valid on this ISA.

This will also allow sharing headers in a multi-arch environment and
reduce the build system complexity.

Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
Cc: Jason Wessel <jason.wessel@windriver.com>
Change-Id: I8e56ada55148d8e0f198c3d2e741ea414de5fef2
---
 configure.ac             | 19 -------------------
 include/urcu/arch.h      |  7 +++++++
 include/urcu/arch/arm.h  | 13 +++++++++++--
 include/urcu/config.h.in |  3 ---
 4 files changed, 18 insertions(+), 24 deletions(-)

diff --git a/configure.ac b/configure.ac
index d1d43e6..daa967a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -21,7 +21,6 @@ m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])])
 AC_REQUIRE_AUX_FILE([tap-driver.sh])
 
 AH_TEMPLATE([CONFIG_RCU_SMP], [Enable SMP support. With SMP support enabled, uniprocessors are also supported. With SMP support disabled, UP systems work fine, but the behavior of SMP systems is undefined.])
-AH_TEMPLATE([CONFIG_RCU_ARM_HAVE_DMB], [Use the dmb instruction if available for use on ARM.])
 AH_TEMPLATE([CONFIG_RCU_TLS], [TLS provided by the compiler.])
 AH_TEMPLATE([CONFIG_RCU_HAVE_CLOCK_GETTIME], [clock_gettime() is detected.])
 AH_TEMPLATE([CONFIG_RCU_FORCE_SYS_MEMBARRIER], [Require the operating system to support the membarrier system call for default and bulletproof flavors.])
@@ -124,24 +123,6 @@ AS_IF([test "$host_cpu" = "armv7l"],[
 	AM_CFLAGS="$AM_CFLAGS -mcpu=cortex-a9 -mtune=cortex-a9 -O1"
 ])
 
-# ARM-specific checks
-AS_CASE([$host_cpu], [arm*], [
-	AC_MSG_CHECKING([for dmb instruction])
-	AC_COMPILE_IFELSE([AC_LANG_SOURCE([[
-				int main()
-				{
-					asm volatile("dmb":::"memory");
-					return 0;
-				}
-		]])
-	],[
-		AC_MSG_RESULT([yes])
-		AC_DEFINE([CONFIG_RCU_ARM_HAVE_DMB], [1])
-	],[
-		AC_MSG_RESULT([no])
-	])
-])
-
 # Search for clock_gettime
 AC_SEARCH_LIBS([clock_gettime], [rt], [
 	AC_DEFINE([CONFIG_RCU_HAVE_CLOCK_GETTIME], [1])
diff --git a/include/urcu/arch.h b/include/urcu/arch.h
index c4b8bc2..620743c 100644
--- a/include/urcu/arch.h
+++ b/include/urcu/arch.h
@@ -41,6 +41,7 @@
  * URCU_ARCH_ALPHA : All DEC Alpha variants
  * URCU_ARCH_IA64 : All Intel Itanium variants
  * URCU_ARCH_ARM : All ARM 32 bits variants
+ *   URCU_ARCH_ARMV7 : All ARMv7 ISA variants
  * URCU_ARCH_AARCH64 : All ARM 64 bits variants
  * URCU_ARCH_MIPS : All MIPS variants
  * URCU_ARCH_NIOS2 : All Intel / Altera NIOS II variants
@@ -105,6 +106,12 @@
 #define URCU_ARCH_IA64 1
 #include <urcu/arch/ia64.h>
 
+#elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7__))
+
+#define URCU_ARCH_ARMV7 1
+#define URCU_ARCH_ARM 1
+#include <urcu/arch/arm.h>
+
 #elif (defined(__arm__) || defined(__arm))
 
 #define URCU_ARCH_ARM 1
diff --git a/include/urcu/arch/arm.h b/include/urcu/arch/arm.h
index e904b06..54ca4fa 100644
--- a/include/urcu/arch/arm.h
+++ b/include/urcu/arch/arm.h
@@ -30,7 +30,15 @@
 extern "C" {
 #endif
 
-#ifdef CONFIG_RCU_ARM_HAVE_DMB
+/*
+ * Using DMB is faster than the builtin __sync_synchronize and this instruction is
+ * part of the baseline ARMv7 ISA.
+ */
+#ifdef URCU_ARCH_ARMV7
+
+/* For backwards compat. */
+#define CONFIG_RCU_ARM_HAVE_DMB 1
+
 /*
  * Issues full system DMB operation.
  */
@@ -44,7 +52,8 @@ extern "C" {
 #define cmm_smp_mb()	__asm__ __volatile__ ("dmb ish":::"memory")
 #define cmm_smp_rmb()	__asm__ __volatile__ ("dmb ish":::"memory")
 #define cmm_smp_wmb()	__asm__ __volatile__ ("dmb ish":::"memory")
-#endif /* CONFIG_RCU_ARM_HAVE_DMB */
+
+#endif /* URCU_ARCH_ARMV7 */
 
 #include <stdlib.h>
 #include <sys/time.h>
diff --git a/include/urcu/config.h.in b/include/urcu/config.h.in
index faf7817..99d763a 100644
--- a/include/urcu/config.h.in
+++ b/include/urcu/config.h.in
@@ -5,9 +5,6 @@
    behavior of SMP systems is undefined. */
 #undef CONFIG_RCU_SMP
 
-/* Use the dmb instruction is available for use on ARM. */
-#undef CONFIG_RCU_ARM_HAVE_DMB
-
 /* TLS provided by the compiler. */
 #undef CONFIG_RCU_TLS
 
-- 
2.29.2

_______________________________________________
lttng-dev mailing list
lttng-dev@lists.lttng.org
https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [lttng-dev] [PATCH urcu 4/4] Don't force a target and optimization level on ARMv7
  2020-12-15 16:28 [lttng-dev] [PATCH urcu 1/4] Cleanup: Move ARM specific code to urcu/arch/arm.h Michael Jeanson via lttng-dev
  2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 2/4] Blacklist GCC 4.4.0, 4.4.1 and 4.4.2 on ARM Michael Jeanson via lttng-dev
  2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 3/4] Use DMB only on ARMv7 Michael Jeanson via lttng-dev
@ 2020-12-15 16:28 ` Michael Jeanson via lttng-dev
  2020-12-15 16:39   ` Paul E. McKenney via lttng-dev
  2020-12-17 13:30   ` Mathieu Desnoyers via lttng-dev
  2020-12-17 13:29 ` [lttng-dev] [PATCH urcu 1/4] Cleanup: Move ARM specific code to urcu/arch/arm.h Mathieu Desnoyers via lttng-dev
  3 siblings, 2 replies; 9+ messages in thread
From: Michael Jeanson via lttng-dev @ 2020-12-15 16:28 UTC (permalink / raw)
  To: lttng-dev; +Cc: Paul E . McKenney

We shouldn't force a specific target cpu for the compiler on ARMv7 but
let the system or the user choose it. If some of our code depends on a
specific target CPU features, it should be compile tested.

Also remove the default optimisation level of O1, it's potentially a
workaround to an early armv7 compiler performance problem and anyway
most builds will have an optimisation level flag set in the CFLAGS which
will override this one.

Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
Cc: Paul E. McKenney <paulmck@kernel.org>
Change-Id: I1d1bb5cc0fa0be8f8b1d6a9ad7bf063809be1aef
---
 configure.ac | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/configure.ac b/configure.ac
index daa967a..f477425 100644
--- a/configure.ac
+++ b/configure.ac
@@ -119,10 +119,6 @@ AS_CASE([$host],[*-cygwin*],
 	[AM_CONDITIONAL(USE_CYGWIN, false)]
 )
 
-AS_IF([test "$host_cpu" = "armv7l"],[
-	AM_CFLAGS="$AM_CFLAGS -mcpu=cortex-a9 -mtune=cortex-a9 -O1"
-])
-
 # Search for clock_gettime
 AC_SEARCH_LIBS([clock_gettime], [rt], [
 	AC_DEFINE([CONFIG_RCU_HAVE_CLOCK_GETTIME], [1])
-- 
2.29.2

_______________________________________________
lttng-dev mailing list
lttng-dev@lists.lttng.org
https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [lttng-dev] [PATCH urcu 4/4] Don't force a target and optimization level on ARMv7
  2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 4/4] Don't force a target and optimization level " Michael Jeanson via lttng-dev
@ 2020-12-15 16:39   ` Paul E. McKenney via lttng-dev
  2020-12-17 13:30   ` Mathieu Desnoyers via lttng-dev
  1 sibling, 0 replies; 9+ messages in thread
From: Paul E. McKenney via lttng-dev @ 2020-12-15 16:39 UTC (permalink / raw)
  To: Michael Jeanson; +Cc: lttng-dev

On Tue, Dec 15, 2020 at 11:28:50AM -0500, Michael Jeanson wrote:
> We shouldn't force a specific target cpu for the compiler on ARMv7 but
> let the system or the user choose it. If some of our code depends on a
> specific target CPU features, it should be compile tested.
> 
> Also remove the default optimisation level of O1, it's potentially a
> workaround to an early armv7 compiler performance problem and anyway
> most builds will have an optimisation level flag set in the CFLAGS which
> will override this one.

Indeed, the original was based on advice from ARM that has undoubtedly
changed over time, so...

> Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
> Cc: Paul E. McKenney <paulmck@kernel.org>

Acked-by: Paul E. McKenney <paulmck@kernel.org>

> Change-Id: I1d1bb5cc0fa0be8f8b1d6a9ad7bf063809be1aef
> ---
>  configure.ac | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/configure.ac b/configure.ac
> index daa967a..f477425 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -119,10 +119,6 @@ AS_CASE([$host],[*-cygwin*],
>  	[AM_CONDITIONAL(USE_CYGWIN, false)]
>  )
>  
> -AS_IF([test "$host_cpu" = "armv7l"],[
> -	AM_CFLAGS="$AM_CFLAGS -mcpu=cortex-a9 -mtune=cortex-a9 -O1"
> -])
> -
>  # Search for clock_gettime
>  AC_SEARCH_LIBS([clock_gettime], [rt], [
>  	AC_DEFINE([CONFIG_RCU_HAVE_CLOCK_GETTIME], [1])
> -- 
> 2.29.2
> 
_______________________________________________
lttng-dev mailing list
lttng-dev@lists.lttng.org
https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [lttng-dev] [PATCH urcu 1/4] Cleanup: Move ARM specific code to urcu/arch/arm.h
  2020-12-15 16:28 [lttng-dev] [PATCH urcu 1/4] Cleanup: Move ARM specific code to urcu/arch/arm.h Michael Jeanson via lttng-dev
                   ` (2 preceding siblings ...)
  2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 4/4] Don't force a target and optimization level " Michael Jeanson via lttng-dev
@ 2020-12-17 13:29 ` Mathieu Desnoyers via lttng-dev
  3 siblings, 0 replies; 9+ messages in thread
From: Mathieu Desnoyers via lttng-dev @ 2020-12-17 13:29 UTC (permalink / raw)
  To: Michael Jeanson; +Cc: lttng-dev

Merged in liburcu master, thanks!

Mathieu

----- On Dec 15, 2020, at 11:28 AM, Michael Jeanson mjeanson@efficios.com wrote:

> Change-Id: I3e17308c5ae985789a2ac8361e9c9e958ff7d656
> Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
> ---
> include/urcu/arch/arm.h | 13 +++++++++++++
> include/urcu/compiler.h | 13 -------------
> 2 files changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/include/urcu/arch/arm.h b/include/urcu/arch/arm.h
> index cb8f28d..5d1c608 100644
> --- a/include/urcu/arch/arm.h
> +++ b/include/urcu/arch/arm.h
> @@ -57,6 +57,19 @@ extern "C" {
> #define __NR_membarrier		389
> #endif
> 
> +/*
> + * Error out for compilers with known bugs.
> + */
> +
> +/*
> + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58854
> + */
> +#ifdef URCU_GCC_VERSION
> +# if URCU_GCC_VERSION >= 40800 && URCU_GCC_VERSION <= 40802
> +#  error Your gcc version produces clobbered frame accesses
> +# endif
> +#endif
> +
> #ifdef __cplusplus
> }
> #endif
> diff --git a/include/urcu/compiler.h b/include/urcu/compiler.h
> index 511dbdf..4806ee3 100644
> --- a/include/urcu/compiler.h
> +++ b/include/urcu/compiler.h
> @@ -108,23 +108,10 @@
> 
> #define CAA_ARRAY_SIZE(x)	(sizeof(x) / sizeof((x)[0]))
> 
> -/*
> - * Don't allow compiling with buggy compiler.
> - */
> -
> #ifdef __GNUC__
> # define URCU_GCC_VERSION	(__GNUC__ * 10000 \
> 				+ __GNUC_MINOR__ * 100 \
> 				+ __GNUC_PATCHLEVEL__)
> -
> -/*
> - * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58854
> - */
> -# ifdef __ARMEL__
> -#  if URCU_GCC_VERSION >= 40800 && URCU_GCC_VERSION <= 40802
> -#   error Your gcc version produces clobbered frame accesses
> -#  endif
> -# endif
> #endif
> 
> #endif /* _URCU_COMPILER_H */
> --
> 2.29.2

-- 
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com
_______________________________________________
lttng-dev mailing list
lttng-dev@lists.lttng.org
https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [lttng-dev] [PATCH urcu 2/4] Blacklist GCC 4.4.0, 4.4.1 and 4.4.2 on ARM
  2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 2/4] Blacklist GCC 4.4.0, 4.4.1 and 4.4.2 on ARM Michael Jeanson via lttng-dev
@ 2020-12-17 13:29   ` Mathieu Desnoyers via lttng-dev
  0 siblings, 0 replies; 9+ messages in thread
From: Mathieu Desnoyers via lttng-dev @ 2020-12-17 13:29 UTC (permalink / raw)
  To: Michael Jeanson; +Cc: lttng-dev

Merged in liburcu master, thanks!

Mathieu

----- On Dec 15, 2020, at 11:28 AM, Michael Jeanson mjeanson@efficios.com wrote:

> GCC added __sync_synchronize() in 4.4.0 but it was broken on ARM until
> 4.4.3, see the GCC bug report for more details :
> 
>  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42263
> 
> Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
> Change-Id: I629e3c8b4baaccb34b2311e220f30d0ad8b69a19
> ---
> include/urcu/arch/arm.h | 9 +++++++++
> 1 file changed, 9 insertions(+)
> 
> diff --git a/include/urcu/arch/arm.h b/include/urcu/arch/arm.h
> index 5d1c608..e904b06 100644
> --- a/include/urcu/arch/arm.h
> +++ b/include/urcu/arch/arm.h
> @@ -70,6 +70,15 @@ extern "C" {
> # endif
> #endif
> 
> +/*
> + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42263
> + */
> +#ifdef URCU_GCC_VERSION
> +# if URCU_GCC_VERSION >= 40400 && URCU_GCC_VERSION <= 40402
> +#  error Your gcc version has a non-functional __sync_synchronize()
> +# endif
> +#endif
> +
> #ifdef __cplusplus
> }
> #endif
> --
> 2.29.2

-- 
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com
_______________________________________________
lttng-dev mailing list
lttng-dev@lists.lttng.org
https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [lttng-dev] [PATCH urcu 3/4] Use DMB only on ARMv7
  2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 3/4] Use DMB only on ARMv7 Michael Jeanson via lttng-dev
@ 2020-12-17 13:29   ` Mathieu Desnoyers via lttng-dev
  0 siblings, 0 replies; 9+ messages in thread
From: Mathieu Desnoyers via lttng-dev @ 2020-12-17 13:29 UTC (permalink / raw)
  To: Michael Jeanson; +Cc: lttng-dev, Jason Wessel

Merged in liburcu master, thanks!

Mathieu

----- On Dec 15, 2020, at 11:28 AM, Michael Jeanson mjeanson@efficios.com wrote:

> Remove the configure time CONFIG_RCU_ARM_HAVE_DMB option and replace it
> by compile time detection based on the ARM ISA version. This makes sure
> we unconditionnaly use the DMB instruction only on ARMv7 where it's part
> of the baseline ISA.
> 
> This will change the behavior on ARMv6 platform that possibly have this
> instruction but it was probably already broken since we use the 'ISH'
> option which doesn't seem to be valid on this ISA.
> 
> This will also allow sharing headers in a multi-arch environment and
> reduce the build system complexity.
> 
> Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
> Cc: Jason Wessel <jason.wessel@windriver.com>
> Change-Id: I8e56ada55148d8e0f198c3d2e741ea414de5fef2
> ---
> configure.ac             | 19 -------------------
> include/urcu/arch.h      |  7 +++++++
> include/urcu/arch/arm.h  | 13 +++++++++++--
> include/urcu/config.h.in |  3 ---
> 4 files changed, 18 insertions(+), 24 deletions(-)
> 
> diff --git a/configure.ac b/configure.ac
> index d1d43e6..daa967a 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -21,7 +21,6 @@ m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])])
> AC_REQUIRE_AUX_FILE([tap-driver.sh])
> 
> AH_TEMPLATE([CONFIG_RCU_SMP], [Enable SMP support. With SMP support enabled,
> uniprocessors are also supported. With SMP support disabled, UP systems work
> fine, but the behavior of SMP systems is undefined.])
> -AH_TEMPLATE([CONFIG_RCU_ARM_HAVE_DMB], [Use the dmb instruction if available
> for use on ARM.])
> AH_TEMPLATE([CONFIG_RCU_TLS], [TLS provided by the compiler.])
> AH_TEMPLATE([CONFIG_RCU_HAVE_CLOCK_GETTIME], [clock_gettime() is detected.])
> AH_TEMPLATE([CONFIG_RCU_FORCE_SYS_MEMBARRIER], [Require the operating system to
> support the membarrier system call for default and bulletproof flavors.])
> @@ -124,24 +123,6 @@ AS_IF([test "$host_cpu" = "armv7l"],[
> 	AM_CFLAGS="$AM_CFLAGS -mcpu=cortex-a9 -mtune=cortex-a9 -O1"
> ])
> 
> -# ARM-specific checks
> -AS_CASE([$host_cpu], [arm*], [
> -	AC_MSG_CHECKING([for dmb instruction])
> -	AC_COMPILE_IFELSE([AC_LANG_SOURCE([[
> -				int main()
> -				{
> -					asm volatile("dmb":::"memory");
> -					return 0;
> -				}
> -		]])
> -	],[
> -		AC_MSG_RESULT([yes])
> -		AC_DEFINE([CONFIG_RCU_ARM_HAVE_DMB], [1])
> -	],[
> -		AC_MSG_RESULT([no])
> -	])
> -])
> -
> # Search for clock_gettime
> AC_SEARCH_LIBS([clock_gettime], [rt], [
> 	AC_DEFINE([CONFIG_RCU_HAVE_CLOCK_GETTIME], [1])
> diff --git a/include/urcu/arch.h b/include/urcu/arch.h
> index c4b8bc2..620743c 100644
> --- a/include/urcu/arch.h
> +++ b/include/urcu/arch.h
> @@ -41,6 +41,7 @@
>  * URCU_ARCH_ALPHA : All DEC Alpha variants
>  * URCU_ARCH_IA64 : All Intel Itanium variants
>  * URCU_ARCH_ARM : All ARM 32 bits variants
> + *   URCU_ARCH_ARMV7 : All ARMv7 ISA variants
>  * URCU_ARCH_AARCH64 : All ARM 64 bits variants
>  * URCU_ARCH_MIPS : All MIPS variants
>  * URCU_ARCH_NIOS2 : All Intel / Altera NIOS II variants
> @@ -105,6 +106,12 @@
> #define URCU_ARCH_IA64 1
> #include <urcu/arch/ia64.h>
> 
> +#elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7__))
> +
> +#define URCU_ARCH_ARMV7 1
> +#define URCU_ARCH_ARM 1
> +#include <urcu/arch/arm.h>
> +
> #elif (defined(__arm__) || defined(__arm))
> 
> #define URCU_ARCH_ARM 1
> diff --git a/include/urcu/arch/arm.h b/include/urcu/arch/arm.h
> index e904b06..54ca4fa 100644
> --- a/include/urcu/arch/arm.h
> +++ b/include/urcu/arch/arm.h
> @@ -30,7 +30,15 @@
> extern "C" {
> #endif
> 
> -#ifdef CONFIG_RCU_ARM_HAVE_DMB
> +/*
> + * Using DMB is faster than the builtin __sync_synchronize and this instruction
> is
> + * part of the baseline ARMv7 ISA.
> + */
> +#ifdef URCU_ARCH_ARMV7
> +
> +/* For backwards compat. */
> +#define CONFIG_RCU_ARM_HAVE_DMB 1
> +
> /*
>  * Issues full system DMB operation.
>  */
> @@ -44,7 +52,8 @@ extern "C" {
> #define cmm_smp_mb()	__asm__ __volatile__ ("dmb ish":::"memory")
> #define cmm_smp_rmb()	__asm__ __volatile__ ("dmb ish":::"memory")
> #define cmm_smp_wmb()	__asm__ __volatile__ ("dmb ish":::"memory")
> -#endif /* CONFIG_RCU_ARM_HAVE_DMB */
> +
> +#endif /* URCU_ARCH_ARMV7 */
> 
> #include <stdlib.h>
> #include <sys/time.h>
> diff --git a/include/urcu/config.h.in b/include/urcu/config.h.in
> index faf7817..99d763a 100644
> --- a/include/urcu/config.h.in
> +++ b/include/urcu/config.h.in
> @@ -5,9 +5,6 @@
>    behavior of SMP systems is undefined. */
> #undef CONFIG_RCU_SMP
> 
> -/* Use the dmb instruction is available for use on ARM. */
> -#undef CONFIG_RCU_ARM_HAVE_DMB
> -
> /* TLS provided by the compiler. */
> #undef CONFIG_RCU_TLS
> 
> --
> 2.29.2

-- 
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com
_______________________________________________
lttng-dev mailing list
lttng-dev@lists.lttng.org
https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [lttng-dev] [PATCH urcu 4/4] Don't force a target and optimization level on ARMv7
  2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 4/4] Don't force a target and optimization level " Michael Jeanson via lttng-dev
  2020-12-15 16:39   ` Paul E. McKenney via lttng-dev
@ 2020-12-17 13:30   ` Mathieu Desnoyers via lttng-dev
  1 sibling, 0 replies; 9+ messages in thread
From: Mathieu Desnoyers via lttng-dev @ 2020-12-17 13:30 UTC (permalink / raw)
  To: Michael Jeanson; +Cc: lttng-dev, paulmck

Merged in liburcu master, thanks!

Mathieu

----- On Dec 15, 2020, at 11:28 AM, Michael Jeanson mjeanson@efficios.com wrote:

> We shouldn't force a specific target cpu for the compiler on ARMv7 but
> let the system or the user choose it. If some of our code depends on a
> specific target CPU features, it should be compile tested.
> 
> Also remove the default optimisation level of O1, it's potentially a
> workaround to an early armv7 compiler performance problem and anyway
> most builds will have an optimisation level flag set in the CFLAGS which
> will override this one.
> 
> Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
> Cc: Paul E. McKenney <paulmck@kernel.org>
> Change-Id: I1d1bb5cc0fa0be8f8b1d6a9ad7bf063809be1aef
> ---
> configure.ac | 4 ----
> 1 file changed, 4 deletions(-)
> 
> diff --git a/configure.ac b/configure.ac
> index daa967a..f477425 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -119,10 +119,6 @@ AS_CASE([$host],[*-cygwin*],
> 	[AM_CONDITIONAL(USE_CYGWIN, false)]
> )
> 
> -AS_IF([test "$host_cpu" = "armv7l"],[
> -	AM_CFLAGS="$AM_CFLAGS -mcpu=cortex-a9 -mtune=cortex-a9 -O1"
> -])
> -
> # Search for clock_gettime
> AC_SEARCH_LIBS([clock_gettime], [rt], [
> 	AC_DEFINE([CONFIG_RCU_HAVE_CLOCK_GETTIME], [1])
> --
> 2.29.2

-- 
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com
_______________________________________________
lttng-dev mailing list
lttng-dev@lists.lttng.org
https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2020-12-17 13:30 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-15 16:28 [lttng-dev] [PATCH urcu 1/4] Cleanup: Move ARM specific code to urcu/arch/arm.h Michael Jeanson via lttng-dev
2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 2/4] Blacklist GCC 4.4.0, 4.4.1 and 4.4.2 on ARM Michael Jeanson via lttng-dev
2020-12-17 13:29   ` Mathieu Desnoyers via lttng-dev
2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 3/4] Use DMB only on ARMv7 Michael Jeanson via lttng-dev
2020-12-17 13:29   ` Mathieu Desnoyers via lttng-dev
2020-12-15 16:28 ` [lttng-dev] [PATCH urcu 4/4] Don't force a target and optimization level " Michael Jeanson via lttng-dev
2020-12-15 16:39   ` Paul E. McKenney via lttng-dev
2020-12-17 13:30   ` Mathieu Desnoyers via lttng-dev
2020-12-17 13:29 ` [lttng-dev] [PATCH urcu 1/4] Cleanup: Move ARM specific code to urcu/arch/arm.h Mathieu Desnoyers via lttng-dev

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).