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* [PATCH v2 net-next] stmmac: intel: Enable SERDES PHY rx clk for PSE
@ 2021-04-06  1:32 Voon Weifeng
  2021-04-07 21:40 ` patchwork-bot+netdevbpf
  0 siblings, 1 reply; 2+ messages in thread
From: Voon Weifeng @ 2021-04-06  1:32 UTC (permalink / raw)
  To: David S . Miller, Maxime Coquelin
  Cc: netdev, linux-kernel, Jose Abreu, Jakub Kicinski,
	Giuseppe Cavallaro, Alexandre Torgue, linux-stm32,
	linux-arm-kernel, Ong Boon Leong, Voon Weifeng, Wong Vee Khee

EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
sequence and vice versa.

Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
---
Changes:
 v1 -> v2
 -change subject from "net: intel" to "stmmac: intel"
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 10 ++++++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h |  1 +
 2 files changed, 11 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index add95e20548d..a4fec5fe0779 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -153,6 +153,11 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
 		return data;
 	}
 
+	/* PSE only - ungate SGMII PHY Rx Clock */
+	if (intel_priv->is_pse)
+		mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
+			       0, SERDES_PHY_RX_CLK);
+
 	return 0;
 }
 
@@ -168,6 +173,11 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
 
 	serdes_phy_addr = intel_priv->mdio_adhoc_addr;
 
+	/* PSE only - gate SGMII PHY Rx Clock */
+	if (intel_priv->is_pse)
+		mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
+			       SERDES_PHY_RX_CLK, 0);
+
 	/*  move power state to P3 */
 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
index e723096c0b15..542acb8ce467 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
@@ -14,6 +14,7 @@
 
 /* SERDES defines */
 #define SERDES_PLL_CLK		BIT(0)		/* PLL clk valid signal */
+#define SERDES_PHY_RX_CLK	BIT(1)		/* PSE SGMII PHY rx clk */
 #define SERDES_RST		BIT(2)		/* Serdes Reset */
 #define SERDES_PWR_ST_MASK	GENMASK(6, 4)	/* Serdes Power state*/
 #define SERDES_PWR_ST_SHIFT	4
-- 
2.17.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH v2 net-next] stmmac: intel: Enable SERDES PHY rx clk for PSE
  2021-04-06  1:32 [PATCH v2 net-next] stmmac: intel: Enable SERDES PHY rx clk for PSE Voon Weifeng
@ 2021-04-07 21:40 ` patchwork-bot+netdevbpf
  0 siblings, 0 replies; 2+ messages in thread
From: patchwork-bot+netdevbpf @ 2021-04-07 21:40 UTC (permalink / raw)
  To: Voon, Weifeng
  Cc: davem, mcoquelin.stm32, netdev, linux-kernel, joabreu, kuba,
	peppe.cavallaro, alexandre.torgue, linux-stm32, linux-arm-kernel,
	boon.leong.ong, vee.khee.wong

Hello:

This patch was applied to netdev/net-next.git (refs/heads/master):

On Tue,  6 Apr 2021 09:32:50 +0800 you wrote:
> EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
> sequence and vice versa.
> 
> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
> ---
> Changes:
>  v1 -> v2
>  -change subject from "net: intel" to "stmmac: intel"
> 
> [...]

Here is the summary with links:
  - [v2,net-next] stmmac: intel: Enable SERDES PHY rx clk for PSE
    https://git.kernel.org/netdev/net-next/c/017d6250ad71

You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



^ permalink raw reply	[flat|nested] 2+ messages in thread

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2021-04-06  1:32 [PATCH v2 net-next] stmmac: intel: Enable SERDES PHY rx clk for PSE Voon Weifeng
2021-04-07 21:40 ` patchwork-bot+netdevbpf

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