* [PATCH net] net: dsa: sja1105: disallow C45 transactions on the BASE-TX MDIO bus
@ 2022-11-16 10:06 Vladimir Oltean
2022-11-16 13:28 ` Andrew Lunn
2022-11-18 12:20 ` patchwork-bot+netdevbpf
0 siblings, 2 replies; 6+ messages in thread
From: Vladimir Oltean @ 2022-11-16 10:06 UTC (permalink / raw)
To: netdev
Cc: Andrew Lunn, Florian Fainelli, Vladimir Oltean, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni
You'd think people know that the internal 100BASE-TX PHY on the SJA1110
responds only to clause 22 MDIO transactions, but they don't :)
When a clause 45 transaction is attempted, sja1105_base_tx_mdio_read()
and sja1105_base_tx_mdio_write() don't expect "reg" to contain bit 30
set (MII_ADDR_C45) and pack this value into the SPI transaction buffer.
But the field in the SPI buffer has a width smaller than 30 bits, so we
see this confusing message from the packing() API rather than a proper
rejection of C45 transactions:
Call trace:
dump_stack+0x1c/0x38
sja1105_pack+0xbc/0xc0 [sja1105]
sja1105_xfer+0x114/0x2b0 [sja1105]
sja1105_xfer_u32+0x44/0xf4 [sja1105]
sja1105_base_tx_mdio_read+0x44/0x7c [sja1105]
mdiobus_read+0x44/0x80
get_phy_c45_ids+0x70/0x234
get_phy_device+0x68/0x15c
fwnode_mdiobus_register_phy+0x74/0x240
of_mdiobus_register+0x13c/0x380
sja1105_mdiobus_register+0x368/0x490 [sja1105]
sja1105_setup+0x94/0x119c [sja1105]
Cannot store 401d2405 inside bits 24-4 (would truncate)
Fixes: 5a8f09748ee7 ("net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/dsa/sja1105/sja1105_mdio.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/dsa/sja1105/sja1105_mdio.c b/drivers/net/dsa/sja1105/sja1105_mdio.c
index 215dd17ca790..4059fcc8c832 100644
--- a/drivers/net/dsa/sja1105/sja1105_mdio.c
+++ b/drivers/net/dsa/sja1105/sja1105_mdio.c
@@ -256,6 +256,9 @@ static int sja1105_base_tx_mdio_read(struct mii_bus *bus, int phy, int reg)
u32 tmp;
int rc;
+ if (reg & MII_ADDR_C45)
+ return -EOPNOTSUPP;
+
rc = sja1105_xfer_u32(priv, SPI_READ, regs->mdio_100base_tx + reg,
&tmp, NULL);
if (rc < 0)
@@ -272,6 +275,9 @@ static int sja1105_base_tx_mdio_write(struct mii_bus *bus, int phy, int reg,
const struct sja1105_regs *regs = priv->info->regs;
u32 tmp = val;
+ if (reg & MII_ADDR_C45)
+ return -EOPNOTSUPP;
+
return sja1105_xfer_u32(priv, SPI_WRITE, regs->mdio_100base_tx + reg,
&tmp, NULL);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH net] net: dsa: sja1105: disallow C45 transactions on the BASE-TX MDIO bus
2022-11-16 10:06 [PATCH net] net: dsa: sja1105: disallow C45 transactions on the BASE-TX MDIO bus Vladimir Oltean
@ 2022-11-16 13:28 ` Andrew Lunn
2022-11-17 8:11 ` Michael Walle
2022-11-18 12:20 ` patchwork-bot+netdevbpf
1 sibling, 1 reply; 6+ messages in thread
From: Andrew Lunn @ 2022-11-16 13:28 UTC (permalink / raw)
To: Vladimir Oltean
Cc: netdev, Florian Fainelli, Vladimir Oltean, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni
On Wed, Nov 16, 2022 at 12:06:53PM +0200, Vladimir Oltean wrote:
> You'd think people know that the internal 100BASE-TX PHY on the SJA1110
> responds only to clause 22 MDIO transactions, but they don't :)
>
> When a clause 45 transaction is attempted, sja1105_base_tx_mdio_read()
> and sja1105_base_tx_mdio_write() don't expect "reg" to contain bit 30
> set (MII_ADDR_C45) and pack this value into the SPI transaction buffer.
Yep, it is a common problem with MDIO busses. And driver i review now
i asks for EOPNOTSUPP for clauses which are not supported, but there
are old drivers out there missing such checks.
I have a bit rotting patchset which completely separates C22 and C45,
i just spend too much time reviewing other code to get my own merged.
> Fixes: 5a8f09748ee7 ("net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH net] net: dsa: sja1105: disallow C45 transactions on the BASE-TX MDIO bus
2022-11-16 13:28 ` Andrew Lunn
@ 2022-11-17 8:11 ` Michael Walle
2022-11-17 13:41 ` Andrew Lunn
0 siblings, 1 reply; 6+ messages in thread
From: Michael Walle @ 2022-11-17 8:11 UTC (permalink / raw)
To: andrew, Vladimir Oltean
Cc: davem, edumazet, f.fainelli, kuba, netdev, olteanv, pabeni
From: Andrew Lunn <andrew@lunn.ch>
> I have a bit rotting patchset which completely separates C22 and C45,
> i just spend too much time reviewing other code to get my own merged.
I'm still rebasing your patchset to the latest next as I still
need it as a base for my patches regarding the maxlinear/microchip phy
issue :)
-michael
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH net] net: dsa: sja1105: disallow C45 transactions on the BASE-TX MDIO bus
2022-11-17 8:11 ` Michael Walle
@ 2022-11-17 13:41 ` Andrew Lunn
2022-11-18 13:31 ` Michael Walle
0 siblings, 1 reply; 6+ messages in thread
From: Andrew Lunn @ 2022-11-17 13:41 UTC (permalink / raw)
To: Michael Walle
Cc: Vladimir Oltean, davem, edumazet, f.fainelli, kuba, netdev,
olteanv, pabeni
On Thu, Nov 17, 2022 at 09:11:05AM +0100, Michael Walle wrote:
> From: Andrew Lunn <andrew@lunn.ch>
>
> > I have a bit rotting patchset which completely separates C22 and C45,
> > i just spend too much time reviewing other code to get my own merged.
>
> I'm still rebasing your patchset to the latest next as I still
> need it as a base for my patches regarding the maxlinear/microchip phy
> issue :)
Feel free to post it. Just add your own Signed-off-by: after mine.
I can probably help with some of the review comments. I think the
biggest problem i had was some reviews wanted more cleanup, when i was
trying to keep it KISS to reduce the likelihood of breakage.
Andrew
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH net] net: dsa: sja1105: disallow C45 transactions on the BASE-TX MDIO bus
2022-11-16 10:06 [PATCH net] net: dsa: sja1105: disallow C45 transactions on the BASE-TX MDIO bus Vladimir Oltean
2022-11-16 13:28 ` Andrew Lunn
@ 2022-11-18 12:20 ` patchwork-bot+netdevbpf
1 sibling, 0 replies; 6+ messages in thread
From: patchwork-bot+netdevbpf @ 2022-11-18 12:20 UTC (permalink / raw)
To: Vladimir Oltean
Cc: netdev, andrew, f.fainelli, olteanv, davem, edumazet, kuba, pabeni
Hello:
This patch was applied to netdev/net.git (master)
by David S. Miller <davem@davemloft.net>:
On Wed, 16 Nov 2022 12:06:53 +0200 you wrote:
> You'd think people know that the internal 100BASE-TX PHY on the SJA1110
> responds only to clause 22 MDIO transactions, but they don't :)
>
> When a clause 45 transaction is attempted, sja1105_base_tx_mdio_read()
> and sja1105_base_tx_mdio_write() don't expect "reg" to contain bit 30
> set (MII_ADDR_C45) and pack this value into the SPI transaction buffer.
>
> [...]
Here is the summary with links:
- [net] net: dsa: sja1105: disallow C45 transactions on the BASE-TX MDIO bus
https://git.kernel.org/netdev/net/c/24deec6b9e4a
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH net] net: dsa: sja1105: disallow C45 transactions on the BASE-TX MDIO bus
2022-11-17 13:41 ` Andrew Lunn
@ 2022-11-18 13:31 ` Michael Walle
0 siblings, 0 replies; 6+ messages in thread
From: Michael Walle @ 2022-11-18 13:31 UTC (permalink / raw)
To: Andrew Lunn
Cc: Vladimir Oltean, davem, edumazet, f.fainelli, kuba, netdev,
olteanv, pabeni
Am 2022-11-17 14:41, schrieb Andrew Lunn:
> On Thu, Nov 17, 2022 at 09:11:05AM +0100, Michael Walle wrote:
>> From: Andrew Lunn <andrew@lunn.ch>
>>
>> > I have a bit rotting patchset which completely separates C22 and C45,
>> > i just spend too much time reviewing other code to get my own merged.
>>
>> I'm still rebasing your patchset to the latest next as I still
>> need it as a base for my patches regarding the maxlinear/microchip phy
>> issue :)
>
> Feel free to post it. Just add your own Signed-off-by: after mine.
>
> I can probably help with some of the review comments. I think the
> biggest problem i had was some reviews wanted more cleanup, when i was
> trying to keep it KISS to reduce the likelihood of breakage.
I wasn't aware that some of the patches were already sent to the
LKML. I guess you refer to this:
https://lore.kernel.org/netdev/20220508153049.427227-1-andrew@lunn.ch/
-michael
^ permalink raw reply [flat|nested] 6+ messages in thread
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2022-11-16 10:06 [PATCH net] net: dsa: sja1105: disallow C45 transactions on the BASE-TX MDIO bus Vladimir Oltean
2022-11-16 13:28 ` Andrew Lunn
2022-11-17 8:11 ` Michael Walle
2022-11-17 13:41 ` Andrew Lunn
2022-11-18 13:31 ` Michael Walle
2022-11-18 12:20 ` patchwork-bot+netdevbpf
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