[PATCH net-next 0/8] net: eth: altera: tse: Add PTP and mSGDMA prefetcher

[PATCH net-next 0/8] net: eth: altera: tse: Add PTP and mSGDMA prefetcher

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

This patch series cleans up the Altera TSE driver and adds support
for the newer msgdma prefetcher as well as ptp support when using
the msgdma prefetcher.

Dalon Westergreen (8):
  net: eth: altera: tse_start_xmit ignores tx_buffer call response
  net: eth: altera: set rx and tx ring size before init_dma call
  net: eth: altera: tse: fix altera_dmaops declaration
  net: eth: altera: tse: add optional function to start tx dma
  net: eth: altera: tse: Move common functions to altera_utils
  net: eth: altera: tse: add support for ptp and timestamping
  net: eth: altera: tse: add msgdma prefetcher
  net: eth: altera: tse: update devicetree bindings documentation

 .../devicetree/bindings/net/altera_tse.txt    |  98 +++-
 drivers/net/ethernet/altera/Kconfig           |   1 +
 drivers/net/ethernet/altera/Makefile          |   3 +-
 .../altera/altera_msgdma_prefetcher.c         | 433 ++++++++++++++++
 .../altera/altera_msgdma_prefetcher.h         |  30 ++
 .../altera/altera_msgdmahw_prefetcher.h       |  87 ++++
 drivers/net/ethernet/altera/altera_ptp.c      | 473 ++++++++++++++++++
 drivers/net/ethernet/altera/altera_ptp.h      |  77 +++
 drivers/net/ethernet/altera/altera_sgdma.c    |  14 +-
 drivers/net/ethernet/altera/altera_tse.h      | 100 ++--
 .../net/ethernet/altera/altera_tse_ethtool.c  |  29 ++
 drivers/net/ethernet/altera/altera_tse_main.c | 244 ++++++++-
 drivers/net/ethernet/altera/altera_utils.c    |  30 ++
 drivers/net/ethernet/altera/altera_utils.h    |  46 ++
 14 files changed, 1554 insertions(+), 111 deletions(-)
 create mode 100644 drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
 create mode 100644 drivers/net/ethernet/altera/altera_msgdma_prefetcher.h
 create mode 100644 drivers/net/ethernet/altera/altera_msgdmahw_prefetcher.h
 create mode 100644 drivers/net/ethernet/altera/altera_ptp.c
 create mode 100644 drivers/net/ethernet/altera/altera_ptp.h

-- 
2.19.1

[PATCH net-next 1/8] net: eth: altera: tse_start_xmit ignores tx_buffer call response

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

The return from tx_buffer call in tse_start_xmit is
inapropriately ignored.  tse_buffer calls should return
0 for success or NETDEV_TX_BUSY.  tse_start_xmit should
return not report a successful transmit when the tse_buffer
call returns an error condition.

In addition to the above, the msgdma and sgdma do not return
the same value on success or failure.  The sgdma_tx_buffer
returned 0 on failure and a positive number of transmitted
packets on success.  Given that it only ever sends 1 packet,
this made no sense.  The msgdma implementation msgdma_tx_buffer
returns 0 on success.

  -> Don't ignore the return from tse_buffer calls
  -> Fix sgdma tse_buffer call to return 0 on success
     and NETDEV_TX_BUSY on failure.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 drivers/net/ethernet/altera/altera_sgdma.c    | 14 ++++++++------
 drivers/net/ethernet/altera/altera_tse_main.c |  4 +++-
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_sgdma.c b/drivers/net/ethernet/altera/altera_sgdma.c
index 88ef67a998b4..eb47b9b820bb 100644
--- a/drivers/net/ethernet/altera/altera_sgdma.c
+++ b/drivers/net/ethernet/altera/altera_sgdma.c
@@ -15,6 +15,7 @@
  */
 
 #include <linux/list.h>
+#include <linux/netdevice.h>
 #include "altera_utils.h"
 #include "altera_tse.h"
 #include "altera_sgdmahw.h"
@@ -170,10 +171,11 @@ void sgdma_clear_txirq(struct altera_tse_private *priv)
 		    SGDMA_CTRLREG_CLRINT);
 }
 
-/* transmits buffer through SGDMA. Returns number of buffers
- * transmitted, 0 if not possible.
- *
- * tx_lock is held by the caller
+/* transmits buffer through SGDMA.
+ *   original behavior returned the number of transmitted packets (always 1) &
+ *   returned 0 on error.  This differs from the msgdma.  the calling function
+ *   will now actually look at the code, so from now, 0 is good and return
+ *   NETDEV_TX_BUSY when busy.
  */
 int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
 {
@@ -185,7 +187,7 @@ int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
 
 	/* wait 'til the tx sgdma is ready for the next transmit request */
 	if (sgdma_txbusy(priv))
-		return 0;
+		return NETDEV_TX_BUSY;
 
 	sgdma_setup_descrip(cdesc,			/* current descriptor */
 			    ndesc,			/* next descriptor */
@@ -202,7 +204,7 @@ int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
 	/* enqueue the request to the pending transmit queue */
 	queue_tx(priv, buffer);
 
-	return 1;
+	return 0;
 }
 
 
diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c
index baca8f704a45..dcb330129e23 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -606,7 +606,9 @@ static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
 	buffer->dma_addr = dma_addr;
 	buffer->len = nopaged_len;
 
-	priv->dmaops->tx_buffer(priv, buffer);
+	ret = priv->dmaops->tx_buffer(priv, buffer);
+	if (ret)
+		goto out;
 
 	skb_tx_timestamp(skb);
 
-- 
2.19.1

[PATCH net-next 2/8] net: eth: altera: set rx and tx ring size before init_dma call

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

It is more appropriate to set the rx and tx ring size before calling
the init function for the dma.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 drivers/net/ethernet/altera/altera_tse_main.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c
index dcb330129e23..0c0e8f9bba9b 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -1166,6 +1166,10 @@ static int tse_open(struct net_device *dev)
 	int i;
 	unsigned long int flags;
 
+	/* set tx and rx ring size */
+	priv->rx_ring_size = dma_rx_num;
+	priv->tx_ring_size = dma_tx_num;
+
 	/* Reset and configure TSE MAC and probe associated PHY */
 	ret = priv->dmaops->init_dma(priv);
 	if (ret != 0) {
@@ -1208,8 +1212,6 @@ static int tse_open(struct net_device *dev)
 	priv->dmaops->reset_dma(priv);
 
 	/* Create and initialize the TX/RX descriptors chains. */
-	priv->rx_ring_size = dma_rx_num;
-	priv->tx_ring_size = dma_tx_num;
 	ret = alloc_init_skbufs(priv);
 	if (ret) {
 		netdev_err(dev, "DMA descriptors initialization failed\n");
-- 
2.19.1

[PATCH net-next 3/8] net: eth: altera: tse: fix altera_dmaops declaration

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

The declaration of struct altera_dmaops does not have
identifier names.  Add identifier names to confrom with
required coding styles.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 drivers/net/ethernet/altera/altera_tse.h | 30 +++++++++++++-----------
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h
index e2feee87180a..d5b97e02e6d6 100644
--- a/drivers/net/ethernet/altera/altera_tse.h
+++ b/drivers/net/ethernet/altera/altera_tse.h
@@ -396,20 +396,22 @@ struct altera_tse_private;
 struct altera_dmaops {
 	int altera_dtype;
 	int dmamask;
-	void (*reset_dma)(struct altera_tse_private *);
-	void (*enable_txirq)(struct altera_tse_private *);
-	void (*enable_rxirq)(struct altera_tse_private *);
-	void (*disable_txirq)(struct altera_tse_private *);
-	void (*disable_rxirq)(struct altera_tse_private *);
-	void (*clear_txirq)(struct altera_tse_private *);
-	void (*clear_rxirq)(struct altera_tse_private *);
-	int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *);
-	u32 (*tx_completions)(struct altera_tse_private *);
-	void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *);
-	u32 (*get_rx_status)(struct altera_tse_private *);
-	int (*init_dma)(struct altera_tse_private *);
-	void (*uninit_dma)(struct altera_tse_private *);
-	void (*start_rxdma)(struct altera_tse_private *);
+	void (*reset_dma)(struct altera_tse_private *priv);
+	void (*enable_txirq)(struct altera_tse_private *priv);
+	void (*enable_rxirq)(struct altera_tse_private *priv);
+	void (*disable_txirq)(struct altera_tse_private *priv);
+	void (*disable_rxirq)(struct altera_tse_private *priv);
+	void (*clear_txirq)(struct altera_tse_private *priv);
+	void (*clear_rxirq)(struct altera_tse_private *priv);
+	int (*tx_buffer)(struct altera_tse_private *priv,
+			 struct tse_buffer *buffer);
+	u32 (*tx_completions)(struct altera_tse_private *priv);
+	void (*add_rx_desc)(struct altera_tse_private *priv,
+			    struct tse_buffer *buffer);
+	u32 (*get_rx_status)(struct altera_tse_private *priv);
+	int (*init_dma)(struct altera_tse_private *priv);
+	void (*uninit_dma)(struct altera_tse_private *priv);
+	void (*start_rxdma)(struct altera_tse_private *priv);
 };
 
 /* This structure is private to each device.
-- 
2.19.1

[PATCH net-next 4/8] net: eth: altera: tse: add optional function to start tx dma

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Allow for optional start up of tx dma if the start_txdma
function is defined in altera_dmaops.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 drivers/net/ethernet/altera/altera_tse.h      | 1 +
 drivers/net/ethernet/altera/altera_tse_main.c | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h
index d5b97e02e6d6..7f246040135d 100644
--- a/drivers/net/ethernet/altera/altera_tse.h
+++ b/drivers/net/ethernet/altera/altera_tse.h
@@ -412,6 +412,7 @@ struct altera_dmaops {
 	int (*init_dma)(struct altera_tse_private *priv);
 	void (*uninit_dma)(struct altera_tse_private *priv);
 	void (*start_rxdma)(struct altera_tse_private *priv);
+	void (*start_txdma)(struct altera_tse_private *priv);
 };
 
 /* This structure is private to each device.
diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c
index 0c0e8f9bba9b..f6b6a14b1ce9 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -1256,6 +1256,9 @@ static int tse_open(struct net_device *dev)
 
 	priv->dmaops->start_rxdma(priv);
 
+	if (priv->dmaops->start_txdma)
+		priv->dmaops->start_txdma(priv);
+
 	/* Start MAC Rx/Tx */
 	spin_lock(&priv->mac_cfg_lock);
 	tse_set_mac(priv, true);
@@ -1658,6 +1661,7 @@ static const struct altera_dmaops altera_dtype_sgdma = {
 	.init_dma = sgdma_initialize,
 	.uninit_dma = sgdma_uninitialize,
 	.start_rxdma = sgdma_start_rxdma,
+	.start_txdma = NULL,
 };
 
 static const struct altera_dmaops altera_dtype_msgdma = {
@@ -1677,6 +1681,7 @@ static const struct altera_dmaops altera_dtype_msgdma = {
 	.init_dma = msgdma_initialize,
 	.uninit_dma = msgdma_uninitialize,
 	.start_rxdma = msgdma_start_rxdma,
+	.start_txdma = NULL,
 };
 
 static const struct of_device_id altera_tse_ids[] = {
-- 
2.19.1

[PATCH net-next 5/8] net: eth: altera: tse: Move common functions to altera_utils

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Move request_and_map and other shared functions to altera_utils. This
is the first step to moving common code out of tse specific code so
that it can be shared with future altera ethernet ip.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 drivers/net/ethernet/altera/altera_tse.h      | 45 ------------------
 .../net/ethernet/altera/altera_tse_ethtool.c  |  1 +
 drivers/net/ethernet/altera/altera_tse_main.c | 32 +------------
 drivers/net/ethernet/altera/altera_utils.c    | 30 ++++++++++++
 drivers/net/ethernet/altera/altera_utils.h    | 46 +++++++++++++++++++
 5 files changed, 78 insertions(+), 76 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h
index 7f246040135d..f435fb0eca90 100644
--- a/drivers/net/ethernet/altera/altera_tse.h
+++ b/drivers/net/ethernet/altera/altera_tse.h
@@ -500,49 +500,4 @@ struct altera_tse_private {
  */
 void altera_tse_set_ethtool_ops(struct net_device *);
 
-static inline
-u32 csrrd32(void __iomem *mac, size_t offs)
-{
-	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
-	return readl(paddr);
-}
-
-static inline
-u16 csrrd16(void __iomem *mac, size_t offs)
-{
-	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
-	return readw(paddr);
-}
-
-static inline
-u8 csrrd8(void __iomem *mac, size_t offs)
-{
-	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
-	return readb(paddr);
-}
-
-static inline
-void csrwr32(u32 val, void __iomem *mac, size_t offs)
-{
-	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
-
-	writel(val, paddr);
-}
-
-static inline
-void csrwr16(u16 val, void __iomem *mac, size_t offs)
-{
-	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
-
-	writew(val, paddr);
-}
-
-static inline
-void csrwr8(u8 val, void __iomem *mac, size_t offs)
-{
-	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
-
-	writeb(val, paddr);
-}
-
 #endif /* __ALTERA_TSE_H__ */
diff --git a/drivers/net/ethernet/altera/altera_tse_ethtool.c b/drivers/net/ethernet/altera/altera_tse_ethtool.c
index 7c367713c3e6..2998655ab316 100644
--- a/drivers/net/ethernet/altera/altera_tse_ethtool.c
+++ b/drivers/net/ethernet/altera/altera_tse_ethtool.c
@@ -33,6 +33,7 @@
 #include <linux/phy.h>
 
 #include "altera_tse.h"
+#include "altera_utils.h"
 
 #define TSE_STATS_LEN	31
 #define TSE_NUM_REGS	128
diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c
index f6b6a14b1ce9..b25d03506470 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -34,7 +34,6 @@
 #include <linux/if_vlan.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
-#include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/mii.h>
@@ -44,7 +43,7 @@
 #include <linux/of_net.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
-#include <linux/platform_device.h>
+#include <linux/ptp_classify.h>
 #include <linux/skbuff.h>
 #include <asm/cacheflush.h>
 
@@ -1332,35 +1331,6 @@ static struct net_device_ops altera_tse_netdev_ops = {
 	.ndo_validate_addr	= eth_validate_addr,
 };
 
-static int request_and_map(struct platform_device *pdev, const char *name,
-			   struct resource **res, void __iomem **ptr)
-{
-	struct resource *region;
-	struct device *device = &pdev->dev;
-
-	*res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
-	if (*res == NULL) {
-		dev_err(device, "resource %s not defined\n", name);
-		return -ENODEV;
-	}
-
-	region = devm_request_mem_region(device, (*res)->start,
-					 resource_size(*res), dev_name(device));
-	if (region == NULL) {
-		dev_err(device, "unable to request %s\n", name);
-		return -EBUSY;
-	}
-
-	*ptr = devm_ioremap_nocache(device, region->start,
-				    resource_size(region));
-	if (*ptr == NULL) {
-		dev_err(device, "ioremap_nocache of %s failed!", name);
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
 /* Probe Altera TSE MAC device
  */
 static int altera_tse_probe(struct platform_device *pdev)
diff --git a/drivers/net/ethernet/altera/altera_utils.c b/drivers/net/ethernet/altera/altera_utils.c
index d7eeb1713ad2..bc33b7f0b0c5 100644
--- a/drivers/net/ethernet/altera/altera_utils.c
+++ b/drivers/net/ethernet/altera/altera_utils.c
@@ -42,3 +42,33 @@ int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask)
 	u32 value = csrrd32(ioaddr, offs);
 	return (value & bit_mask) ? 0 : 1;
 }
+
+int request_and_map(struct platform_device *pdev, const char *name,
+		    struct resource **res, void __iomem **ptr)
+{
+	struct resource *region;
+	struct device *device = &pdev->dev;
+
+	*res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+	if (!*res) {
+		dev_err(device, "resource %s not defined\n", name);
+		return -ENODEV;
+	}
+
+	region = devm_request_mem_region(device, (*res)->start,
+					 resource_size(*res), dev_name(device));
+	if (!region) {
+		dev_err(device, "unable to request %s\n", name);
+		return -EBUSY;
+	}
+
+	*ptr = devm_ioremap_nocache(device, region->start,
+				    resource_size(region));
+	if (!*ptr) {
+		dev_err(device, "ioremap_nocache of %s failed!", name);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
diff --git a/drivers/net/ethernet/altera/altera_utils.h b/drivers/net/ethernet/altera/altera_utils.h
index baf100ccf587..bb7eff792bb7 100644
--- a/drivers/net/ethernet/altera/altera_utils.h
+++ b/drivers/net/ethernet/altera/altera_utils.h
@@ -14,7 +14,9 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/platform_device.h>
 
 #ifndef __ALTERA_UTILS_H__
 #define __ALTERA_UTILS_H__
@@ -23,5 +25,49 @@ void tse_set_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask);
 void tse_clear_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask);
 int tse_bit_is_set(void __iomem *ioaddr, size_t offs, u32 bit_mask);
 int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask);
+int request_and_map(struct platform_device *pdev, const char *name,
+		    struct resource **res, void __iomem **ptr);
+
+static inline u32 csrrd32(void __iomem *mac, size_t offs)
+{
+	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+	return readl(paddr);
+}
+
+static inline u16 csrrd16(void __iomem *mac, size_t offs)
+{
+	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+	return readw(paddr);
+}
+
+static inline u8 csrrd8(void __iomem *mac, size_t offs)
+{
+	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+	return readb(paddr);
+}
+
+static inline void csrwr32(u32 val, void __iomem *mac, size_t offs)
+{
+	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+	writel(val, paddr);
+}
+
+static inline void csrwr16(u16 val, void __iomem *mac, size_t offs)
+{
+	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+	writew(val, paddr);
+}
+
+static inline void csrwr8(u8 val, void __iomem *mac, size_t offs)
+{
+	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+	writeb(val, paddr);
+}
 
 #endif /* __ALTERA_UTILS_H__*/
-- 
2.19.1

[PATCH net-next 6/8] net: eth: altera: tse: add support for ptp and timestamping

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Add support for the ptp clock used with the tse, and update
the driver to support timestamping when enabled.  We also
enable debugfs entries for the ptp clock to allow some user
control and interaction with the ptp clock.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 drivers/net/ethernet/altera/Kconfig           |   1 +
 drivers/net/ethernet/altera/Makefile          |   3 +-
 drivers/net/ethernet/altera/altera_ptp.c      | 473 ++++++++++++++++++
 drivers/net/ethernet/altera/altera_ptp.h      |  77 +++
 drivers/net/ethernet/altera/altera_tse.h      |  10 +
 .../net/ethernet/altera/altera_tse_ethtool.c  |  28 ++
 drivers/net/ethernet/altera/altera_tse_main.c | 164 +++++-
 7 files changed, 754 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/ethernet/altera/altera_ptp.c
 create mode 100644 drivers/net/ethernet/altera/altera_ptp.h

diff --git a/drivers/net/ethernet/altera/Kconfig b/drivers/net/ethernet/altera/Kconfig
index fdddba51473e..36aee0fc0b51 100644
--- a/drivers/net/ethernet/altera/Kconfig
+++ b/drivers/net/ethernet/altera/Kconfig
@@ -2,6 +2,7 @@ config ALTERA_TSE
 	tristate "Altera Triple-Speed Ethernet MAC support"
 	depends on HAS_DMA
 	select PHYLIB
+	select PTP_1588_CLOCK
 	---help---
 	  This driver supports the Altera Triple-Speed (TSE) Ethernet MAC.
 
diff --git a/drivers/net/ethernet/altera/Makefile b/drivers/net/ethernet/altera/Makefile
index d4a187e45369..ad80be42fa26 100644
--- a/drivers/net/ethernet/altera/Makefile
+++ b/drivers/net/ethernet/altera/Makefile
@@ -4,4 +4,5 @@
 
 obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
 altera_tse-objs := altera_tse_main.o altera_tse_ethtool.o \
-altera_msgdma.o altera_sgdma.o altera_utils.o
+		   altera_msgdma.o altera_sgdma.o altera_utils.o \
+		   altera_ptp.o
diff --git a/drivers/net/ethernet/altera/altera_ptp.c b/drivers/net/ethernet/altera/altera_ptp.c
new file mode 100644
index 000000000000..4467b3c90c59
--- /dev/null
+++ b/drivers/net/ethernet/altera/altera_ptp.c
@@ -0,0 +1,473 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Altera PTP Hardware Clock (PHC) Linux driver
+ * Copyright (C) 2015-2016 Altera Corporation. All rights reserved.
+ * Copyright (C) 2017-2018 Intel Corporation. All rights reserved.
+ *
+ * Author(s):
+ *	Dalon Westergreen <dalon.westergreen@intel.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/gcd.h>
+#include <linux/module.h>
+#include <linux/math64.h>
+#include <linux/net_tstamp.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include "altera_ptp.h"
+#include "altera_utils.h"
+
+#define NOMINAL_PPB			1000000000ULL
+#define TOD_PERIOD_MAX			0xfffff
+#define TOD_PERIOD_MIN			0
+#define TOD_DRIFT_ADJUST_FNS_MAX	0xffff
+#define TOD_DRIFT_ADJUST_RATE_MAX	0xffff
+#define TOD_ADJUST_COUNT_MAX		0xfffff
+#define TOD_ADJUST_MS_MAX		(((((TOD_PERIOD_MAX) >> 16) + 1) * \
+					  ((TOD_ADJUST_COUNT_MAX) + 1)) /  \
+					 1000000UL)
+
+/* A fine ToD HW clock offset adjustment.
+ * To perform the fine offset adjustment the AdjustPeriod register is used
+ * to replace the Period register for AdjustCount clock cycles in hardware.
+ */
+static int fine_adjust_tod_clock(struct altera_ptp_private *priv,
+				 u32 adjust_period, u32 adjust_count)
+{
+	int limit;
+
+	csrwr32(adjust_period, priv->tod_ctrl, tod_csroffs(adjust_period));
+	csrwr32(adjust_count, priv->tod_ctrl, tod_csroffs(adjust_count));
+
+	/* Wait for present offset adjustment update to complete */
+	limit = TOD_ADJUST_MS_MAX;
+	while (limit--) {
+		if (!csrrd32(priv->tod_ctrl, tod_csroffs(adjust_count)))
+			break;
+		mdelay(1);
+	}
+	if (limit < 0)
+		return -EBUSY;
+
+	return 0;
+}
+
+/* A coarse ToD HW clock offset adjustment.
+ * The coarse time adjustment performs by adding or subtracting the delta value
+ * from the current ToD HW clock time.
+ */
+static int coarse_adjust_tod_clock(struct altera_ptp_private *priv, s64 delta)
+{
+	u64 seconds;
+	u32 seconds_msb;
+	u32 seconds_lsb;
+	u32 nanosec;
+	u64 now;
+
+	if (delta == 0)
+		goto out;
+
+	/* Get current time */
+	nanosec = csrrd32(priv->tod_ctrl, tod_csroffs(nanosec));
+	seconds_lsb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_lsb));
+	seconds_msb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_msb));
+
+	/* Calculate new time */
+	seconds = (((u64)(seconds_msb & 0x0000ffff)) << 32) | seconds_lsb;
+	now = seconds * NSEC_PER_SEC + nanosec + delta;
+
+	seconds = div_u64_rem(now, NSEC_PER_SEC, &nanosec);
+	seconds_msb = upper_32_bits(seconds) & 0x0000ffff;
+	seconds_lsb = lower_32_bits(seconds);
+
+	/* Set corrected time */
+	csrwr32(seconds_msb, priv->tod_ctrl, tod_csroffs(seconds_msb));
+	csrwr32(seconds_lsb, priv->tod_ctrl, tod_csroffs(seconds_lsb));
+	csrwr32(nanosec, priv->tod_ctrl, tod_csroffs(nanosec));
+
+out:
+	return 0;
+}
+
+static int adjust_fine(struct ptp_clock_info *ptp, long scaled_ppm)
+{
+	struct altera_ptp_private *priv =
+		container_of(ptp, struct altera_ptp_private, ptp_clock_ops);
+	unsigned long flags;
+	int ret = 0;
+	u64 ppb;
+	u32 tod_period;
+	u32 tod_rem;
+	u32 tod_drift_adjust_fns;
+	u32 tod_drift_adjust_rate;
+	unsigned long rate;
+
+	priv->scaled_ppm = scaled_ppm;
+
+	/* only unlock if it is currently locked */
+	if (mutex_is_locked(&priv->ppm_mutex))
+		mutex_unlock(&priv->ppm_mutex);
+
+	if (!priv->ptp_correct_freq)
+		goto out;
+
+	rate = clk_get_rate(priv->tod_clk);
+
+	/* From scaled_ppm_to_ppb */
+	ppb = 1 + scaled_ppm;
+	ppb *= 125;
+	ppb >>= 13;
+
+	ppb += NOMINAL_PPB;
+
+	tod_period = div_u64_rem(ppb << 16, rate, &tod_rem);
+	if (tod_period > TOD_PERIOD_MAX) {
+		ret = -ERANGE;
+		goto out;
+	}
+
+	/* The drift of ToD adjusted periodically by adding a drift_adjust_fns
+	 * correction value every drift_adjust_rate count of clock cycles.
+	 */
+	tod_drift_adjust_fns = tod_rem / gcd(tod_rem, rate);
+	tod_drift_adjust_rate = rate / gcd(tod_rem, rate);
+
+	while ((tod_drift_adjust_fns > TOD_DRIFT_ADJUST_FNS_MAX) |
+		(tod_drift_adjust_rate > TOD_DRIFT_ADJUST_RATE_MAX)) {
+		tod_drift_adjust_fns = tod_drift_adjust_fns >> 1;
+		tod_drift_adjust_rate = tod_drift_adjust_rate >> 1;
+	}
+
+	if (tod_drift_adjust_fns == 0)
+		tod_drift_adjust_rate = 0;
+
+	spin_lock_irqsave(&priv->tod_lock, flags);
+	csrwr32(tod_period, priv->tod_ctrl, tod_csroffs(period));
+	csrwr32(0, priv->tod_ctrl, tod_csroffs(adjust_period));
+	csrwr32(0, priv->tod_ctrl, tod_csroffs(adjust_count));
+	csrwr32(tod_drift_adjust_fns, priv->tod_ctrl,
+		tod_csroffs(drift_adjust));
+	csrwr32(tod_drift_adjust_rate, priv->tod_ctrl,
+		tod_csroffs(drift_adjust_rate));
+	spin_unlock_irqrestore(&priv->tod_lock, flags);
+
+out:
+	return ret;
+}
+
+static int adjust_time(struct ptp_clock_info *ptp, s64 delta)
+{
+	struct altera_ptp_private *priv =
+		container_of(ptp, struct altera_ptp_private, ptp_clock_ops);
+	int ret = 0;
+	u64 abs_delta;
+	unsigned long flags;
+	u32 period;
+	u32 diff;
+	u64 count;
+	u32 rem;
+
+	if (!priv->ptp_correct_offs)
+		goto out;
+
+	if (delta < 0)
+		abs_delta = -delta;
+	else
+		abs_delta = delta;
+
+	spin_lock_irqsave(&priv->tod_lock, flags);
+
+	/* Get the maximum possible value of the Period register offset
+	 * adjustment in nanoseconds scale. This depends on the current
+	 * Period register settings and the maximum and minimum possible
+	 * values of the Period register.
+	 */
+	period = csrrd32(priv->tod_ctrl, tod_csroffs(period));
+
+	if (delta < 0)
+		diff = (period - TOD_PERIOD_MIN) >> 16;
+	else
+		diff = (TOD_PERIOD_MAX - period) >> 16;
+
+	/* Find out the least number of cycles needed for the Period register
+	 * adjustment by delta nanoseconds.
+	 */
+	while (diff) {
+		count = div_u64_rem(abs_delta, diff, &rem);
+		if (rem == 0)
+			break;
+		diff--;
+	}
+
+	if (diff && count && count < TOD_ADJUST_COUNT_MAX) {
+		/* Perform the fine time offset adjustment */
+		if (delta < 0)
+			period -= (diff << 16);
+		else
+			period += (diff << 16);
+
+		ret = fine_adjust_tod_clock(priv, period, count);
+
+	} else {
+		/* Perform the coarse time offset adjustment */
+		ret = coarse_adjust_tod_clock(priv, delta);
+	}
+
+	spin_unlock_irqrestore(&priv->tod_lock, flags);
+
+out:
+	return ret;
+}
+
+static int get_time(struct ptp_clock_info *ptp, struct timespec64 *ts)
+{
+	struct altera_ptp_private *priv =
+		container_of(ptp, struct altera_ptp_private, ptp_clock_ops);
+	unsigned long flags;
+	u64 seconds;
+	u32 seconds_msb;
+	u32 seconds_lsb;
+	u32 nanosec;
+
+	spin_lock_irqsave(&priv->tod_lock, flags);
+	nanosec = csrrd32(priv->tod_ctrl, tod_csroffs(nanosec));
+	seconds_lsb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_lsb));
+	seconds_msb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_msb));
+	spin_unlock_irqrestore(&priv->tod_lock, flags);
+
+	seconds = (((u64)(seconds_msb & 0x0000ffff)) << 32) | seconds_lsb;
+
+	ts->tv_nsec = nanosec;
+	ts->tv_sec = (__kernel_time_t)seconds;
+
+	return 0;
+}
+
+static int set_time(struct ptp_clock_info *ptp, const struct timespec64 *ts)
+{
+	struct altera_ptp_private *priv =
+		container_of(ptp, struct altera_ptp_private, ptp_clock_ops);
+	unsigned long flags;
+	u32 seconds_msb = upper_32_bits(ts->tv_sec) & 0x0000ffff;
+	u32 seconds_lsb = lower_32_bits(ts->tv_sec);
+	u32 nanosec = lower_32_bits(ts->tv_nsec);
+
+	spin_lock_irqsave(&priv->tod_lock, flags);
+	csrwr32(seconds_msb, priv->tod_ctrl, tod_csroffs(seconds_msb));
+	csrwr32(seconds_lsb, priv->tod_ctrl, tod_csroffs(seconds_lsb));
+	csrwr32(nanosec, priv->tod_ctrl, tod_csroffs(nanosec));
+	spin_unlock_irqrestore(&priv->tod_lock, flags);
+
+	return 0;
+}
+
+static int enable_feature(struct ptp_clock_info *ptp,
+			  struct ptp_clock_request *request, int on)
+{
+	return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info altera_ptp_clock_ops = {
+	.owner = THIS_MODULE,
+	.name = "altera_ptp",
+	.max_adj = 500000000,
+	.n_alarm = 0,
+	.n_ext_ts = 0,
+	.n_per_out = 0,
+	.pps = 0,
+	.adjfine = adjust_fine,
+	.adjtime = adjust_time,
+	.gettime64 = get_time,
+	.settime64 = set_time,
+	.enable = enable_feature,
+};
+
+/* ptp debugfs */
+static ssize_t ptp_tod_read(struct file *filp, char __user *buffer,
+			    size_t count, loff_t *ppos)
+{
+	struct altera_ptp_private *priv = filp->private_data;
+	unsigned long flags;
+	u32 seconds_msb;
+	u32 seconds_lsb;
+	u32 nanosec;
+
+	if (*ppos != 0)
+		return 0;
+
+	if (count < (sizeof(u32) * 3))
+		return -ENOSPC;
+
+	spin_lock_irqsave(&priv->tod_lock, flags);
+	nanosec = csrrd32(priv->tod_ctrl, tod_csroffs(nanosec));
+	seconds_lsb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_lsb));
+	seconds_msb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_msb));
+	spin_unlock_irqrestore(&priv->tod_lock, flags);
+
+	if (copy_to_user(buffer, &seconds_msb, sizeof(u32)))
+		return -EFAULT;
+	buffer += sizeof(u32);
+
+	if (copy_to_user(buffer, &seconds_lsb, sizeof(u32)))
+		return -EFAULT;
+	buffer += sizeof(u32);
+
+	if (copy_to_user(buffer, &nanosec, sizeof(u32)))
+		return -EFAULT;
+
+	return (sizeof(u32) * 3);
+}
+
+static const struct file_operations ptp_dbg_tod_ops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.read = ptp_tod_read,
+	.write = NULL,
+};
+
+static ssize_t ptp_ppm_read(struct file *filp, char __user *buffer,
+			    size_t count, loff_t *ppos)
+{
+	struct altera_ptp_private *priv = filp->private_data;
+
+	if (*ppos != 0)
+		return 0;
+
+	if (count < sizeof(long))
+		return -ENOSPC;
+
+	if (mutex_lock_interruptible(&priv->ppm_mutex))
+		return -EAGAIN;
+
+	if (copy_to_user(buffer, &priv->scaled_ppm, sizeof(long)))
+		return -EFAULT;
+
+	return sizeof(long);
+}
+
+static const struct file_operations ptp_dbg_ppm_ops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.read = ptp_ppm_read,
+	.write = NULL,
+};
+
+int altera_ptp_dbg_init(struct altera_ptp_private *priv,
+			struct dentry *dfs_dir_root)
+{
+	struct dentry *dfs_dir;
+
+	dfs_dir = debugfs_create_dir("ptp", dfs_dir_root);
+
+	/* Use u32 instead of bool */
+	if (!debugfs_create_u32("correct_offset", 0600, dfs_dir,
+				&priv->ptp_correct_offs))
+		return -ENOMEM;
+
+	/* Use u32 instead of bool */
+	if (!debugfs_create_u32("correct_frequency", 0600, dfs_dir,
+				&priv->ptp_correct_freq))
+		return -ENOMEM;
+
+	if (!debugfs_create_file("tod", 0400, dfs_dir,
+				 (void *)priv, &ptp_dbg_tod_ops))
+		return -ENOMEM;
+
+	if (!debugfs_create_file("scaled_ppm", 0400, dfs_dir,
+				 (void *)priv, &ptp_dbg_ppm_ops))
+		return -ENOMEM;
+
+	return 0;
+}
+
+/* Initialize PTP control block registers */
+int altera_init_ptp(struct altera_ptp_private *priv)
+{
+	int ret = 0;
+	struct timespec64 now;
+
+	ret = adjust_fine(&priv->ptp_clock_ops, 0l);
+	if (ret != 0)
+		goto out;
+
+	/* Initialize the hardware clock to the system time */
+	getnstimeofday64(&now);
+	set_time(&priv->ptp_clock_ops, &now);
+
+	priv->ptp_correct_offs = true;
+	priv->ptp_correct_freq = true;
+
+	spin_lock_init(&priv->tod_lock);
+
+	/* we want the mutex locked by default */
+	mutex_init(&priv->ppm_mutex);
+	mutex_lock(&priv->ppm_mutex);
+
+out:
+	return ret;
+}
+
+/* Register the PTP clock driver to kernel */
+int altera_ptp_register(struct altera_ptp_private *priv, struct device *device)
+{
+	int ret = 0;
+
+	priv->ptp_clock_ops = altera_ptp_clock_ops;
+
+	priv->ptp_clock = ptp_clock_register(&priv->ptp_clock_ops, device);
+	if (IS_ERR(priv->ptp_clock)) {
+		priv->ptp_clock = NULL;
+		ret = -ENODEV;
+	}
+
+	if (priv->tod_clk)
+		ret = clk_prepare_enable(priv->tod_clk);
+
+	return ret;
+}
+
+/* Remove/unregister the ptp clock driver from the kernel */
+void altera_ptp_unregister(struct altera_ptp_private *priv)
+{
+	if (priv->ptp_clock) {
+		ptp_clock_unregister(priv->ptp_clock);
+		priv->ptp_clock = NULL;
+	}
+
+	if (priv->tod_clk)
+		clk_disable_unprepare(priv->tod_clk);
+}
+
+/* Common PTP probe function */
+int altera_ptp_probe(struct platform_device *pdev,
+		     struct altera_ptp_private *priv)
+{
+	int ret = -ENODEV;
+	struct resource *ptp_res;
+
+	priv->dev = (struct net_device *)platform_get_drvdata(pdev);
+
+	/* Time-of-Day (ToD) Clock address space */
+	ret = request_and_map(pdev, "tod_ctrl", &ptp_res,
+			      (void __iomem **)&priv->tod_ctrl);
+	if (ret)
+		goto err;
+
+	dev_info(&pdev->dev, "\tTOD Ctrl at 0x%08lx\n",
+		 (unsigned long)ptp_res->start);
+
+	/* Time-of-Day (ToD) Clock period clock */
+	priv->tod_clk = devm_clk_get(&pdev->dev, "tod_clk");
+	if (IS_ERR(priv->tod_clk)) {
+		dev_err(&pdev->dev, "cannot obtain ToD period clock\n");
+		ret = -ENXIO;
+		goto err;
+	}
+err:
+	return ret;
+}
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/altera/altera_ptp.h b/drivers/net/ethernet/altera/altera_ptp.h
new file mode 100644
index 000000000000..66cd11902743
--- /dev/null
+++ b/drivers/net/ethernet/altera/altera_ptp.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Altera PTP Hardware Clock (PHC) Linux driver
+ * Copyright (C) 2015-2016 Altera Corporation. All rights reserved.
+ * Copyright (C) 2017-2018 Intel Corporation. All rights reserved.
+ *
+ * Author(s):
+ *	Dalon Westergreen <dalon.westergreen@intel.com>
+ */
+
+#ifndef __ALTERA_PTP_H__
+#define __ALTERA_PTP_H__
+
+#include <linux/debugfs.h>
+#include <linux/netdevice.h>
+#include <linux/ptp_clock_kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+
+/* Altera Time-of-Day (ToD) clock register space. */
+struct altera_eth_tod {
+	u32 seconds_msb;
+	u32 seconds_lsb;
+	u32 nanosec;
+	u32 reserved1[0x1];
+	u32 period;
+	u32 adjust_period;
+	u32 adjust_count;
+	u32 drift_adjust;
+	u32 drift_adjust_rate;
+};
+
+#define tod_csroffs(a)	(offsetof(struct altera_eth_tod, a))
+
+struct altera_ptp_private {
+	struct net_device *dev;
+
+	struct ptp_clock_info ptp_clock_ops;
+	struct ptp_clock *ptp_clock;
+
+	/* Time-of-Day (ToD) Clock address space */
+	struct altera_eth_tod __iomem *tod_ctrl;
+	struct clk *tod_clk;
+
+	/* Ability to turn on and turn off PTP offset correction and
+	 * frequency correction
+	 */
+	u32 ptp_correct_offs;
+	u32 ptp_correct_freq;
+
+	/* ToD clock registers protection */
+	spinlock_t tod_lock;
+
+	/* Debug for PTP interface with mutex for passing
+	 * scaled_ppm from adjfine to debugfs
+	 */
+	struct mutex ppm_mutex;
+	long scaled_ppm;
+};
+
+struct altera_timestamp {
+	u32 tstamp[3];
+};
+
+void altera_tx_hwtstamp(struct altera_ptp_private *priv, struct sk_buff *skb,
+			struct altera_timestamp *tstamp);
+void altera_rx_hwtstamp(struct altera_ptp_private *priv, struct sk_buff *skb,
+			struct altera_timestamp *tstamp);
+int altera_init_ptp(struct altera_ptp_private *priv);
+void altera_uninit_ptp(struct altera_ptp_private *priv);
+int altera_ptp_register(struct altera_ptp_private *priv, struct device *device);
+void altera_ptp_unregister(struct altera_ptp_private *priv);
+int altera_ptp_probe(struct platform_device *pdev,
+		     struct altera_ptp_private *priv);
+int altera_ptp_dbg_init(struct altera_ptp_private *priv,
+			struct dentry *dfs_dir);
+
+#endif /* __ALTERA_PTP_H__ */
diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h
index f435fb0eca90..508d5d015ca6 100644
--- a/drivers/net/ethernet/altera/altera_tse.h
+++ b/drivers/net/ethernet/altera/altera_tse.h
@@ -39,6 +39,8 @@
 #include <linux/netdevice.h>
 #include <linux/phy.h>
 
+#include "altera_ptp.h"
+
 #define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR	10000
 #define ALTERA_TSE_MAC_FIFO_WIDTH		4	/* TX/RX FIFO width in
 							 * bytes
@@ -428,6 +430,12 @@ struct altera_tse_private {
 	/* TSE Revision */
 	u32	revision;
 
+	/* Shared PTP structure */
+	struct altera_ptp_private ptp_priv;
+	int hwts_tx_en;
+	int hwts_rx_en;
+	u32 ptp_enable;
+
 	/* mSGDMA Rx Dispatcher address space */
 	void __iomem *rx_dma_csr;
 	void __iomem *rx_dma_desc;
@@ -494,6 +502,8 @@ struct altera_tse_private {
 	u32 msg_enable;
 
 	struct altera_dmaops *dmaops;
+
+	struct dentry *dfs_dir;
 };
 
 /* Function prototypes
diff --git a/drivers/net/ethernet/altera/altera_tse_ethtool.c b/drivers/net/ethernet/altera/altera_tse_ethtool.c
index 2998655ab316..eeb6e5558c6a 100644
--- a/drivers/net/ethernet/altera/altera_tse_ethtool.c
+++ b/drivers/net/ethernet/altera/altera_tse_ethtool.c
@@ -30,6 +30,7 @@
 #include <linux/ethtool.h>
 #include <linux/kernel.h>
 #include <linux/netdevice.h>
+#include <linux/net_tstamp.h>
 #include <linux/phy.h>
 
 #include "altera_tse.h"
@@ -234,6 +235,32 @@ static void tse_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 		buf[i] = csrrd32(priv->mac_dev, i * 4);
 }
 
+static int tse_get_ts_info(struct net_device *dev,
+			   struct ethtool_ts_info *info)
+{
+	struct altera_tse_private *priv = netdev_priv(dev);
+
+	if (priv->ptp_enable) {
+		if (priv->ptp_priv.ptp_clock)
+			info->phc_index =
+				ptp_clock_index(priv->ptp_priv.ptp_clock);
+
+		info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
+					SOF_TIMESTAMPING_RX_HARDWARE |
+					SOF_TIMESTAMPING_RAW_HARDWARE;
+
+		info->tx_types = (1 << HWTSTAMP_TX_OFF) |
+						 (1 << HWTSTAMP_TX_ON);
+
+		info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
+						   (1 << HWTSTAMP_FILTER_ALL);
+
+		return 0;
+	} else {
+		return ethtool_op_get_ts_info(dev, info);
+	}
+}
+
 static const struct ethtool_ops tse_ethtool_ops = {
 	.get_drvinfo = tse_get_drvinfo,
 	.get_regs_len = tse_reglen,
@@ -246,6 +273,7 @@ static const struct ethtool_ops tse_ethtool_ops = {
 	.set_msglevel = tse_set_msglevel,
 	.get_link_ksettings = phy_ethtool_get_link_ksettings,
 	.set_link_ksettings = phy_ethtool_set_link_ksettings,
+	.get_ts_info = tse_get_ts_info,
 };
 
 void altera_tse_set_ethtool_ops(struct net_device *netdev)
diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c
index b25d03506470..3b0c940189be 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -29,14 +29,18 @@
  */
 
 #include <linux/atomic.h>
+#include <linux/clk.h>
+#include <linux/debugfs.h>
 #include <linux/delay.h>
 #include <linux/etherdevice.h>
+#include <linux/if_ether.h>
 #include <linux/if_vlan.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/mii.h>
+#include <linux/net_tstamp.h>
 #include <linux/netdevice.h>
 #include <linux/of_device.h>
 #include <linux/of_mdio.h>
@@ -51,6 +55,7 @@
 #include "altera_tse.h"
 #include "altera_sgdma.h"
 #include "altera_msgdma.h"
+#include "altera_ptp.h"
 
 static atomic_t instance_count = ATOMIC_INIT(~0);
 /* Module parameters */
@@ -609,7 +614,14 @@ static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
 	if (ret)
 		goto out;
 
-	skb_tx_timestamp(skb);
+	/* Provide a hardware time stamp if requested.
+	 */
+	if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
+		     priv->hwts_tx_en))
+		/* declare that device is doing timestamping */
+		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
+	else
+		skb_tx_timestamp(skb);
 
 	priv->tx_prod++;
 	dev->stats.tx_bytes += skb->len;
@@ -1250,6 +1262,13 @@ static int tse_open(struct net_device *dev)
 	if (dev->phydev)
 		phy_start(dev->phydev);
 
+	ret = altera_init_ptp(&priv->ptp_priv);
+	if (ret)
+		netdev_warn(dev, "Failed PTP initialization\n");
+
+	priv->hwts_tx_en = 0;
+	priv->hwts_rx_en = 0;
+
 	napi_enable(&priv->napi);
 	netif_start_queue(dev);
 
@@ -1321,6 +1340,83 @@ static int tse_shutdown(struct net_device *dev)
 	return 0;
 }
 
+/* ioctl to configure timestamping */
+static int tse_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+	struct altera_tse_private *priv = netdev_priv(dev);
+	struct hwtstamp_config config;
+
+	if (!netif_running(dev))
+		return -EINVAL;
+
+	if (!priv->ptp_enable)	{
+		netdev_alert(priv->dev, "Timestamping not supported");
+		return -EOPNOTSUPP;
+	}
+
+	if (cmd == SIOCSHWTSTAMP) {
+		if (copy_from_user(&config, ifr->ifr_data,
+				   sizeof(struct hwtstamp_config)))
+			return -EFAULT;
+
+		if (config.flags)
+			return -EINVAL;
+
+		switch (config.tx_type) {
+		case HWTSTAMP_TX_OFF:
+			priv->hwts_tx_en = 0;
+			break;
+		case HWTSTAMP_TX_ON:
+			priv->hwts_tx_en = 1;
+			break;
+		default:
+			return -ERANGE;
+		}
+
+		switch (config.rx_filter) {
+		case HWTSTAMP_FILTER_NONE:
+			priv->hwts_rx_en = 0;
+			config.rx_filter = HWTSTAMP_FILTER_NONE;
+			break;
+		default:
+			priv->hwts_rx_en = 1;
+			config.rx_filter = HWTSTAMP_FILTER_ALL;
+			break;
+		}
+
+		if (copy_to_user(ifr->ifr_data, &config,
+				 sizeof(struct hwtstamp_config)))
+			return -EFAULT;
+		else
+			return 0;
+	}
+
+	if (cmd == SIOCGHWTSTAMP) {
+		config.flags = 0;
+
+		if (priv->hwts_tx_en)
+			config.tx_type = HWTSTAMP_TX_ON;
+		else
+			config.tx_type = HWTSTAMP_TX_OFF;
+
+		if (priv->hwts_rx_en)
+			config.rx_filter = HWTSTAMP_FILTER_ALL;
+		else
+			config.rx_filter = HWTSTAMP_FILTER_NONE;
+
+		if (copy_to_user(ifr->ifr_data, &config,
+				 sizeof(struct hwtstamp_config)))
+			return -EFAULT;
+		else
+			return 0;
+	}
+
+	if (!dev->phydev)
+		return -EINVAL;
+
+	return phy_mii_ioctl(dev->phydev, ifr, cmd);
+}
+
 static struct net_device_ops altera_tse_netdev_ops = {
 	.ndo_open		= tse_open,
 	.ndo_stop		= tse_shutdown,
@@ -1329,8 +1425,44 @@ static struct net_device_ops altera_tse_netdev_ops = {
 	.ndo_set_rx_mode	= tse_set_rx_mode,
 	.ndo_change_mtu		= tse_change_mtu,
 	.ndo_validate_addr	= eth_validate_addr,
+	.ndo_do_ioctl		= tse_do_ioctl,
 };
 
+/* Debugfs entries */
+int altera_tse_dbg_init(struct net_device *dev)
+{
+	struct altera_tse_private *priv = netdev_priv(dev);
+	char *buf;
+
+	buf = kasprintf(GFP_KERNEL, "%s_%s",
+			ALTERA_TSE_RESOURCE_NAME, dev->name);
+
+	priv->dfs_dir = debugfs_create_dir(buf, NULL);
+	if (!priv->dfs_dir) {
+		netdev_err(dev, "debugfs create directory failed\n");
+		goto err_dfs;
+	}
+
+	if (priv->ptp_enable)
+		if (altera_ptp_dbg_init(&priv->ptp_priv, priv->dfs_dir))
+			goto err_entry;
+
+	return 0;
+
+err_entry:
+	debugfs_remove_recursive(priv->dfs_dir);
+	priv->dfs_dir = NULL;
+err_dfs:
+	return -ENOMEM;
+}
+
+static void altera_tse_dbg_exit(struct net_device *dev)
+{
+	struct altera_tse_private *priv = netdev_priv(dev);
+
+	debugfs_remove_recursive(priv->dfs_dir);
+}
+
 /* Probe Altera TSE MAC device
  */
 static int altera_tse_probe(struct platform_device *pdev)
@@ -1580,6 +1712,31 @@ static int altera_tse_probe(struct platform_device *pdev)
 		netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret);
 		goto err_init_phy;
 	}
+
+	priv->ptp_enable = of_property_read_bool(pdev->dev.of_node,
+						 "altr,has-ptp");
+	dev_info(&pdev->dev, "PTP Enable: %d\n", priv->ptp_enable);
+
+	if (priv->ptp_enable) {
+		/* MAP PTP */
+		ret = altera_ptp_probe(pdev, &priv->ptp_priv);
+		if (ret) {
+			dev_err(&pdev->dev, "cannot map PTP\n");
+			goto err_init_phy;
+		}
+		ret = altera_ptp_register(&priv->ptp_priv,
+					  priv->device);
+		if (ret) {
+			dev_err(&pdev->dev, "Failed to register PTP clock\n");
+			ret = -ENXIO;
+			goto err_init_phy;
+		}
+	}
+
+#ifdef CONFIG_DEBUG_FS
+	if (altera_tse_dbg_init(ndev))
+		goto err_init_phy;
+#endif
 	return 0;
 
 err_init_phy:
@@ -1606,7 +1763,12 @@ static int altera_tse_remove(struct platform_device *pdev)
 			of_phy_deregister_fixed_link(priv->device->of_node);
 	}
 
+#ifdef CONFIG_DEBUG_FS
+	altera_tse_dbg_exit(ndev);
+#endif
 	platform_set_drvdata(pdev, NULL);
+	if (priv->ptp_enable)
+		altera_ptp_unregister(&priv->ptp_priv);
 	altera_tse_mdio_destroy(ndev);
 	unregister_netdev(ndev);
 	free_netdev(ndev);
-- 
2.19.1

[PATCH net-next 7/8] net: eth: altera: tse: add msgdma prefetcher

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Add support for the mSGDMA prefetcher.  The prefetcher adds support
for a linked list of descriptors in system memory.  The prefetcher
feeds these to the mSGDMA dispatcher.

The prefetcher is configured to poll for the next descriptor in the
list to be owned by hardware, then pass the descriptor to the
dispatcher.  It will then poll the next descriptor until it is
owned by hardware.

The dispatcher responses are written back to the appropriate
descriptor, and the owned by hardware bit is cleared.

The driver sets up a linked list twice the tx and rx ring sizes,
with the last descriptor pointing back to the first.  This ensures
that the ring of descriptors will always have inactive descriptors
preventing the prefetcher from looping over and reusing descriptors
inappropriately.  The prefetcher will continuously loop over these
descriptors.  The driver modifies descriptors as required to update
the skb address and length as well as the owned by hardware bit.

In addition to the above, the mSGDMA prefetcher can be used to
handle rx and tx timestamps coming from the ethernet ip.  These
can be included in the prefetcher response in the descriptor.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 drivers/net/ethernet/altera/Makefile          |   2 +-
 .../altera/altera_msgdma_prefetcher.c         | 433 ++++++++++++++++++
 .../altera/altera_msgdma_prefetcher.h         |  30 ++
 .../altera/altera_msgdmahw_prefetcher.h       |  87 ++++
 drivers/net/ethernet/altera/altera_tse.h      |  14 +
 drivers/net/ethernet/altera/altera_tse_main.c |  51 +++
 6 files changed, 616 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
 create mode 100644 drivers/net/ethernet/altera/altera_msgdma_prefetcher.h
 create mode 100644 drivers/net/ethernet/altera/altera_msgdmahw_prefetcher.h

diff --git a/drivers/net/ethernet/altera/Makefile b/drivers/net/ethernet/altera/Makefile
index ad80be42fa26..73b32876f126 100644
--- a/drivers/net/ethernet/altera/Makefile
+++ b/drivers/net/ethernet/altera/Makefile
@@ -5,4 +5,4 @@
 obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
 altera_tse-objs := altera_tse_main.o altera_tse_ethtool.o \
 		   altera_msgdma.o altera_sgdma.o altera_utils.o \
-		   altera_ptp.o
+		   altera_ptp.o altera_msgdma_prefetcher.o
diff --git a/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
new file mode 100644
index 000000000000..55b475e9e15b
--- /dev/null
+++ b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
@@ -0,0 +1,433 @@
+// SPDX-License-Identifier: GPL-2.0
+/* MSGDMA Prefetcher driver for Altera ethernet devices
+ *
+ * Copyright (C) 2018 Intel Corporation. All rights reserved.
+ * Author(s):
+ *   Dalon Westergreen <dalon.westergreen@intel.com>
+ */
+
+#include <linux/list.h>
+#include <linux/netdevice.h>
+#include <linux/net_tstamp.h>
+#include "altera_utils.h"
+#include "altera_tse.h"
+#include "altera_msgdma.h"
+#include "altera_msgdmahw.h"
+#include "altera_msgdma_prefetcher.h"
+#include "altera_msgdmahw_prefetcher.h"
+
+int msgdma_pref_initialize(struct altera_tse_private *priv)
+{
+	int i;
+	struct msgdma_pref_extended_desc *rx_descs;
+	struct msgdma_pref_extended_desc *tx_descs;
+	dma_addr_t rx_descsphys;
+	dma_addr_t tx_descsphys;
+	u32 rx_ring_size;
+	u32 tx_ring_size;
+
+	priv->pref_rxdescphys = (dma_addr_t)0;
+	priv->pref_txdescphys = (dma_addr_t)0;
+
+	/* we need to allocate more pref descriptors than ringsize, for now
+	 * just double ringsize
+	 */
+	rx_ring_size = priv->rx_ring_size * 2;
+	tx_ring_size = priv->tx_ring_size * 2;
+
+	/* The prefetcher requires the descriptors to be aligned to the
+	 * descriptor read/write master's data width which worst case is
+	 * 512 bits.  Currently we DO NOT CHECK THIS and only support 32-bit
+	 * prefetcher masters.
+	 */
+
+	/* allocate memory for rx descriptors */
+	priv->pref_rxdesc =
+		dma_zalloc_coherent(priv->device,
+				    sizeof(struct msgdma_pref_extended_desc)
+				    * rx_ring_size,
+				    &priv->pref_rxdescphys, GFP_KERNEL);
+
+	if (!priv->pref_rxdesc)
+		goto err_rx;
+
+	/* allocate memory for tx descriptors */
+	priv->pref_txdesc =
+		dma_zalloc_coherent(priv->device,
+				    sizeof(struct msgdma_pref_extended_desc)
+				    * tx_ring_size,
+				    &priv->pref_txdescphys, GFP_KERNEL);
+
+	if (!priv->pref_txdesc)
+		goto err_tx;
+
+	/* setup base descriptor ring for tx & rx */
+	rx_descs = (struct msgdma_pref_extended_desc *)priv->pref_rxdesc;
+	tx_descs = (struct msgdma_pref_extended_desc *)priv->pref_txdesc;
+	tx_descsphys = priv->pref_txdescphys;
+	rx_descsphys = priv->pref_rxdescphys;
+
+	/* setup RX descriptors */
+	priv->pref_rx_prod = 0;
+	for (i = 0; i < rx_ring_size; i++) {
+		rx_descsphys = priv->pref_rxdescphys +
+			(((i + 1) % rx_ring_size) *
+			sizeof(struct msgdma_pref_extended_desc));
+		rx_descs[i].next_desc_lo = lower_32_bits(rx_descsphys);
+		rx_descs[i].next_desc_hi = upper_32_bits(rx_descsphys);
+		rx_descs[i].stride = MSGDMA_DESC_RX_STRIDE;
+		/* burst set to 0 so it defaults to max configured */
+		/* set seq number to desc number */
+		rx_descs[i].burst_seq_num = i;
+	}
+
+	/* setup TX descriptors */
+	for (i = 0; i < tx_ring_size; i++) {
+		tx_descsphys = priv->pref_txdescphys +
+			(((i + 1) % tx_ring_size) *
+			sizeof(struct msgdma_pref_extended_desc));
+		tx_descs[i].next_desc_lo = lower_32_bits(tx_descsphys);
+		tx_descs[i].next_desc_hi = upper_32_bits(tx_descsphys);
+		tx_descs[i].stride = MSGDMA_DESC_TX_STRIDE;
+		/* burst set to 0 so it defaults to max configured */
+		/* set seq number to desc number */
+		tx_descs[i].burst_seq_num = i;
+	}
+
+	if (netif_msg_ifup(priv))
+		netdev_info(priv->dev, "%s: RX Desc mem at 0x%x\n", __func__,
+			    priv->pref_rxdescphys);
+
+	if (netif_msg_ifup(priv))
+		netdev_info(priv->dev, "%s: TX Desc mem at 0x%x\n", __func__,
+			    priv->pref_txdescphys);
+
+	return 0;
+
+err_tx:
+	dma_free_coherent(priv->device,
+			  sizeof(struct msgdma_pref_extended_desc)
+			  * rx_ring_size,
+			  priv->pref_rxdesc, priv->pref_rxdescphys);
+err_rx:
+	return -ENOMEM;
+}
+
+void msgdma_pref_uninitialize(struct altera_tse_private *priv)
+{
+	if (priv->pref_rxdesc)
+		dma_free_coherent(priv->device,
+				  sizeof(struct msgdma_pref_extended_desc)
+				  * priv->rx_ring_size * 2,
+				  priv->pref_rxdesc, priv->pref_rxdescphys);
+
+	if (priv->pref_txdesc)
+		dma_free_coherent(priv->device,
+				  sizeof(struct msgdma_pref_extended_desc)
+				  * priv->rx_ring_size * 2,
+				  priv->pref_txdesc, priv->pref_txdescphys);
+}
+
+void msgdma_pref_enable_txirq(struct altera_tse_private *priv)
+{
+	tse_set_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control),
+		    MSGDMA_PREF_CTL_GLOBAL_INTR);
+}
+
+void msgdma_pref_disable_txirq(struct altera_tse_private *priv)
+{
+	tse_clear_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control),
+		      MSGDMA_PREF_CTL_GLOBAL_INTR);
+}
+
+void msgdma_pref_clear_txirq(struct altera_tse_private *priv)
+{
+	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr,
+		msgdma_pref_csroffs(status));
+}
+
+void msgdma_pref_enable_rxirq(struct altera_tse_private *priv)
+{
+	tse_set_bit(priv->rx_pref_csr, msgdma_pref_csroffs(control),
+		    MSGDMA_PREF_CTL_GLOBAL_INTR);
+}
+
+void msgdma_pref_disable_rxirq(struct altera_tse_private *priv)
+{
+	tse_clear_bit(priv->rx_pref_csr, msgdma_pref_csroffs(control),
+		      MSGDMA_PREF_CTL_GLOBAL_INTR);
+}
+
+void msgdma_pref_clear_rxirq(struct altera_tse_private *priv)
+{
+	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->rx_pref_csr,
+		msgdma_pref_csroffs(status));
+}
+
+static u64 timestamp_to_ns(struct msgdma_pref_extended_desc *desc)
+{
+	u64 ns = 0;
+	u64 second;
+	u32 tmp;
+
+	tmp = desc->timestamp_96b[0] >> 16;
+	tmp |= (desc->timestamp_96b[1] << 16);
+
+	second = desc->timestamp_96b[2];
+	second <<= 16;
+	second |= ((desc->timestamp_96b[1] & 0xffff0000) >> 16);
+
+	ns = second * NSEC_PER_SEC + tmp;
+
+	return ns;
+}
+
+/* Setup TX descriptor
+ *   -> this should never be called when a descriptor isn't available
+ */
+
+int msgdma_pref_tx_buffer(struct altera_tse_private *priv,
+			  struct tse_buffer *buffer)
+{
+	u32 desc_entry = priv->tx_prod % (priv->tx_ring_size * 2);
+	struct msgdma_pref_extended_desc *tx_descs = priv->pref_txdesc;
+
+	/* if for some reason the descriptor is still owned by hardware */
+	if (unlikely(tx_descs[desc_entry].desc_control
+		     & MSGDMA_PREF_DESC_CTL_OWNED_BY_HW))
+		return NETDEV_TX_BUSY;
+
+	/* write descriptor entries */
+	tx_descs[desc_entry].len = buffer->len;
+	tx_descs[desc_entry].read_addr_lo = lower_32_bits(buffer->dma_addr);
+	tx_descs[desc_entry].read_addr_hi = upper_32_bits(buffer->dma_addr);
+
+	/* set the control bits and set owned by hw */
+	tx_descs[desc_entry].desc_control = (MSGDMA_DESC_CTL_TX_SINGLE
+			| MSGDMA_PREF_DESC_CTL_OWNED_BY_HW);
+
+	if (netif_msg_tx_queued(priv))
+		netdev_info(priv->dev, "%s: cons: %d prod: %d",
+			    __func__, priv->tx_cons, priv->tx_prod);
+
+	return 0;
+}
+
+u32 msgdma_pref_tx_completions(struct altera_tse_private *priv)
+{
+	u32 control;
+	u32 ready = 0;
+	u32 cons = priv->tx_cons;
+	u32 desc_ringsize = priv->tx_ring_size * 2;
+	u32 ringsize = priv->tx_ring_size;
+	u64 ns = 0;
+	struct msgdma_pref_extended_desc *cur;
+	struct tse_buffer *tx_buff;
+	struct skb_shared_hwtstamps shhwtstamp;
+	int i;
+
+	if (netif_msg_tx_done(priv))
+		for (i = 0; i < desc_ringsize; i++)
+			netdev_info(priv->dev, "%s: desc: %d control 0x%x\n",
+				    __func__, i,
+				    priv->pref_txdesc[i].desc_control);
+
+	cur = &priv->pref_txdesc[cons % desc_ringsize];
+	control = cur->desc_control;
+	tx_buff = &priv->tx_ring[cons % ringsize];
+
+	while (!(control & MSGDMA_PREF_DESC_CTL_OWNED_BY_HW) &&
+	       (priv->tx_prod != (cons + ready)) && control) {
+		if (skb_shinfo(tx_buff->skb)->tx_flags & SKBTX_IN_PROGRESS) {
+			/* Timestamping is enabled, pass timestamp back */
+			ns = timestamp_to_ns(cur);
+			memset(&shhwtstamp, 0,
+			       sizeof(struct skb_shared_hwtstamps));
+			shhwtstamp.hwtstamp = ns_to_ktime(ns);
+			skb_tstamp_tx(tx_buff->skb, &shhwtstamp);
+		}
+
+		if (netif_msg_tx_done(priv))
+			netdev_info(priv->dev, "%s: cur: %d ts: %lld ns\n",
+				    __func__,
+				    ((cons + ready) % desc_ringsize), ns);
+
+		/* clear data */
+		cur->desc_control = 0;
+		cur->timestamp_96b[0] = 0;
+		cur->timestamp_96b[1] = 0;
+		cur->timestamp_96b[2] = 0;
+
+		ready++;
+		cur = &priv->pref_txdesc[(cons + ready) % desc_ringsize];
+		tx_buff = &priv->tx_ring[(cons + ready) % ringsize];
+		control = cur->desc_control;
+	}
+
+	return ready;
+}
+
+void msgdma_pref_reset(struct altera_tse_private *priv)
+{
+	int counter;
+
+	/* turn off polling */
+	tse_clear_bit(priv->rx_pref_csr, msgdma_pref_csroffs(control),
+		      MSGDMA_PREF_CTL_DESC_POLL_EN);
+	tse_clear_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control),
+		      MSGDMA_PREF_CTL_DESC_POLL_EN);
+
+	/* Reset the RX Prefetcher */
+	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->rx_pref_csr,
+		msgdma_pref_csroffs(status));
+	csrwr32(MSGDMA_PREF_CTL_RESET, priv->rx_pref_csr,
+		msgdma_pref_csroffs(control));
+
+	counter = 0;
+	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
+		if (tse_bit_is_clear(priv->rx_pref_csr,
+				     msgdma_pref_csroffs(control),
+				     MSGDMA_PREF_CTL_RESET))
+			break;
+		udelay(1);
+	}
+
+	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
+		netif_warn(priv, drv, priv->dev,
+			   "TSE Rx Prefetcher reset bit never cleared!\n");
+
+	/* clear all status bits */
+	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr,
+		msgdma_pref_csroffs(status));
+
+	/* Reset the TX Prefetcher */
+	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr,
+		msgdma_pref_csroffs(status));
+	csrwr32(MSGDMA_PREF_CTL_RESET, priv->tx_pref_csr,
+		msgdma_pref_csroffs(control));
+
+	counter = 0;
+	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
+		if (tse_bit_is_clear(priv->tx_pref_csr,
+				     msgdma_pref_csroffs(control),
+				     MSGDMA_PREF_CTL_RESET))
+			break;
+		udelay(1);
+	}
+
+	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
+		netif_warn(priv, drv, priv->dev,
+			   "TSE Tx Prefetcher reset bit never cleared!\n");
+
+	/* clear all status bits */
+	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr,
+		msgdma_pref_csroffs(status));
+
+	/* Reset mSGDMA dispatchers*/
+	msgdma_reset(priv);
+}
+
+/* Setup the RX and TX prefetchers to poll the descriptor chain */
+void msgdma_pref_start_rxdma(struct altera_tse_private *priv)
+{
+	csrwr32(priv->rx_poll_freq, priv->rx_pref_csr,
+		msgdma_pref_csroffs(desc_poll_freq));
+	csrwr32(lower_32_bits(priv->pref_rxdescphys), priv->rx_pref_csr,
+		msgdma_pref_csroffs(next_desc_lo));
+	csrwr32(upper_32_bits(priv->pref_rxdescphys), priv->rx_pref_csr,
+		msgdma_pref_csroffs(next_desc_hi));
+	tse_set_bit(priv->rx_pref_csr, msgdma_pref_csroffs(control),
+		    MSGDMA_PREF_CTL_DESC_POLL_EN | MSGDMA_PREF_CTL_RUN);
+}
+
+void msgdma_pref_start_txdma(struct altera_tse_private *priv)
+{
+	csrwr32(priv->tx_poll_freq, priv->tx_pref_csr,
+		msgdma_pref_csroffs(desc_poll_freq));
+	csrwr32(lower_32_bits(priv->pref_txdescphys), priv->tx_pref_csr,
+		msgdma_pref_csroffs(next_desc_lo));
+	csrwr32(upper_32_bits(priv->pref_txdescphys), priv->tx_pref_csr,
+		msgdma_pref_csroffs(next_desc_hi));
+	tse_set_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control),
+		    MSGDMA_PREF_CTL_DESC_POLL_EN | MSGDMA_PREF_CTL_RUN);
+}
+
+/* Add MSGDMA Prefetcher Descriptor to descriptor list
+ *   -> This should never be called when a descriptor isn't available
+ */
+void msgdma_pref_add_rx_desc(struct altera_tse_private *priv,
+			     struct tse_buffer *rxbuffer)
+{
+	struct msgdma_pref_extended_desc *rx_descs = priv->pref_rxdesc;
+	u32 desc_entry = priv->pref_rx_prod % (priv->rx_ring_size * 2);
+
+	/* write descriptor entries */
+	rx_descs[desc_entry].len = priv->rx_dma_buf_sz;
+	rx_descs[desc_entry].write_addr_lo = lower_32_bits(rxbuffer->dma_addr);
+	rx_descs[desc_entry].write_addr_hi = upper_32_bits(rxbuffer->dma_addr);
+
+	/* set the control bits and set owned by hw */
+	rx_descs[desc_entry].desc_control = (MSGDMA_DESC_CTL_END_ON_EOP
+			| MSGDMA_DESC_CTL_END_ON_LEN
+			| MSGDMA_DESC_CTL_TR_COMP_IRQ
+			| MSGDMA_DESC_CTL_EARLY_IRQ
+			| MSGDMA_DESC_CTL_TR_ERR_IRQ
+			| MSGDMA_DESC_CTL_GO
+			| MSGDMA_PREF_DESC_CTL_OWNED_BY_HW);
+
+	/* we need to keep a separate one for rx as RX_DESCRIPTORS are
+	 * pre-configured at startup
+	 */
+	priv->pref_rx_prod++;
+
+	if (netif_msg_rx_status(priv)) {
+		netdev_info(priv->dev, "%s: desc: %d buf: %d control 0x%x\n",
+			    __func__, desc_entry,
+			    priv->rx_prod % priv->rx_ring_size,
+			    priv->pref_rxdesc[desc_entry].desc_control);
+	}
+}
+
+u32 msgdma_pref_rx_status(struct altera_tse_private *priv)
+{
+	u32 rxstatus = 0;
+	u32 pktlength;
+	u32 pktstatus;
+	u64 ns = 0;
+	u32 entry = priv->rx_cons % priv->rx_ring_size;
+	u32 desc_entry = priv->rx_prod % (priv->rx_ring_size * 2);
+	struct msgdma_pref_extended_desc *rx_descs = priv->pref_rxdesc;
+	struct skb_shared_hwtstamps *shhwtstamp = NULL;
+	struct tse_buffer *rx_buff = priv->rx_ring;
+
+	/* if the current entry is not owned by hardware, process it */
+	if (!(rx_descs[desc_entry].desc_control
+	      & MSGDMA_PREF_DESC_CTL_OWNED_BY_HW) &&
+	      rx_descs[desc_entry].desc_control) {
+		pktlength = rx_descs[desc_entry].bytes_transferred;
+		pktstatus = rx_descs[desc_entry].desc_status;
+		rxstatus = pktstatus;
+		rxstatus = rxstatus << 16;
+		rxstatus |= (pktlength & 0xffff);
+
+		/* get the timestamp */
+		if (priv->hwts_rx_en) {
+			ns = timestamp_to_ns(&rx_descs[desc_entry]);
+			shhwtstamp = skb_hwtstamps(rx_buff[entry].skb);
+			memset(shhwtstamp, 0,
+			       sizeof(struct skb_shared_hwtstamps));
+			shhwtstamp->hwtstamp = ns_to_ktime(ns);
+		}
+
+		/* clear data */
+		rx_descs[desc_entry].desc_control = 0;
+		rx_descs[desc_entry].timestamp_96b[0] = 0;
+		rx_descs[desc_entry].timestamp_96b[1] = 0;
+		rx_descs[desc_entry].timestamp_96b[2] = 0;
+
+		if (netif_msg_rx_status(priv))
+			netdev_info(priv->dev, "%s: desc: %d buf: %d ts: %lld ns",
+				    __func__, desc_entry, entry, ns);
+	}
+	return rxstatus;
+}
diff --git a/drivers/net/ethernet/altera/altera_msgdma_prefetcher.h b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.h
new file mode 100644
index 000000000000..ccf9954504ee
--- /dev/null
+++ b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* MSGDMA Prefetcher driver for Altera ethernet devices
+ *
+ * Copyright (C) 2018 Intel Corporation. All rights reserved.
+ * Author(s):
+ *   Dalon Westergreen <dalon.westergreen@intel.com>
+ */
+
+#ifndef __ALTERA_PREF_MSGDMA_H__
+#define __ALTERA_PREF_MSGDMA_H__
+
+void msgdma_pref_reset(struct altera_tse_private *priv);
+void msgdma_pref_enable_txirq(struct altera_tse_private *priv);
+void msgdma_pref_enable_rxirq(struct altera_tse_private *priv);
+void msgdma_pref_disable_rxirq(struct altera_tse_private *priv);
+void msgdma_pref_disable_txirq(struct altera_tse_private *priv);
+void msgdma_pref_clear_rxirq(struct altera_tse_private *priv);
+void msgdma_pref_clear_txirq(struct altera_tse_private *priv);
+u32 msgdma_pref_tx_completions(struct altera_tse_private *priv);
+void msgdma_pref_add_rx_desc(struct altera_tse_private *priv,
+			     struct tse_buffer *buffer);
+int msgdma_pref_tx_buffer(struct altera_tse_private *priv,
+			  struct tse_buffer *buffer);
+u32 msgdma_pref_rx_status(struct altera_tse_private *priv);
+int msgdma_pref_initialize(struct altera_tse_private *priv);
+void msgdma_pref_uninitialize(struct altera_tse_private *priv);
+void msgdma_pref_start_rxdma(struct altera_tse_private *priv);
+void msgdma_pref_start_txdma(struct altera_tse_private *priv);
+
+#endif /*  __ALTERA_PREF_MSGDMA_H__ */
diff --git a/drivers/net/ethernet/altera/altera_msgdmahw_prefetcher.h b/drivers/net/ethernet/altera/altera_msgdmahw_prefetcher.h
new file mode 100644
index 000000000000..e0484a3dc66e
--- /dev/null
+++ b/drivers/net/ethernet/altera/altera_msgdmahw_prefetcher.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* MSGDMA Prefetcher driver for Altera ethernet devices
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ * Contributors:
+ *   Dalon Westergreen
+ *   Thomas Chou
+ *   Ian Abbott
+ *   Yuriy Kozlov
+ *   Tobias Klauser
+ *   Andriy Smolskyy
+ *   Roman Bulgakov
+ *   Dmytro Mytarchuk
+ *   Matthew Gerlach
+ */
+
+#ifndef __ALTERA_MSGDMAHW_PREFETCHER_H__
+#define __ALTERA_MSGDMAHW_PREFETCHER_H__
+
+/* mSGDMA prefetcher extended prefectcher descriptor format
+ */
+struct msgdma_pref_extended_desc {
+	/* data buffer source address low bits */
+	u32 read_addr_lo;
+	/* data buffer destination address low bits */
+	u32 write_addr_lo;
+	/* the number of bytes to transfer */
+	u32 len;
+	/* next descriptor low address */
+	u32 next_desc_lo;
+	/* number of bytes transferred */
+	u32 bytes_transferred;
+	u32 desc_status;
+	u32 reserved_18;
+	/* bit 31:24 write burst */
+	/* bit 23:16 read burst */
+	/* bit 15:0  sequence number */
+	u32 burst_seq_num;
+	/* bit 31:16 write stride */
+	/* bit 15:0  read stride */
+	u32 stride;
+	/* data buffer source address high bits */
+	u32 read_addr_hi;
+	/* data buffer destination address high bits */
+	u32 write_addr_hi;
+	/* next descriptor high address */
+	u32 next_desc_hi;
+	/* prefetcher mod now writes these reserved bits*/
+	/* Response bits [191:160] */
+	u32 timestamp_96b[3];
+	/* desc_control */
+	u32 desc_control;
+};
+
+/* mSGDMA Prefetcher Descriptor Status bits */
+#define MSGDMA_PREF_DESC_STAT_STOPPED_ON_EARLY		BIT(8)
+#define MSGDMA_PREF_DESC_STAT_MASK			0xFF
+
+/* mSGDMA Prefetcher Descriptor Control bits */
+/* bit 31 and bits 29-0 are the same as the normal dispatcher ctl flags */
+#define MSGDMA_PREF_DESC_CTL_OWNED_BY_HW		BIT(30)
+
+/* mSGDMA Prefetcher CSR */
+struct msgdma_prefetcher_csr {
+	u32 control;
+	u32 next_desc_lo;
+	u32 next_desc_hi;
+	u32 desc_poll_freq;
+	u32 status;
+};
+
+/* mSGDMA Prefetcher Control */
+#define MSGDMA_PREF_CTL_PARK				BIT(4)
+#define MSGDMA_PREF_CTL_GLOBAL_INTR			BIT(3)
+#define MSGDMA_PREF_CTL_RESET				BIT(2)
+#define MSGDMA_PREF_CTL_DESC_POLL_EN			BIT(1)
+#define MSGDMA_PREF_CTL_RUN				BIT(0)
+
+#define MSGDMA_PREF_POLL_FREQ_MASK			0xFFFF
+
+/* mSGDMA Prefetcher Status */
+#define MSGDMA_PREF_STAT_IRQ				BIT(0)
+
+#define msgdma_pref_csroffs(a) (offsetof(struct msgdma_prefetcher_csr, a))
+#define msgdma_pref_descroffs(a) (offsetof(struct msgdma_pref_extended_desc, a))
+
+#endif /* __ALTERA_MSGDMAHW_PREFETCHER_H__*/
diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h
index 508d5d015ca6..e8f9c47385e8 100644
--- a/drivers/net/ethernet/altera/altera_tse.h
+++ b/drivers/net/ethernet/altera/altera_tse.h
@@ -393,6 +393,7 @@ struct altera_tse_private;
 
 #define ALTERA_DTYPE_SGDMA 1
 #define ALTERA_DTYPE_MSGDMA 2
+#define ALTERA_DTYPE_MSGDMA_PREF 3
 
 /* standard DMA interface for SGDMA and MSGDMA */
 struct altera_dmaops {
@@ -445,6 +446,19 @@ struct altera_tse_private {
 	void __iomem *tx_dma_csr;
 	void __iomem *tx_dma_desc;
 
+	/* mSGDMA Rx Prefecher address space */
+	void __iomem *rx_pref_csr;
+	struct msgdma_pref_extended_desc *pref_rxdesc;
+	dma_addr_t pref_rxdescphys;
+	u32 pref_rx_prod;
+
+	/* mSGDMA Tx Prefecher address space */
+	void __iomem *tx_pref_csr;
+	struct msgdma_pref_extended_desc *pref_txdesc;
+	dma_addr_t pref_txdescphys;
+	u32 rx_poll_freq;
+	u32 tx_poll_freq;
+
 	/* Rx buffers queue */
 	struct tse_buffer *rx_ring;
 	u32 rx_cons;
diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c
index 3b0c940189be..05d4c48b875c 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -55,6 +55,7 @@
 #include "altera_tse.h"
 #include "altera_sgdma.h"
 #include "altera_msgdma.h"
+#include "altera_msgdma_prefetcher.h"
 #include "altera_ptp.h"
 
 static atomic_t instance_count = ATOMIC_INIT(~0);
@@ -1551,6 +1552,34 @@ static int altera_tse_probe(struct platform_device *pdev)
 		priv->rxdescmem = resource_size(dma_res);
 		priv->rxdescmem_busaddr = dma_res->start;
 
+	} else if (priv->dmaops &&
+			   priv->dmaops->altera_dtype ==
+			   ALTERA_DTYPE_MSGDMA_PREF) {
+		/* mSGDMA Rx Prefetcher address space */
+		ret = request_and_map(pdev, "rx_pref", &dma_res,
+				      &priv->rx_pref_csr);
+		if (ret)
+			goto err_free_netdev;
+
+		/* mSGDMA Tx Prefetcher address space */
+		ret = request_and_map(pdev, "tx_pref", &dma_res,
+				      &priv->tx_pref_csr);
+		if (ret)
+			goto err_free_netdev;
+
+		/* get prefetcher rx poll frequency from device tree */
+		if (of_property_read_u32(pdev->dev.of_node, "rx-poll-freq",
+					 &priv->rx_poll_freq)) {
+			dev_info(&pdev->dev, "Defaulting RX Poll Frequency to 128\n");
+			priv->rx_poll_freq = 128;
+		}
+
+		/* get prefetcher rx poll frequency from device tree */
+		if (of_property_read_u32(pdev->dev.of_node, "tx-poll-freq",
+					 &priv->tx_poll_freq)) {
+			dev_info(&pdev->dev, "Defaulting TX Poll Frequency to 128\n");
+			priv->tx_poll_freq = 128;
+		}
 	} else {
 		goto err_free_netdev;
 	}
@@ -1816,7 +1845,29 @@ static const struct altera_dmaops altera_dtype_msgdma = {
 	.start_txdma = NULL,
 };
 
+static const struct altera_dmaops altera_dtype_prefetcher = {
+	.altera_dtype = ALTERA_DTYPE_MSGDMA_PREF,
+	.dmamask = 64,
+	.reset_dma = msgdma_pref_reset,
+	.enable_txirq = msgdma_pref_enable_txirq,
+	.enable_rxirq = msgdma_pref_enable_rxirq,
+	.disable_txirq = msgdma_pref_disable_txirq,
+	.disable_rxirq = msgdma_pref_disable_rxirq,
+	.clear_txirq = msgdma_pref_clear_txirq,
+	.clear_rxirq = msgdma_pref_clear_rxirq,
+	.tx_buffer = msgdma_pref_tx_buffer,
+	.tx_completions = msgdma_pref_tx_completions,
+	.add_rx_desc = msgdma_pref_add_rx_desc,
+	.get_rx_status = msgdma_pref_rx_status,
+	.init_dma = msgdma_pref_initialize,
+	.uninit_dma = msgdma_pref_uninitialize,
+	.start_rxdma = msgdma_pref_start_rxdma,
+	.start_txdma = msgdma_pref_start_txdma,
+};
+
 static const struct of_device_id altera_tse_ids[] = {
+	{ .compatible = "altr,tse-msgdma-2.0",
+		.data = &altera_dtype_prefetcher, },
 	{ .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
 	{ .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
 	{ .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
-- 
2.19.1

[PATCH net-next 8/8] net: eth: altera: tse: update devicetree bindings documentation

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Update devicetree bindings documentation to include msgdma
prefetcher and ptp bindings.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 .../devicetree/bindings/net/altera_tse.txt    | 98 +++++++++++++++----
 1 file changed, 79 insertions(+), 19 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/altera_tse.txt b/Documentation/devicetree/bindings/net/altera_tse.txt
index 0e21df94a53f..d35806942a8f 100644
--- a/Documentation/devicetree/bindings/net/altera_tse.txt
+++ b/Documentation/devicetree/bindings/net/altera_tse.txt
@@ -2,50 +2,79 @@
 
 Required properties:
 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
-		be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
+		be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE,
+		and "altr,tse-msgdma-2.0" for MSGDMA with prefetcher based
+		implementations.
 		ALTR is supported for legacy device trees, but is deprecated.
 		altr should be used for all new designs.
 - reg: Address and length of the register set for the device. It contains
   the information of registers in the same order as described by reg-names
 - reg-names: Should contain the reg names
-  "control_port": MAC configuration space region
-  "tx_csr":       xDMA Tx dispatcher control and status space region
-  "tx_desc":      MSGDMA Tx dispatcher descriptor space region
-  "rx_csr" :      xDMA Rx dispatcher control and status space region
-  "rx_desc":      MSGDMA Rx dispatcher descriptor space region
-  "rx_resp":      MSGDMA Rx dispatcher response space region
-  "s1":		  SGDMA descriptor memory
 - interrupts: Should contain the TSE interrupts and it's mode.
 - interrupt-names: Should contain the interrupt names
-  "rx_irq":       xDMA Rx dispatcher interrupt
-  "tx_irq":       xDMA Tx dispatcher interrupt
+  "rx_irq":       DMA Rx dispatcher interrupt
+  "tx_irq":       DMA Tx dispatcher interrupt
 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
 - phy-mode: See ethernet.txt in the same directory.
 - phy-handle: See ethernet.txt in the same directory.
 - phy-addr: See ethernet.txt in the same directory. A configuration should
 		include phy-handle or phy-addr.
-- altr,has-supplementary-unicast:
-		If present, TSE supports additional unicast addresses.
-		Otherwise additional unicast addresses are not supported.
-- altr,has-hash-multicast-filter:
-		If present, TSE supports a hash based multicast filter.
-		Otherwise, hash-based multicast filtering is not supported.
-
 - mdio device tree subnode: When the TSE has a phy connected to its local
 		mdio, there must be device tree subnode with the following
 		required properties:
-
 	- compatible: Must be "altr,tse-mdio".
 	- #address-cells: Must be <1>.
 	- #size-cells: Must be <0>.
 
 	For each phy on the mdio bus, there must be a node with the following
 	fields:
-
 	- reg: phy id used to communicate to phy.
 	- device_type: Must be "ethernet-phy".
 
+- altr,has-supplementary-unicast:
+		If present, TSE supports additional unicast addresses.
+		Otherwise additional unicast addresses are not supported.
+- altr,has-hash-multicast-filter:
+		If present, TSE supports a hash based multicast filter.
+		Otherwise, hash-based multicast filtering is not supported.
+- altr,has-ptp:
+		If present, TSE supports 1588 timestamping.  Currently only
+		supported with the msgdma prefetcher.
+- altr,tx-poll-cnt:
+		Optional cycle count for Tx prefetcher to poll descriptor
+		list.  If not present, defaults to 128, which at 125MHz is
+		roughly 1usec. Only for "altr,tse-msgdma-2.0".
+- altr,rx-poll-cnt:
+		Optional cycle count for Tx prefetcher to poll descriptor
+		list.  If not present, defaults to 128, which at 125MHz is
+		roughly 1usec. Only for "altr,tse-msgdma-2.0".
+
+Required registers by compatibility string:
+ - "altr,tse-1.0"
+	"control_port": MAC configuration space region
+	"tx_csr":       DMA Tx dispatcher control and status space region
+	"rx_csr" :      DMA Rx dispatcher control and status space region
+	"s1":		DMA descriptor memory
+
+ - "altr,tse-msgdma-1.0"
+	"control_port": MAC configuration space region
+	"tx_csr":       DMA Tx dispatcher control and status space region
+	"tx_desc":      DMA Tx dispatcher descriptor space region
+	"rx_csr" :      DMA Rx dispatcher control and status space region
+	"rx_desc":      DMA Rx dispatcher descriptor space region
+	"rx_resp":      DMA Rx dispatcher response space region
+
+ - "altr,tse-msgdma-2.0"
+	"control_port": MAC configuration space region
+	"tx_csr":       DMA Tx dispatcher control and status space region
+	"tx_pref":      DMA Tx prefetcher configuration space region
+	"rx_csr" :      DMA Rx dispatcher control and status space region
+	"rx_pref":      DMA Rx prefetcher configuration space region
+	"tod_ctrl":     Time of Day Control register only required when
+			timestamping support is enabled.  Timestamping is
+			only supported with the msgdma-2.0 implementation.
+
 Optional properties:
 - local-mac-address: See ethernet.txt in the same directory.
 - max-frame-size: See ethernet.txt in the same directory.
@@ -87,6 +116,11 @@ Example:
 				device_type = "ethernet-phy";
 			};
 
+			phy2: ethernet-phy@2 {
+				reg = <0x2>;
+				device_type = "ethernet-phy";
+			};
+
 		};
 	};
 
@@ -112,3 +146,29 @@ Example:
 		altr,has-hash-multicast-filter;
 		phy-handle = <&phy1>;
 	};
+
+	tse_sub_2_eth_tse_0: ethernet@1,00002000 {
+		compatible = "altr,tse-msgdma-2.0";
+		reg = 	<0x00000001 0x00002000 0x00000400>,
+			<0x00000001 0x00002400 0x00000020>,
+			<0x00000001 0x00002420 0x00000020>,
+			<0x00000001 0x00002440 0x00000020>,
+			<0x00000001 0x00002460 0x00000020>,
+			<0x00000001 0x00002480 0x00000040>;
+		reg-names = "control_port", "rx_csr", "rx_pref","tx_csr", "tx_pref", "tod_ctrl";
+		interrupt-parent = <&hps_0_arm_gic_0>;
+		interrupts = <0 45 4>, <0 44 4>;
+		interrupt-names = "rx_irq", "tx_irq";
+		rx-fifo-depth = <2048>;
+		tx-fifo-depth = <2048>;
+		address-bits = <48>;
+		max-frame-size = <1500>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		phy-mode = "sgmii";
+		altr,has-supplementary-unicast;
+		altr,has-hash-multicast-filter;
+		altr,has-ptp;
+		altr,tx-poll-cnt = <128>;
+		altr,rx-poll-cnt = <32>;
+		phy-handle = <&phy2>;
+	};
-- 
2.19.1

Re: [PATCH net-next 6/8] net: eth: altera: tse: add support for ptp and timestamping

[Richard Cochran]

On Wed, Nov 14, 2018 at 04:50:45PM -0800, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Add support for the ptp clock used with the tse, and update
> the driver to support timestamping when enabled.  We also
> enable debugfs entries for the ptp clock to allow some user
> control and interaction with the ptp clock.
> 
> Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> ---
>  drivers/net/ethernet/altera/Kconfig           |   1 +
>  drivers/net/ethernet/altera/Makefile          |   3 +-
>  drivers/net/ethernet/altera/altera_ptp.c      | 473 ++++++++++++++++++
>  drivers/net/ethernet/altera/altera_ptp.h      |  77 +++

Wouldn't it be nice if the PTP maintainer were included on CC for new
PTP drivers?  One can always wish...

> diff --git a/drivers/net/ethernet/altera/Kconfig b/drivers/net/ethernet/altera/Kconfig
> index fdddba51473e..36aee0fc0b51 100644
> --- a/drivers/net/ethernet/altera/Kconfig
> +++ b/drivers/net/ethernet/altera/Kconfig
> @@ -2,6 +2,7 @@ config ALTERA_TSE
>  	tristate "Altera Triple-Speed Ethernet MAC support"
>  	depends on HAS_DMA
>  	select PHYLIB
> +	select PTP_1588_CLOCK

We now use "imply" instead of "select".

> +/* A fine ToD HW clock offset adjustment.
> + * To perform the fine offset adjustment the AdjustPeriod register is used
> + * to replace the Period register for AdjustCount clock cycles in hardware.
> + */
> +static int fine_adjust_tod_clock(struct altera_ptp_private *priv,
> +				 u32 adjust_period, u32 adjust_count)

The function naming is really poor throughout this driver.  You should
use a unique prefix that relates to your driver or HW.

> +static int adjust_fine(struct ptp_clock_info *ptp, long scaled_ppm)
> +{

This is named like a global function.  Needs prefix.

> +	struct altera_ptp_private *priv =
> +		container_of(ptp, struct altera_ptp_private, ptp_clock_ops);
> +	unsigned long flags;
> +	int ret = 0;
> +	u64 ppb;
> +	u32 tod_period;
> +	u32 tod_rem;
> +	u32 tod_drift_adjust_fns;
> +	u32 tod_drift_adjust_rate;
> +	unsigned long rate;

Please put all like types together on one line, and use reverse
Christmas tree style.

> +
> +	priv->scaled_ppm = scaled_ppm;
> +
> +	/* only unlock if it is currently locked */
> +	if (mutex_is_locked(&priv->ppm_mutex))
> +		mutex_unlock(&priv->ppm_mutex);
> +
> +	if (!priv->ptp_correct_freq)
> +		goto out;
> +
> +	rate = clk_get_rate(priv->tod_clk);
> +
> +	/* From scaled_ppm_to_ppb */
> +	ppb = 1 + scaled_ppm;
> +	ppb *= 125;
> +	ppb >>= 13;
> +
> +	ppb += NOMINAL_PPB;
> +
> +	tod_period = div_u64_rem(ppb << 16, rate, &tod_rem);
> +	if (tod_period > TOD_PERIOD_MAX) {
> +		ret = -ERANGE;
> +		goto out;
> +	}
> +
> +	/* The drift of ToD adjusted periodically by adding a drift_adjust_fns
> +	 * correction value every drift_adjust_rate count of clock cycles.
> +	 */
> +	tod_drift_adjust_fns = tod_rem / gcd(tod_rem, rate);
> +	tod_drift_adjust_rate = rate / gcd(tod_rem, rate);
> +
> +	while ((tod_drift_adjust_fns > TOD_DRIFT_ADJUST_FNS_MAX) |
> +		(tod_drift_adjust_rate > TOD_DRIFT_ADJUST_RATE_MAX)) {
> +		tod_drift_adjust_fns = tod_drift_adjust_fns >> 1;
> +		tod_drift_adjust_rate = tod_drift_adjust_rate >> 1;
> +	}
> +
> +	if (tod_drift_adjust_fns == 0)
> +		tod_drift_adjust_rate = 0;
> +
> +	spin_lock_irqsave(&priv->tod_lock, flags);
> +	csrwr32(tod_period, priv->tod_ctrl, tod_csroffs(period));
> +	csrwr32(0, priv->tod_ctrl, tod_csroffs(adjust_period));
> +	csrwr32(0, priv->tod_ctrl, tod_csroffs(adjust_count));
> +	csrwr32(tod_drift_adjust_fns, priv->tod_ctrl,
> +		tod_csroffs(drift_adjust));
> +	csrwr32(tod_drift_adjust_rate, priv->tod_ctrl,
> +		tod_csroffs(drift_adjust_rate));
> +	spin_unlock_irqrestore(&priv->tod_lock, flags);
> +
> +out:
> +	return ret;
> +}
> +
> +static int adjust_time(struct ptp_clock_info *ptp, s64 delta)
> +{
> +	struct altera_ptp_private *priv =
> +		container_of(ptp, struct altera_ptp_private, ptp_clock_ops);
> +	int ret = 0;
> +	u64 abs_delta;
> +	unsigned long flags;
> +	u32 period;
> +	u32 diff;
> +	u64 count;
> +	u32 rem;

Same here.

> +	if (!priv->ptp_correct_offs)
> +		goto out;
> +
> +	if (delta < 0)
> +		abs_delta = -delta;
> +	else
> +		abs_delta = delta;
> +
> +	spin_lock_irqsave(&priv->tod_lock, flags);
> +
> +	/* Get the maximum possible value of the Period register offset
> +	 * adjustment in nanoseconds scale. This depends on the current
> +	 * Period register settings and the maximum and minimum possible
> +	 * values of the Period register.
> +	 */
> +	period = csrrd32(priv->tod_ctrl, tod_csroffs(period));
> +
> +	if (delta < 0)
> +		diff = (period - TOD_PERIOD_MIN) >> 16;
> +	else
> +		diff = (TOD_PERIOD_MAX - period) >> 16;
> +
> +	/* Find out the least number of cycles needed for the Period register
> +	 * adjustment by delta nanoseconds.
> +	 */
> +	while (diff) {

Ugh.  How many 64 divisions are you going to do?  Is there no better
way?

> +		count = div_u64_rem(abs_delta, diff, &rem);
> +		if (rem == 0)
> +			break;
> +		diff--;
> +	}
> +
> +	if (diff && count && count < TOD_ADJUST_COUNT_MAX) {
> +		/* Perform the fine time offset adjustment */
> +		if (delta < 0)
> +			period -= (diff << 16);
> +		else
> +			period += (diff << 16);
> +
> +		ret = fine_adjust_tod_clock(priv, period, count);
> +
> +	} else {
> +		/* Perform the coarse time offset adjustment */
> +		ret = coarse_adjust_tod_clock(priv, delta);
> +	}
> +
> +	spin_unlock_irqrestore(&priv->tod_lock, flags);
> +
> +out:
> +	return ret;
> +}
> +
> +static int get_time(struct ptp_clock_info *ptp, struct timespec64 *ts)
> +{
> +	struct altera_ptp_private *priv =
> +		container_of(ptp, struct altera_ptp_private, ptp_clock_ops);
> +	unsigned long flags;
> +	u64 seconds;
> +	u32 seconds_msb;
> +	u32 seconds_lsb;
> +	u32 nanosec;
> +
> +	spin_lock_irqsave(&priv->tod_lock, flags);
> +	nanosec = csrrd32(priv->tod_ctrl, tod_csroffs(nanosec));
> +	seconds_lsb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_lsb));
> +	seconds_msb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_msb));
> +	spin_unlock_irqrestore(&priv->tod_lock, flags);
> +
> +	seconds = (((u64)(seconds_msb & 0x0000ffff)) << 32) | seconds_lsb;
> +
> +	ts->tv_nsec = nanosec;
> +	ts->tv_sec = (__kernel_time_t)seconds;
> +
> +	return 0;
> +}
> +
> +static int set_time(struct ptp_clock_info *ptp, const struct timespec64 *ts)
> +{
> +	struct altera_ptp_private *priv =
> +		container_of(ptp, struct altera_ptp_private, ptp_clock_ops);
> +	unsigned long flags;
> +	u32 seconds_msb = upper_32_bits(ts->tv_sec) & 0x0000ffff;
> +	u32 seconds_lsb = lower_32_bits(ts->tv_sec);
> +	u32 nanosec = lower_32_bits(ts->tv_nsec);
> +
> +	spin_lock_irqsave(&priv->tod_lock, flags);
> +	csrwr32(seconds_msb, priv->tod_ctrl, tod_csroffs(seconds_msb));
> +	csrwr32(seconds_lsb, priv->tod_ctrl, tod_csroffs(seconds_lsb));
> +	csrwr32(nanosec, priv->tod_ctrl, tod_csroffs(nanosec));
> +	spin_unlock_irqrestore(&priv->tod_lock, flags);
> +
> +	return 0;
> +}
> +
> +static int enable_feature(struct ptp_clock_info *ptp,
> +			  struct ptp_clock_request *request, int on)
> +{
> +	return -EOPNOTSUPP;
> +}
> +
> +static struct ptp_clock_info altera_ptp_clock_ops = {
> +	.owner = THIS_MODULE,
> +	.name = "altera_ptp",
> +	.max_adj = 500000000,
> +	.n_alarm = 0,
> +	.n_ext_ts = 0,
> +	.n_per_out = 0,
> +	.pps = 0,
> +	.adjfine = adjust_fine,
> +	.adjtime = adjust_time,
> +	.gettime64 = get_time,
> +	.settime64 = set_time,
> +	.enable = enable_feature,

Use driver-specific naming, please.

> +};
> +
> +/* ptp debugfs */
> +static ssize_t ptp_tod_read(struct file *filp, char __user *buffer,
> +			    size_t count, loff_t *ppos)
> +{

Please drop this debugfs stuff.  We can read the clock with clock_gettime().

> +	struct altera_ptp_private *priv = filp->private_data;
> +	unsigned long flags;
> +	u32 seconds_msb;
> +	u32 seconds_lsb;
> +	u32 nanosec;
> +
> +	if (*ppos != 0)
> +		return 0;
> +
> +	if (count < (sizeof(u32) * 3))
> +		return -ENOSPC;
> +
> +	spin_lock_irqsave(&priv->tod_lock, flags);
> +	nanosec = csrrd32(priv->tod_ctrl, tod_csroffs(nanosec));
> +	seconds_lsb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_lsb));
> +	seconds_msb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_msb));
> +	spin_unlock_irqrestore(&priv->tod_lock, flags);
> +
> +	if (copy_to_user(buffer, &seconds_msb, sizeof(u32)))
> +		return -EFAULT;
> +	buffer += sizeof(u32);
> +
> +	if (copy_to_user(buffer, &seconds_lsb, sizeof(u32)))
> +		return -EFAULT;
> +	buffer += sizeof(u32);
> +
> +	if (copy_to_user(buffer, &nanosec, sizeof(u32)))
> +		return -EFAULT;
> +
> +	return (sizeof(u32) * 3);
> +}
> +
> +static const struct file_operations ptp_dbg_tod_ops = {
> +	.owner = THIS_MODULE,
> +	.open = simple_open,
> +	.read = ptp_tod_read,
> +	.write = NULL,
> +};
> +
> +static ssize_t ptp_ppm_read(struct file *filp, char __user *buffer,
> +			    size_t count, loff_t *ppos)
> +{
> +	struct altera_ptp_private *priv = filp->private_data;
> +
> +	if (*ppos != 0)
> +		return 0;
> +
> +	if (count < sizeof(long))
> +		return -ENOSPC;
> +
> +	if (mutex_lock_interruptible(&priv->ppm_mutex))
> +		return -EAGAIN;
> +
> +	if (copy_to_user(buffer, &priv->scaled_ppm, sizeof(long)))
> +		return -EFAULT;
> +
> +	return sizeof(long);
> +}
> +
> +static const struct file_operations ptp_dbg_ppm_ops = {
> +	.owner = THIS_MODULE,
> +	.open = simple_open,
> +	.read = ptp_ppm_read,
> +	.write = NULL,
> +};
> +
> +int altera_ptp_dbg_init(struct altera_ptp_private *priv,
> +			struct dentry *dfs_dir_root)
> +{
> +	struct dentry *dfs_dir;
> +
> +	dfs_dir = debugfs_create_dir("ptp", dfs_dir_root);
> +
> +	/* Use u32 instead of bool */
> +	if (!debugfs_create_u32("correct_offset", 0600, dfs_dir,
> +				&priv->ptp_correct_offs))
> +		return -ENOMEM;
> +
> +	/* Use u32 instead of bool */
> +	if (!debugfs_create_u32("correct_frequency", 0600, dfs_dir,
> +				&priv->ptp_correct_freq))
> +		return -ENOMEM;
> +
> +	if (!debugfs_create_file("tod", 0400, dfs_dir,
> +				 (void *)priv, &ptp_dbg_tod_ops))
> +		return -ENOMEM;
> +
> +	if (!debugfs_create_file("scaled_ppm", 0400, dfs_dir,
> +				 (void *)priv, &ptp_dbg_ppm_ops))
> +		return -ENOMEM;
> +
> +	return 0;
> +}
> +
> +/* Initialize PTP control block registers */
> +int altera_init_ptp(struct altera_ptp_private *priv)
> +{

So here we have a prefix, but "altera" is a poor choice.  That is (or
was) a company name, not the name of a specific device.  Imagine if a
MAC driver used "intel_init_mac()"!

Maybe "altera_tse_" ?

Thanks,
Richard

Re: [PATCH net-next 1/8] net: eth: altera: tse_start_xmit ignores tx_buffer call response

[Thor Thayer]

On 11/14/18 6:50 PM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> The return from tx_buffer call in tse_start_xmit is
> inapropriately ignored.  tse_buffer calls should return
> 0 for success or NETDEV_TX_BUSY.  tse_start_xmit should
> return not report a successful transmit when the tse_buffer
> call returns an error condition.
> 
> In addition to the above, the msgdma and sgdma do not return
> the same value on success or failure.  The sgdma_tx_buffer
> returned 0 on failure and a positive number of transmitted
> packets on success.  Given that it only ever sends 1 packet,
> this made no sense.  The msgdma implementation msgdma_tx_buffer
> returns 0 on success.
> 
>    -> Don't ignore the return from tse_buffer calls
>    -> Fix sgdma tse_buffer call to return 0 on success
>       and NETDEV_TX_BUSY on failure.
> 
> Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> ---
>   drivers/net/ethernet/altera/altera_sgdma.c    | 14 ++++++++------
>   drivers/net/ethernet/altera/altera_tse_main.c |  4 +++-
>   2 files changed, 11 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/net/ethernet/altera/altera_sgdma.c b/drivers/net/ethernet/altera/altera_sgdma.c
> index 88ef67a998b4..eb47b9b820bb 100644
> --- a/drivers/net/ethernet/altera/altera_sgdma.c
> +++ b/drivers/net/ethernet/altera/altera_sgdma.c
> @@ -15,6 +15,7 @@
>    */
>   
>   #include <linux/list.h>
> +#include <linux/netdevice.h>
>   #include "altera_utils.h"
>   #include "altera_tse.h"
>   #include "altera_sgdmahw.h"
> @@ -170,10 +171,11 @@ void sgdma_clear_txirq(struct altera_tse_private *priv)
>   		    SGDMA_CTRLREG_CLRINT);
>   }
>   
> -/* transmits buffer through SGDMA. Returns number of buffers
> - * transmitted, 0 if not possible.
> - *
> - * tx_lock is held by the caller
> +/* transmits buffer through SGDMA.
> + *   original behavior returned the number of transmitted packets (always 1) &
> + *   returned 0 on error.  This differs from the msgdma.  the calling function
> + *   will now actually look at the code, so from now, 0 is good and return
> + *   NETDEV_TX_BUSY when busy.
>    */
>   int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
>   {
> @@ -185,7 +187,7 @@ int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
>   
>   	/* wait 'til the tx sgdma is ready for the next transmit request */
>   	if (sgdma_txbusy(priv))
> -		return 0;
> +		return NETDEV_TX_BUSY;
>   
>   	sgdma_setup_descrip(cdesc,			/* current descriptor */
>   			    ndesc,			/* next descriptor */
> @@ -202,7 +204,7 @@ int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
>   	/* enqueue the request to the pending transmit queue */
>   	queue_tx(priv, buffer);
>   
> -	return 1;
> +	return 0;
>   }
>   
>   
> diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c
> index baca8f704a45..dcb330129e23 100644
> --- a/drivers/net/ethernet/altera/altera_tse_main.c
> +++ b/drivers/net/ethernet/altera/altera_tse_main.c
> @@ -606,7 +606,9 @@ static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
>   	buffer->dma_addr = dma_addr;
>   	buffer->len = nopaged_len;
>   
> -	priv->dmaops->tx_buffer(priv, buffer);
> +	ret = priv->dmaops->tx_buffer(priv, buffer);
> +	if (ret)
> +		goto out;
>   
>   	skb_tx_timestamp(skb);
>   
> 
Acked-by: Thor Thayer <thor.thayer@linux.intel.com>

Re: [PATCH net-next 2/8] net: eth: altera: set rx and tx ring size before init_dma call

[Thor Thayer]

On 11/14/18 6:50 PM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> It is more appropriate to set the rx and tx ring size before calling
> the init function for the dma.
> 
> Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> ---
>   drivers/net/ethernet/altera/altera_tse_main.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c
> index dcb330129e23..0c0e8f9bba9b 100644
> --- a/drivers/net/ethernet/altera/altera_tse_main.c
> +++ b/drivers/net/ethernet/altera/altera_tse_main.c
> @@ -1166,6 +1166,10 @@ static int tse_open(struct net_device *dev)
>   	int i;
>   	unsigned long int flags;
>   
> +	/* set tx and rx ring size */
> +	priv->rx_ring_size = dma_rx_num;
> +	priv->tx_ring_size = dma_tx_num;
> +
>   	/* Reset and configure TSE MAC and probe associated PHY */
>   	ret = priv->dmaops->init_dma(priv);
>   	if (ret != 0) {
> @@ -1208,8 +1212,6 @@ static int tse_open(struct net_device *dev)
>   	priv->dmaops->reset_dma(priv);
>   
>   	/* Create and initialize the TX/RX descriptors chains. */
> -	priv->rx_ring_size = dma_rx_num;
> -	priv->tx_ring_size = dma_tx_num;
>   	ret = alloc_init_skbufs(priv);
>   	if (ret) {
>   		netdev_err(dev, "DMA descriptors initialization failed\n");
> 
Acked-by: Thor Thayer <thor.thayer@linux.intel.com>

Re: [PATCH net-next 3/8] net: eth: altera: tse: fix altera_dmaops declaration

[Thor Thayer]

On 11/14/18 6:50 PM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> The declaration of struct altera_dmaops does not have
> identifier names.  Add identifier names to confrom with
> required coding styles.
> 
> Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> ---
>   drivers/net/ethernet/altera/altera_tse.h | 30 +++++++++++++-----------
>   1 file changed, 16 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h
> index e2feee87180a..d5b97e02e6d6 100644
> --- a/drivers/net/ethernet/altera/altera_tse.h
> +++ b/drivers/net/ethernet/altera/altera_tse.h
> @@ -396,20 +396,22 @@ struct altera_tse_private;
>   struct altera_dmaops {
>   	int altera_dtype;
>   	int dmamask;
> -	void (*reset_dma)(struct altera_tse_private *);
> -	void (*enable_txirq)(struct altera_tse_private *);
> -	void (*enable_rxirq)(struct altera_tse_private *);
> -	void (*disable_txirq)(struct altera_tse_private *);
> -	void (*disable_rxirq)(struct altera_tse_private *);
> -	void (*clear_txirq)(struct altera_tse_private *);
> -	void (*clear_rxirq)(struct altera_tse_private *);
> -	int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *);
> -	u32 (*tx_completions)(struct altera_tse_private *);
> -	void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *);
> -	u32 (*get_rx_status)(struct altera_tse_private *);
> -	int (*init_dma)(struct altera_tse_private *);
> -	void (*uninit_dma)(struct altera_tse_private *);
> -	void (*start_rxdma)(struct altera_tse_private *);
> +	void (*reset_dma)(struct altera_tse_private *priv);
> +	void (*enable_txirq)(struct altera_tse_private *priv);
> +	void (*enable_rxirq)(struct altera_tse_private *priv);
> +	void (*disable_txirq)(struct altera_tse_private *priv);
> +	void (*disable_rxirq)(struct altera_tse_private *priv);
> +	void (*clear_txirq)(struct altera_tse_private *priv);
> +	void (*clear_rxirq)(struct altera_tse_private *priv);
> +	int (*tx_buffer)(struct altera_tse_private *priv,
> +			 struct tse_buffer *buffer);
> +	u32 (*tx_completions)(struct altera_tse_private *priv);
> +	void (*add_rx_desc)(struct altera_tse_private *priv,
> +			    struct tse_buffer *buffer);
> +	u32 (*get_rx_status)(struct altera_tse_private *priv);
> +	int (*init_dma)(struct altera_tse_private *priv);
> +	void (*uninit_dma)(struct altera_tse_private *priv);
> +	void (*start_rxdma)(struct altera_tse_private *priv);
>   };
>   
>   /* This structure is private to each device.
> 
Acked-by: Thor Thayer <thor.thayer@linux.intel.com>

Re: [PATCH net-next 4/8] net: eth: altera: tse: add optional function to start tx dma

[Thor Thayer]

On 11/14/18 6:50 PM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Allow for optional start up of tx dma if the start_txdma
> function is defined in altera_dmaops.
> 
> Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> ---
>   drivers/net/ethernet/altera/altera_tse.h      | 1 +
>   drivers/net/ethernet/altera/altera_tse_main.c | 5 +++++
>   2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h
> index d5b97e02e6d6..7f246040135d 100644
> --- a/drivers/net/ethernet/altera/altera_tse.h
> +++ b/drivers/net/ethernet/altera/altera_tse.h
> @@ -412,6 +412,7 @@ struct altera_dmaops {
>   	int (*init_dma)(struct altera_tse_private *priv);
>   	void (*uninit_dma)(struct altera_tse_private *priv);
>   	void (*start_rxdma)(struct altera_tse_private *priv);
> +	void (*start_txdma)(struct altera_tse_private *priv);
>   };
>   
>   /* This structure is private to each device.
> diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c
> index 0c0e8f9bba9b..f6b6a14b1ce9 100644
> --- a/drivers/net/ethernet/altera/altera_tse_main.c
> +++ b/drivers/net/ethernet/altera/altera_tse_main.c
> @@ -1256,6 +1256,9 @@ static int tse_open(struct net_device *dev)
>   
>   	priv->dmaops->start_rxdma(priv);
>   
> +	if (priv->dmaops->start_txdma)
> +		priv->dmaops->start_txdma(priv);
> +
>   	/* Start MAC Rx/Tx */
>   	spin_lock(&priv->mac_cfg_lock);
>   	tse_set_mac(priv, true);
> @@ -1658,6 +1661,7 @@ static const struct altera_dmaops altera_dtype_sgdma = {
>   	.init_dma = sgdma_initialize,
>   	.uninit_dma = sgdma_uninitialize,
>   	.start_rxdma = sgdma_start_rxdma,
> +	.start_txdma = NULL,
>   };
>   
>   static const struct altera_dmaops altera_dtype_msgdma = {
> @@ -1677,6 +1681,7 @@ static const struct altera_dmaops altera_dtype_msgdma = {
>   	.init_dma = msgdma_initialize,
>   	.uninit_dma = msgdma_uninitialize,
>   	.start_rxdma = msgdma_start_rxdma,
> +	.start_txdma = NULL,
>   };
>   
>   static const struct of_device_id altera_tse_ids[] = {
> 
Acked-by: Thor Thayer <thor.thayer@linux.intel.com>

Re: [PATCH net-next 5/8] net: eth: altera: tse: Move common functions to altera_utils

[Thor Thayer]

On 11/14/18 6:50 PM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Move request_and_map and other shared functions to altera_utils. This
> is the first step to moving common code out of tse specific code so
> that it can be shared with future altera ethernet ip.
> 
> Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> ---
>   drivers/net/ethernet/altera/altera_tse.h      | 45 ------------------
>   .../net/ethernet/altera/altera_tse_ethtool.c  |  1 +
>   drivers/net/ethernet/altera/altera_tse_main.c | 32 +------------
>   drivers/net/ethernet/altera/altera_utils.c    | 30 ++++++++++++
>   drivers/net/ethernet/altera/altera_utils.h    | 46 +++++++++++++++++++
>   5 files changed, 78 insertions(+), 76 deletions(-)
> 
> diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h
> index 7f246040135d..f435fb0eca90 100644
> --- a/drivers/net/ethernet/altera/altera_tse.h
> +++ b/drivers/net/ethernet/altera/altera_tse.h
> @@ -500,49 +500,4 @@ struct altera_tse_private {
>    */
>   void altera_tse_set_ethtool_ops(struct net_device *);
>   
> -static inline
> -u32 csrrd32(void __iomem *mac, size_t offs)
> -{
> -	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> -	return readl(paddr);
> -}
> -
> -static inline
> -u16 csrrd16(void __iomem *mac, size_t offs)
> -{
> -	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> -	return readw(paddr);
> -}
> -
> -static inline
> -u8 csrrd8(void __iomem *mac, size_t offs)
> -{
> -	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> -	return readb(paddr);
> -}
> -
> -static inline
> -void csrwr32(u32 val, void __iomem *mac, size_t offs)
> -{
> -	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> -
> -	writel(val, paddr);
> -}
> -
> -static inline
> -void csrwr16(u16 val, void __iomem *mac, size_t offs)
> -{
> -	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> -
> -	writew(val, paddr);
> -}
> -
> -static inline
> -void csrwr8(u8 val, void __iomem *mac, size_t offs)
> -{
> -	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> -
> -	writeb(val, paddr);
> -}
> -
>   #endif /* __ALTERA_TSE_H__ */
> diff --git a/drivers/net/ethernet/altera/altera_tse_ethtool.c b/drivers/net/ethernet/altera/altera_tse_ethtool.c
> index 7c367713c3e6..2998655ab316 100644
> --- a/drivers/net/ethernet/altera/altera_tse_ethtool.c
> +++ b/drivers/net/ethernet/altera/altera_tse_ethtool.c
> @@ -33,6 +33,7 @@
>   #include <linux/phy.h>
>   
>   #include "altera_tse.h"
> +#include "altera_utils.h"
>   
>   #define TSE_STATS_LEN	31
>   #define TSE_NUM_REGS	128
> diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c
> index f6b6a14b1ce9..b25d03506470 100644
> --- a/drivers/net/ethernet/altera/altera_tse_main.c
> +++ b/drivers/net/ethernet/altera/altera_tse_main.c
> @@ -34,7 +34,6 @@
>   #include <linux/if_vlan.h>
>   #include <linux/init.h>
>   #include <linux/interrupt.h>
> -#include <linux/io.h>
>   #include <linux/kernel.h>
>   #include <linux/module.h>
>   #include <linux/mii.h>
> @@ -44,7 +43,7 @@
>   #include <linux/of_net.h>
>   #include <linux/of_platform.h>
>   #include <linux/phy.h>
> -#include <linux/platform_device.h>
> +#include <linux/ptp_classify.h>
>   #include <linux/skbuff.h>
>   #include <asm/cacheflush.h>
>   
> @@ -1332,35 +1331,6 @@ static struct net_device_ops altera_tse_netdev_ops = {
>   	.ndo_validate_addr	= eth_validate_addr,
>   };
>   
> -static int request_and_map(struct platform_device *pdev, const char *name,
> -			   struct resource **res, void __iomem **ptr)
> -{
> -	struct resource *region;
> -	struct device *device = &pdev->dev;
> -
> -	*res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
> -	if (*res == NULL) {
> -		dev_err(device, "resource %s not defined\n", name);
> -		return -ENODEV;
> -	}
> -
> -	region = devm_request_mem_region(device, (*res)->start,
> -					 resource_size(*res), dev_name(device));
> -	if (region == NULL) {
> -		dev_err(device, "unable to request %s\n", name);
> -		return -EBUSY;
> -	}
> -
> -	*ptr = devm_ioremap_nocache(device, region->start,
> -				    resource_size(region));
> -	if (*ptr == NULL) {
> -		dev_err(device, "ioremap_nocache of %s failed!", name);
> -		return -ENOMEM;
> -	}
> -
> -	return 0;
> -}
> -
>   /* Probe Altera TSE MAC device
>    */
>   static int altera_tse_probe(struct platform_device *pdev)
> diff --git a/drivers/net/ethernet/altera/altera_utils.c b/drivers/net/ethernet/altera/altera_utils.c
> index d7eeb1713ad2..bc33b7f0b0c5 100644
> --- a/drivers/net/ethernet/altera/altera_utils.c
> +++ b/drivers/net/ethernet/altera/altera_utils.c
> @@ -42,3 +42,33 @@ int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask)
>   	u32 value = csrrd32(ioaddr, offs);
>   	return (value & bit_mask) ? 0 : 1;
>   }
> +
> +int request_and_map(struct platform_device *pdev, const char *name,
> +		    struct resource **res, void __iomem **ptr)
> +{
> +	struct resource *region;
> +	struct device *device = &pdev->dev;
> +
> +	*res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
> +	if (!*res) {
> +		dev_err(device, "resource %s not defined\n", name);
> +		return -ENODEV;
> +	}
> +
> +	region = devm_request_mem_region(device, (*res)->start,
> +					 resource_size(*res), dev_name(device));
> +	if (!region) {
> +		dev_err(device, "unable to request %s\n", name);
> +		return -EBUSY;
> +	}
> +
> +	*ptr = devm_ioremap_nocache(device, region->start,
> +				    resource_size(region));
> +	if (!*ptr) {
> +		dev_err(device, "ioremap_nocache of %s failed!", name);
> +		return -ENOMEM;
> +	}
> +
> +	return 0;
> +}
> +
> diff --git a/drivers/net/ethernet/altera/altera_utils.h b/drivers/net/ethernet/altera/altera_utils.h
> index baf100ccf587..bb7eff792bb7 100644
> --- a/drivers/net/ethernet/altera/altera_utils.h
> +++ b/drivers/net/ethernet/altera/altera_utils.h
> @@ -14,7 +14,9 @@
>    * this program.  If not, see <http://www.gnu.org/licenses/>.
>    */
>   
> +#include <linux/io.h>
>   #include <linux/kernel.h>
> +#include <linux/platform_device.h>
>   
>   #ifndef __ALTERA_UTILS_H__
>   #define __ALTERA_UTILS_H__
> @@ -23,5 +25,49 @@ void tse_set_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask);
>   void tse_clear_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask);
>   int tse_bit_is_set(void __iomem *ioaddr, size_t offs, u32 bit_mask);
>   int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask);
> +int request_and_map(struct platform_device *pdev, const char *name,
> +		    struct resource **res, void __iomem **ptr);
> +
> +static inline u32 csrrd32(void __iomem *mac, size_t offs)
> +{
> +	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> +
> +	return readl(paddr);
> +}
> +
> +static inline u16 csrrd16(void __iomem *mac, size_t offs)
> +{
> +	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> +
> +	return readw(paddr);
> +}
> +
> +static inline u8 csrrd8(void __iomem *mac, size_t offs)
> +{
> +	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> +
> +	return readb(paddr);
> +}
> +
> +static inline void csrwr32(u32 val, void __iomem *mac, size_t offs)
> +{
> +	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> +
> +	writel(val, paddr);
> +}
> +
> +static inline void csrwr16(u16 val, void __iomem *mac, size_t offs)
> +{
> +	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> +
> +	writew(val, paddr);
> +}
> +
> +static inline void csrwr8(u8 val, void __iomem *mac, size_t offs)
> +{
> +	void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
> +
> +	writeb(val, paddr);
> +}
>   
>   #endif /* __ALTERA_UTILS_H__*/
> 
Acked-by: Thor Thayer <thor.thayer@linux.intel.com>

Re: [PATCH net-next 8/8] net: eth: altera: tse: update devicetree bindings documentation

[Thor Thayer]

+ Rob Herring, Mark Rutland and the Device Tree mailing list.

On 11/14/18 6:50 PM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Update devicetree bindings documentation to include msgdma
> prefetcher and ptp bindings.
> 
> Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> ---
>   .../devicetree/bindings/net/altera_tse.txt    | 98 +++++++++++++++----
>   1 file changed, 79 insertions(+), 19 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/altera_tse.txt b/Documentation/devicetree/bindings/net/altera_tse.txt
> index 0e21df94a53f..d35806942a8f 100644
> --- a/Documentation/devicetree/bindings/net/altera_tse.txt
> +++ b/Documentation/devicetree/bindings/net/altera_tse.txt
> @@ -2,50 +2,79 @@
>   
>   Required properties:
>   - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
> -		be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
> +		be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE,
> +		and "altr,tse-msgdma-2.0" for MSGDMA with prefetcher based
> +		implementations.
>   		ALTR is supported for legacy device trees, but is deprecated.
>   		altr should be used for all new designs.
>   - reg: Address and length of the register set for the device. It contains
>     the information of registers in the same order as described by reg-names
>   - reg-names: Should contain the reg names
> -  "control_port": MAC configuration space region
> -  "tx_csr":       xDMA Tx dispatcher control and status space region
> -  "tx_desc":      MSGDMA Tx dispatcher descriptor space region
> -  "rx_csr" :      xDMA Rx dispatcher control and status space region
> -  "rx_desc":      MSGDMA Rx dispatcher descriptor space region
> -  "rx_resp":      MSGDMA Rx dispatcher response space region
> -  "s1":		  SGDMA descriptor memory
>   - interrupts: Should contain the TSE interrupts and it's mode.
>   - interrupt-names: Should contain the interrupt names
> -  "rx_irq":       xDMA Rx dispatcher interrupt
> -  "tx_irq":       xDMA Tx dispatcher interrupt
> +  "rx_irq":       DMA Rx dispatcher interrupt
> +  "tx_irq":       DMA Tx dispatcher interrupt
>   - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
>   - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
>   - phy-mode: See ethernet.txt in the same directory.
>   - phy-handle: See ethernet.txt in the same directory.
>   - phy-addr: See ethernet.txt in the same directory. A configuration should
>   		include phy-handle or phy-addr.
> -- altr,has-supplementary-unicast:
> -		If present, TSE supports additional unicast addresses.
> -		Otherwise additional unicast addresses are not supported.
> -- altr,has-hash-multicast-filter:
> -		If present, TSE supports a hash based multicast filter.
> -		Otherwise, hash-based multicast filtering is not supported.
> -
>   - mdio device tree subnode: When the TSE has a phy connected to its local
>   		mdio, there must be device tree subnode with the following
>   		required properties:
> -
>   	- compatible: Must be "altr,tse-mdio".
>   	- #address-cells: Must be <1>.
>   	- #size-cells: Must be <0>.
>   
>   	For each phy on the mdio bus, there must be a node with the following
>   	fields:
> -
>   	- reg: phy id used to communicate to phy.
>   	- device_type: Must be "ethernet-phy".
>   
> +- altr,has-supplementary-unicast:
> +		If present, TSE supports additional unicast addresses.
> +		Otherwise additional unicast addresses are not supported.
> +- altr,has-hash-multicast-filter:
> +		If present, TSE supports a hash based multicast filter.
> +		Otherwise, hash-based multicast filtering is not supported.
> +- altr,has-ptp:
> +		If present, TSE supports 1588 timestamping.  Currently only
> +		supported with the msgdma prefetcher.
> +- altr,tx-poll-cnt:
> +		Optional cycle count for Tx prefetcher to poll descriptor
> +		list.  If not present, defaults to 128, which at 125MHz is
> +		roughly 1usec. Only for "altr,tse-msgdma-2.0".
> +- altr,rx-poll-cnt:
> +		Optional cycle count for Tx prefetcher to poll descriptor
> +		list.  If not present, defaults to 128, which at 125MHz is
> +		roughly 1usec. Only for "altr,tse-msgdma-2.0".
> +
> +Required registers by compatibility string:
> + - "altr,tse-1.0"
> +	"control_port": MAC configuration space region
> +	"tx_csr":       DMA Tx dispatcher control and status space region
> +	"rx_csr" :      DMA Rx dispatcher control and status space region
> +	"s1":		DMA descriptor memory
> +
> + - "altr,tse-msgdma-1.0"
> +	"control_port": MAC configuration space region
> +	"tx_csr":       DMA Tx dispatcher control and status space region
> +	"tx_desc":      DMA Tx dispatcher descriptor space region
> +	"rx_csr" :      DMA Rx dispatcher control and status space region
> +	"rx_desc":      DMA Rx dispatcher descriptor space region
> +	"rx_resp":      DMA Rx dispatcher response space region
> +
> + - "altr,tse-msgdma-2.0"
> +	"control_port": MAC configuration space region
> +	"tx_csr":       DMA Tx dispatcher control and status space region
> +	"tx_pref":      DMA Tx prefetcher configuration space region
> +	"rx_csr" :      DMA Rx dispatcher control and status space region
> +	"rx_pref":      DMA Rx prefetcher configuration space region
> +	"tod_ctrl":     Time of Day Control register only required when
> +			timestamping support is enabled.  Timestamping is
> +			only supported with the msgdma-2.0 implementation.
> +
>   Optional properties:
>   - local-mac-address: See ethernet.txt in the same directory.
>   - max-frame-size: See ethernet.txt in the same directory.
> @@ -87,6 +116,11 @@ Example:
>   				device_type = "ethernet-phy";
>   			};
>   
> +			phy2: ethernet-phy@2 {
> +				reg = <0x2>;
> +				device_type = "ethernet-phy";
> +			};
> +
>   		};
>   	};
>   
> @@ -112,3 +146,29 @@ Example:
>   		altr,has-hash-multicast-filter;
>   		phy-handle = <&phy1>;
>   	};
> +
> +	tse_sub_2_eth_tse_0: ethernet@1,00002000 {
> +		compatible = "altr,tse-msgdma-2.0";
> +		reg = 	<0x00000001 0x00002000 0x00000400>,
> +			<0x00000001 0x00002400 0x00000020>,
> +			<0x00000001 0x00002420 0x00000020>,
> +			<0x00000001 0x00002440 0x00000020>,
> +			<0x00000001 0x00002460 0x00000020>,
> +			<0x00000001 0x00002480 0x00000040>;
> +		reg-names = "control_port", "rx_csr", "rx_pref","tx_csr", "tx_pref", "tod_ctrl";
> +		interrupt-parent = <&hps_0_arm_gic_0>;
> +		interrupts = <0 45 4>, <0 44 4>;
> +		interrupt-names = "rx_irq", "tx_irq";
> +		rx-fifo-depth = <2048>;
> +		tx-fifo-depth = <2048>;
> +		address-bits = <48>;
> +		max-frame-size = <1500>;
> +		local-mac-address = [ 00 00 00 00 00 00 ];
> +		phy-mode = "sgmii";
> +		altr,has-supplementary-unicast;
> +		altr,has-hash-multicast-filter;
> +		altr,has-ptp;
> +		altr,tx-poll-cnt = <128>;
> +		altr,rx-poll-cnt = <32>;
> +		phy-handle = <&phy2>;
> +	};
> 

Re: [PATCH net-next 6/8] net: eth: altera: tse: add support for ptp and timestamping

[Richard Cochran]

On Thu, Nov 15, 2018 at 06:55:29AM -0800, Dalon Westergreen wrote:
> Sure, I would like to keep the debugfs entries for disabling freq correction,and
> reading the current scaled_ppm value.  I intend to use these to tune anexternal
> vcxo.  If there is a better way to do this, please let me know.

Yes, there is.  The external VCXO should be a proper PHC.  Then, with
a minor change to the linuxptp stack (already in the pipe), you can
just use that.

You should not disable frequency correction in the driver.  Leave that
decision to the user space PTP stack.

> I would prefer to keep altera just to be consistent with the altera_tse stuff,
> and i intend to reusethis code for a 10GbE driver, so perhaps altera_tod to
> reference the fpga ip name?

So the IP core is called "tod"?  Really?

Thanks,
Richard

Re: [PATCH net-next 6/8] net: eth: altera: tse: add support for ptp and timestamping

[Dalon Westergreen]

On Thu, 2018-11-15 at 18:14 -0800, Richard Cochran wrote:
> On Thu, Nov 15, 2018 at 06:55:29AM -0800, Dalon Westergreen wrote:
> > Sure, I would like to keep the debugfs entries for disabling freq
> > correction,and
> > reading the current scaled_ppm value.  I intend to use these to tune
> > anexternal
> > vcxo.  If there is a better way to do this, please let me know.
> 
> Yes, there is.  The external VCXO should be a proper PHC.  Then, with
> a minor change to the linuxptp stack (already in the pipe), you can
> just use that.
> 
> You should not disable frequency correction in the driver.  Leave that
> decision to the user space PTP stack.

Good to know, thanks.

> 
> > I would prefer to keep altera just to be consistent with the altera_tse
> > stuff,
> > and i intend to reusethis code for a 10GbE driver, so perhaps altera_tod to
> > reference the fpga ip name?
> 
> So the IP core is called "tod"?  Really?

yes, i am afraid so. "Time of Day"

--dalon

> 
> Thanks,
> Richard

Re: [PATCH net-next 6/8] net: eth: altera: tse: add support for ptp and timestamping

[Dalon Westergreen]

On Thu, 2018-11-15 at 18:14 -0800, Richard Cochran wrote:
> On Thu, Nov 15, 2018 at 06:55:29AM -0800, Dalon Westergreen wrote:
> > I would prefer to keep altera just to be consistent with the altera_tse
> > stuff,
> > and i intend to reusethis code for a 10GbE driver, so perhaps altera_tod to
> > reference the fpga ip name?
> 
> So the IP core is called "tod"?  Really?

For naming, how about intel_fpga_tod ?

--dalon

> 
> Thanks,
> Richard

Re: [PATCH net-next 7/8] net: eth: altera: tse: add msgdma prefetcher

[Thor Thayer]

Hi Dalon,

Just a few comments/questions.

On 11/14/18 6:50 PM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Add support for the mSGDMA prefetcher.  The prefetcher adds support
> for a linked list of descriptors in system memory.  The prefetcher
> feeds these to the mSGDMA dispatcher.
> 
> The prefetcher is configured to poll for the next descriptor in the
> list to be owned by hardware, then pass the descriptor to the
> dispatcher.  It will then poll the next descriptor until it is
> owned by hardware.
> 
> The dispatcher responses are written back to the appropriate
> descriptor, and the owned by hardware bit is cleared.
> 
> The driver sets up a linked list twice the tx and rx ring sizes,
> with the last descriptor pointing back to the first.  This ensures
> that the ring of descriptors will always have inactive descriptors
> preventing the prefetcher from looping over and reusing descriptors
> inappropriately.  The prefetcher will continuously loop over these
> descriptors.  The driver modifies descriptors as required to update
> the skb address and length as well as the owned by hardware bit.
> 
> In addition to the above, the mSGDMA prefetcher can be used to
> handle rx and tx timestamps coming from the ethernet ip.  These
> can be included in the prefetcher response in the descriptor.
> 
> Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> ---
>   drivers/net/ethernet/altera/Makefile          |   2 +-
>   .../altera/altera_msgdma_prefetcher.c         | 433 ++++++++++++++++++
>   .../altera/altera_msgdma_prefetcher.h         |  30 ++
>   .../altera/altera_msgdmahw_prefetcher.h       |  87 ++++
>   drivers/net/ethernet/altera/altera_tse.h      |  14 +
>   drivers/net/ethernet/altera/altera_tse_main.c |  51 +++
>   6 files changed, 616 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
>   create mode 100644 drivers/net/ethernet/altera/altera_msgdma_prefetcher.h
>   create mode 100644 drivers/net/ethernet/altera/altera_msgdmahw_prefetcher.h
> 
> diff --git a/drivers/net/ethernet/altera/Makefile b/drivers/net/ethernet/altera/Makefile
> index ad80be42fa26..73b32876f126 100644
> --- a/drivers/net/ethernet/altera/Makefile
> +++ b/drivers/net/ethernet/altera/Makefile
> @@ -5,4 +5,4 @@
>   obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
>   altera_tse-objs := altera_tse_main.o altera_tse_ethtool.o \
>   		   altera_msgdma.o altera_sgdma.o altera_utils.o \
> -		   altera_ptp.o
> +		   altera_ptp.o altera_msgdma_prefetcher.o
> diff --git a/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
> new file mode 100644
> index 000000000000..55b475e9e15b
> --- /dev/null
> +++ b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
> @@ -0,0 +1,433 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* MSGDMA Prefetcher driver for Altera ethernet devices
> + *
> + * Copyright (C) 2018 Intel Corporation. All rights reserved.
> + * Author(s):
> + *   Dalon Westergreen <dalon.westergreen@intel.com>
> + */
> +
> +#include <linux/list.h>
> +#include <linux/netdevice.h>
> +#include <linux/net_tstamp.h>
> +#include "altera_utils.h"
> +#include "altera_tse.h"
> +#include "altera_msgdma.h"
> +#include "altera_msgdmahw.h"
> +#include "altera_msgdma_prefetcher.h"
> +#include "altera_msgdmahw_prefetcher.h"

These could be alphabetized - tse and utils at the end.
> +
> +int msgdma_pref_initialize(struct altera_tse_private *priv)
> +{
> +	int i;
> +	struct msgdma_pref_extended_desc *rx_descs;
> +	struct msgdma_pref_extended_desc *tx_descs;
> +	dma_addr_t rx_descsphys;
> +	dma_addr_t tx_descsphys;
> +	u32 rx_ring_size;
> +	u32 tx_ring_size;
> +
> +	priv->pref_rxdescphys = (dma_addr_t)0;
> +	priv->pref_txdescphys = (dma_addr_t)0;
> +
> +	/* we need to allocate more pref descriptors than ringsize, for now
> +	 * just double ringsize
> +	 */
> +	rx_ring_size = priv->rx_ring_size * 2;
> +	tx_ring_size = priv->tx_ring_size * 2;
> +
> +	/* The prefetcher requires the descriptors to be aligned to the
> +	 * descriptor read/write master's data width which worst case is
> +	 * 512 bits.  Currently we DO NOT CHECK THIS and only support 32-bit
> +	 * prefetcher masters.
> +	 */
> +
> +	/* allocate memory for rx descriptors */
> +	priv->pref_rxdesc =
> +		dma_zalloc_coherent(priv->device,
> +				    sizeof(struct msgdma_pref_extended_desc)
> +				    * rx_ring_size,
> +				    &priv->pref_rxdescphys, GFP_KERNEL);
> +
> +	if (!priv->pref_rxdesc)
> +		goto err_rx;
> +
> +	/* allocate memory for tx descriptors */
> +	priv->pref_txdesc =
> +		dma_zalloc_coherent(priv->device,
> +				    sizeof(struct msgdma_pref_extended_desc)
> +				    * tx_ring_size,
> +				    &priv->pref_txdescphys, GFP_KERNEL);
> +
> +	if (!priv->pref_txdesc)
> +		goto err_tx;
> +
> +	/* setup base descriptor ring for tx & rx */
> +	rx_descs = (struct msgdma_pref_extended_desc *)priv->pref_rxdesc;
> +	tx_descs = (struct msgdma_pref_extended_desc *)priv->pref_txdesc;
> +	tx_descsphys = priv->pref_txdescphys;
> +	rx_descsphys = priv->pref_rxdescphys;
> +
> +	/* setup RX descriptors */
> +	priv->pref_rx_prod = 0;
> +	for (i = 0; i < rx_ring_size; i++) {
> +		rx_descsphys = priv->pref_rxdescphys +
> +			(((i + 1) % rx_ring_size) *
> +			sizeof(struct msgdma_pref_extended_desc));
> +		rx_descs[i].next_desc_lo = lower_32_bits(rx_descsphys);
> +		rx_descs[i].next_desc_hi = upper_32_bits(rx_descsphys);
> +		rx_descs[i].stride = MSGDMA_DESC_RX_STRIDE;
> +		/* burst set to 0 so it defaults to max configured */
> +		/* set seq number to desc number */
> +		rx_descs[i].burst_seq_num = i;
> +	}
> +
> +	/* setup TX descriptors */
> +	for (i = 0; i < tx_ring_size; i++) {
> +		tx_descsphys = priv->pref_txdescphys +
> +			(((i + 1) % tx_ring_size) *
> +			sizeof(struct msgdma_pref_extended_desc));
> +		tx_descs[i].next_desc_lo = lower_32_bits(tx_descsphys);
> +		tx_descs[i].next_desc_hi = upper_32_bits(tx_descsphys);
> +		tx_descs[i].stride = MSGDMA_DESC_TX_STRIDE;
> +		/* burst set to 0 so it defaults to max configured */
> +		/* set seq number to desc number */
> +		tx_descs[i].burst_seq_num = i;
> +	}
> +
> +	if (netif_msg_ifup(priv))
> +		netdev_info(priv->dev, "%s: RX Desc mem at 0x%x\n", __func__,
> +			    priv->pref_rxdescphys);
> +
> +	if (netif_msg_ifup(priv))
> +		netdev_info(priv->dev, "%s: TX Desc mem at 0x%x\n", __func__,
> +			    priv->pref_txdescphys);
> +
> +	return 0;
> +
> +err_tx:
> +	dma_free_coherent(priv->device,
> +			  sizeof(struct msgdma_pref_extended_desc)
> +			  * rx_ring_size,
> +			  priv->pref_rxdesc, priv->pref_rxdescphys);
> +err_rx:
> +	return -ENOMEM;
> +}
> +
> +void msgdma_pref_uninitialize(struct altera_tse_private *priv)
> +{
> +	if (priv->pref_rxdesc)
> +		dma_free_coherent(priv->device,
> +				  sizeof(struct msgdma_pref_extended_desc)
> +				  * priv->rx_ring_size * 2,
> +				  priv->pref_rxdesc, priv->pref_rxdescphys);
> +
> +	if (priv->pref_txdesc)
> +		dma_free_coherent(priv->device,
> +				  sizeof(struct msgdma_pref_extended_desc)
> +				  * priv->rx_ring_size * 2,
> +				  priv->pref_txdesc, priv->pref_txdescphys);

Why does this have the ring_size*2 but the error path in 
msgdma_pref_initialize() above (err_tx path) doesn't?

> +}
> +
> +void msgdma_pref_enable_txirq(struct altera_tse_private *priv)
> +{
> +	tse_set_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control),
> +		    MSGDMA_PREF_CTL_GLOBAL_INTR);
> +}
> +

<snip>

> +
> +void msgdma_pref_reset(struct altera_tse_private *priv)
> +{
> +	int counter;
> +
> +	/* turn off polling */
> +	tse_clear_bit(priv->rx_pref_csr, msgdma_pref_csroffs(control),
> +		      MSGDMA_PREF_CTL_DESC_POLL_EN);
> +	tse_clear_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control),
> +		      MSGDMA_PREF_CTL_DESC_POLL_EN);
> +
> +	/* Reset the RX Prefetcher */
> +	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->rx_pref_csr,
> +		msgdma_pref_csroffs(status));
> +	csrwr32(MSGDMA_PREF_CTL_RESET, priv->rx_pref_csr,
> +		msgdma_pref_csroffs(control));
> +
> +	counter = 0;
> +	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
> +		if (tse_bit_is_clear(priv->rx_pref_csr,
> +				     msgdma_pref_csroffs(control),
> +				     MSGDMA_PREF_CTL_RESET))
> +			break;
> +		udelay(1);
> +	}
> +
> +	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
> +		netif_warn(priv, drv, priv->dev,
> +			   "TSE Rx Prefetcher reset bit never cleared!\n");
> +
I take it there are no negative consequences for the reset bit not 
clearing? Would it be useful to return an error?

> +	/* clear all status bits */
> +	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr,
> +		msgdma_pref_csroffs(status));
> +

This looks the same as below. Are they the same or did I miss something?

> +	/* Reset the TX Prefetcher */
> +	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr,
> +		msgdma_pref_csroffs(status));
> +	csrwr32(MSGDMA_PREF_CTL_RESET, priv->tx_pref_csr,
> +		msgdma_pref_csroffs(control));
> +
> +	counter = 0;
> +	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
> +		if (tse_bit_is_clear(priv->tx_pref_csr,
> +				     msgdma_pref_csroffs(control),
> +				     MSGDMA_PREF_CTL_RESET))
> +			break;
> +		udelay(1);
> +	}
> +
> +	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
> +		netif_warn(priv, drv, priv->dev,
> +			   "TSE Tx Prefetcher reset bit never cleared!\n");
> +
Same as above.

> +	/* clear all status bits */
> +	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr,
> +		msgdma_pref_csroffs(status));
> +
> +	/* Reset mSGDMA dispatchers*/
> +	msgdma_reset(priv);
> +}
> +

<snip>

> +
> +/* Add MSGDMA Prefetcher Descriptor to descriptor list
> + *   -> This should never be called when a descriptor isn't available
> + */
> +void msgdma_pref_add_rx_desc(struct altera_tse_private *priv,
> +			     struct tse_buffer *rxbuffer)
> +{
> +	struct msgdma_pref_extended_desc *rx_descs = priv->pref_rxdesc;
> +	u32 desc_entry = priv->pref_rx_prod % (priv->rx_ring_size * 2);
> +
> +	/* write descriptor entries */
> +	rx_descs[desc_entry].len = priv->rx_dma_buf_sz;
> +	rx_descs[desc_entry].write_addr_lo = lower_32_bits(rxbuffer->dma_addr);
> +	rx_descs[desc_entry].write_addr_hi = upper_32_bits(rxbuffer->dma_addr);
> +
> +	/* set the control bits and set owned by hw */
> +	rx_descs[desc_entry].desc_control = (MSGDMA_DESC_CTL_END_ON_EOP
> +			| MSGDMA_DESC_CTL_END_ON_LEN
> +			| MSGDMA_DESC_CTL_TR_COMP_IRQ
> +			| MSGDMA_DESC_CTL_EARLY_IRQ
> +			| MSGDMA_DESC_CTL_TR_ERR_IRQ
> +			| MSGDMA_DESC_CTL_GO
> +			| MSGDMA_PREF_DESC_CTL_OWNED_BY_HW);
> +
> +	/* we need to keep a separate one for rx as RX_DESCRIPTORS are
> +	 * pre-configured at startup
> +	 */
> +	priv->pref_rx_prod++;

Can you explain more in the comment? What is "one"?

> +
> +	if (netif_msg_rx_status(priv)) {
> +		netdev_info(priv->dev, "%s: desc: %d buf: %d control 0x%x\n",
> +			    __func__, desc_entry,
> +			    priv->rx_prod % priv->rx_ring_size,
> +			    priv->pref_rxdesc[desc_entry].desc_control);
> +	}
> +}
> +

<snip>

Thanks for the patches!

Re: [PATCH net-next 6/8] net: eth: altera: tse: add support for ptp and timestamping

[Richard Cochran]

On Fri, Nov 16, 2018 at 06:48:15AM -0800, Dalon Westergreen wrote:
> For naming, how about intel_fpga_tod ?

Fine by me.

Thanks,
Richard

Re: [PATCH net-next 1/8] net: eth: altera: tse_start_xmit ignores tx_buffer call response

[David Miller]

From: Dalon Westergreen <dwesterg@gmail.com>
Date: Wed, 14 Nov 2018 16:50:40 -0800

> @@ -202,7 +204,7 @@ int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
>  	/* enqueue the request to the pending transmit queue */
>  	queue_tx(priv, buffer);
>  
> -	return 1;
> +	return 0;

NETDEV_TX_OK.

And now you can make all of these functions properly return netdev_tx_t instead of int.

Re: [PATCH net-next 1/8] net: eth: altera: tse_start_xmit ignores tx_buffer call response

[Westergreen, Dalon]

[-- Attachment #1: Type: text/plain, Size: 553 bytes --]

On Fri, 2018-11-16 at 20:38 -0800, David Miller wrote:
> From: Dalon Westergreen <dwesterg@gmail.com>
> Date: Wed, 14 Nov 2018 16:50:40 -0800
> 
> > @@ -202,7 +204,7 @@ int sgdma_tx_buffer(struct altera_tse_private *priv,
> struct tse_buffer *buffer)
> >       /* enqueue the request to the pending transmit queue */
> >       queue_tx(priv, buffer);
> >  
> > -     return 1;
> > +     return 0;
> 
> NETDEV_TX_OK.
> 
> And now you can make all of these functions properly return netdev_tx_t
> instead of int.

sure thing.

--dalon

[-- Attachment #2: smime.p7s --]
[-- Type: application/x-pkcs7-signature, Size: 3282 bytes --]

Re: [PATCH net-next 7/8] net: eth: altera: tse: add msgdma prefetcher

[Dalon Westergreen]

On Fri, 2018-11-16 at 09:20 -0600, Thor Thayer wrote:
> Hi Dalon,
> 
> Just a few comments/questions.
> 
> On 11/14/18 6:50 PM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <dalon.westergreen@intel.com>
> > 
> > Add support for the mSGDMA prefetcher.  The prefetcher adds support
> > for a linked list of descriptors in system memory.  The prefetcher
> > feeds these to the mSGDMA dispatcher.
> > 
> > The prefetcher is configured to poll for the next descriptor in the
> > list to be owned by hardware, then pass the descriptor to the
> > dispatcher.  It will then poll the next descriptor until it is
> > owned by hardware.
> > 
> > The dispatcher responses are written back to the appropriate
> > descriptor, and the owned by hardware bit is cleared.
> > 
> > The driver sets up a linked list twice the tx and rx ring sizes,
> > with the last descriptor pointing back to the first.  This ensures
> > that the ring of descriptors will always have inactive descriptors
> > preventing the prefetcher from looping over and reusing descriptors
> > inappropriately.  The prefetcher will continuously loop over these
> > descriptors.  The driver modifies descriptors as required to update
> > the skb address and length as well as the owned by hardware bit.
> > 
> > In addition to the above, the mSGDMA prefetcher can be used to
> > handle rx and tx timestamps coming from the ethernet ip.  These
> > can be included in the prefetcher response in the descriptor.
> > 
> > Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> > ---
> >   drivers/net/ethernet/altera/Makefile          |   2 +-
> >   .../altera/altera_msgdma_prefetcher.c         | 433 ++++++++++++++++++
> >   .../altera/altera_msgdma_prefetcher.h         |  30 ++
> >   .../altera/altera_msgdmahw_prefetcher.h       |  87 ++++
> >   drivers/net/ethernet/altera/altera_tse.h      |  14 +
> >   drivers/net/ethernet/altera/altera_tse_main.c |  51 +++
> >   6 files changed, 616 insertions(+), 1 deletion(-)
> >   create mode 100644 drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
> >   create mode 100644 drivers/net/ethernet/altera/altera_msgdma_prefetcher.h
> >   create mode 100644
> > drivers/net/ethernet/altera/altera_msgdmahw_prefetcher.h
> > 
> > diff --git a/drivers/net/ethernet/altera/Makefile
> > b/drivers/net/ethernet/altera/Makefile
> > index ad80be42fa26..73b32876f126 100644
> > --- a/drivers/net/ethernet/altera/Makefile
> > +++ b/drivers/net/ethernet/altera/Makefile
> > @@ -5,4 +5,4 @@
> >   obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
> >   altera_tse-objs := altera_tse_main.o altera_tse_ethtool.o \
> >   		   altera_msgdma.o altera_sgdma.o altera_utils.o \
> > -		   altera_ptp.o
> > +		   altera_ptp.o altera_msgdma_prefetcher.o
> > diff --git a/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
> > b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
> > new file mode 100644
> > index 000000000000..55b475e9e15b
> > --- /dev/null
> > +++ b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
> > @@ -0,0 +1,433 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/* MSGDMA Prefetcher driver for Altera ethernet devices
> > + *
> > + * Copyright (C) 2018 Intel Corporation. All rights reserved.
> > + * Author(s):
> > + *   Dalon Westergreen <dalon.westergreen@intel.com>
> > + */
> > +
> > +#include <linux/list.h>
> > +#include <linux/netdevice.h>
> > +#include <linux/net_tstamp.h>
> > +#include "altera_utils.h"
> > +#include "altera_tse.h"
> > +#include "altera_msgdma.h"
> > +#include "altera_msgdmahw.h"
> > +#include "altera_msgdma_prefetcher.h"
> > +#include "altera_msgdmahw_prefetcher.h"
> 
> These could be alphabetized - tse and utils at the end.

sure thing.

> > +
> > +int msgdma_pref_initialize(struct altera_tse_private *priv)
> > +{
> > +	int i;
> > +	struct msgdma_pref_extended_desc *rx_descs;
> > +	struct msgdma_pref_extended_desc *tx_descs;
> > +	dma_addr_t rx_descsphys;
> > +	dma_addr_t tx_descsphys;
> > +	u32 rx_ring_size;
> > +	u32 tx_ring_size;
> > +
> > +	priv->pref_rxdescphys = (dma_addr_t)0;
> > +	priv->pref_txdescphys = (dma_addr_t)0;
> > +
> > +	/* we need to allocate more pref descriptors than ringsize, for now
> > +	 * just double ringsize
> > +	 */
> > +	rx_ring_size = priv->rx_ring_size * 2;
> > +	tx_ring_size = priv->tx_ring_size * 2;
> > +
> > +	/* The prefetcher requires the descriptors to be aligned to the
> > +	 * descriptor read/write master's data width which worst case is
> > +	 * 512 bits.  Currently we DO NOT CHECK THIS and only support 32-bit
> > +	 * prefetcher masters.
> > +	 */
> > +
> > +	/* allocate memory for rx descriptors */
> > +	priv->pref_rxdesc =
> > +		dma_zalloc_coherent(priv->device,
> > +				    sizeof(struct msgdma_pref_extended_desc)
> > +				    * rx_ring_size,
> > +				    &priv->pref_rxdescphys, GFP_KERNEL);
> > +
> > +	if (!priv->pref_rxdesc)
> > +		goto err_rx;
> > +
> > +	/* allocate memory for tx descriptors */
> > +	priv->pref_txdesc =
> > +		dma_zalloc_coherent(priv->device,
> > +				    sizeof(struct msgdma_pref_extended_desc)
> > +				    * tx_ring_size,
> > +				    &priv->pref_txdescphys, GFP_KERNEL);
> > +
> > +	if (!priv->pref_txdesc)
> > +		goto err_tx;
> > +
> > +	/* setup base descriptor ring for tx & rx */
> > +	rx_descs = (struct msgdma_pref_extended_desc *)priv->pref_rxdesc;
> > +	tx_descs = (struct msgdma_pref_extended_desc *)priv->pref_txdesc;
> > +	tx_descsphys = priv->pref_txdescphys;
> > +	rx_descsphys = priv->pref_rxdescphys;
> > +
> > +	/* setup RX descriptors */
> > +	priv->pref_rx_prod = 0;
> > +	for (i = 0; i < rx_ring_size; i++) {
> > +		rx_descsphys = priv->pref_rxdescphys +
> > +			(((i + 1) % rx_ring_size) *
> > +			sizeof(struct msgdma_pref_extended_desc));
> > +		rx_descs[i].next_desc_lo = lower_32_bits(rx_descsphys);
> > +		rx_descs[i].next_desc_hi = upper_32_bits(rx_descsphys);
> > +		rx_descs[i].stride = MSGDMA_DESC_RX_STRIDE;
> > +		/* burst set to 0 so it defaults to max configured */
> > +		/* set seq number to desc number */
> > +		rx_descs[i].burst_seq_num = i;
> > +	}
> > +
> > +	/* setup TX descriptors */
> > +	for (i = 0; i < tx_ring_size; i++) {
> > +		tx_descsphys = priv->pref_txdescphys +
> > +			(((i + 1) % tx_ring_size) *
> > +			sizeof(struct msgdma_pref_extended_desc));
> > +		tx_descs[i].next_desc_lo = lower_32_bits(tx_descsphys);
> > +		tx_descs[i].next_desc_hi = upper_32_bits(tx_descsphys);
> > +		tx_descs[i].stride = MSGDMA_DESC_TX_STRIDE;
> > +		/* burst set to 0 so it defaults to max configured */
> > +		/* set seq number to desc number */
> > +		tx_descs[i].burst_seq_num = i;
> > +	}
> > +
> > +	if (netif_msg_ifup(priv))
> > +		netdev_info(priv->dev, "%s: RX Desc mem at 0x%x\n", __func__,
> > +			    priv->pref_rxdescphys);
> > +
> > +	if (netif_msg_ifup(priv))
> > +		netdev_info(priv->dev, "%s: TX Desc mem at 0x%x\n", __func__,
> > +			    priv->pref_txdescphys);
> > +
> > +	return 0;
> > +
> > +err_tx:
> > +	dma_free_coherent(priv->device,
> > +			  sizeof(struct msgdma_pref_extended_desc)
> > +			  * rx_ring_size,
> > +			  priv->pref_rxdesc, priv->pref_rxdescphys);
> > +err_rx:
> > +	return -ENOMEM;
> > +}
> > +
> > +void msgdma_pref_uninitialize(struct altera_tse_private *priv)
> > +{
> > +	if (priv->pref_rxdesc)
> > +		dma_free_coherent(priv->device,
> > +				  sizeof(struct msgdma_pref_extended_desc)
> > +				  * priv->rx_ring_size * 2,
> > +				  priv->pref_rxdesc, priv->pref_rxdescphys);
> > +
> > +	if (priv->pref_txdesc)
> > +		dma_free_coherent(priv->device,
> > +				  sizeof(struct msgdma_pref_extended_desc)
> > +				  * priv->rx_ring_size * 2,
> > +				  priv->pref_txdesc, priv->pref_txdescphys);
> 
> Why does this have the ring_size*2 but the error path in 
> msgdma_pref_initialize() above (err_tx path) doesn't?

The msgdma_pref_initialize uses a local rx_ring_size which is already 2 *
priv->rx_ring_size.  i'll just make it more clear and fix the other error
above where priv->rx_ring_size is being used for the tx_ring_size.

> 
> > +}
> > +
> > +void msgdma_pref_enable_txirq(struct altera_tse_private *priv)
> > +{
> > +	tse_set_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control),
> > +		    MSGDMA_PREF_CTL_GLOBAL_INTR);
> > +}
> > +
> 
> <snip>
> 
> > +
> > +void msgdma_pref_reset(struct altera_tse_private *priv)
> > +{
> > +	int counter;
> > +
> > +	/* turn off polling */
> > +	tse_clear_bit(priv->rx_pref_csr, msgdma_pref_csroffs(control),
> > +		      MSGDMA_PREF_CTL_DESC_POLL_EN);
> > +	tse_clear_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control),
> > +		      MSGDMA_PREF_CTL_DESC_POLL_EN);
> > +
> > +	/* Reset the RX Prefetcher */
> > +	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->rx_pref_csr,
> > +		msgdma_pref_csroffs(status));
> > +	csrwr32(MSGDMA_PREF_CTL_RESET, priv->rx_pref_csr,
> > +		msgdma_pref_csroffs(control));
> > +
> > +	counter = 0;
> > +	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
> > +		if (tse_bit_is_clear(priv->rx_pref_csr,
> > +				     msgdma_pref_csroffs(control),
> > +				     MSGDMA_PREF_CTL_RESET))
> > +			break;
> > +		udelay(1);
> > +	}
> > +
> > +	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
> > +		netif_warn(priv, drv, priv->dev,
> > +			   "TSE Rx Prefetcher reset bit never cleared!\n");
> > +
> I take it there are no negative consequences for the reset bit not 
> clearing? Would it be useful to return an error?

I will look into what i can do with this, it is no different than the
currently implemented msgdma code, not that that is an excuse. 

> 
> > +	/* clear all status bits */
> > +	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr,
> > +		msgdma_pref_csroffs(status));
> > +
> 
> This looks the same as below. Are they the same or did I miss something?

nope, that's an error. thanks.

> 
> > +	/* Reset the TX Prefetcher */
> > +	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr,
> > +		msgdma_pref_csroffs(status));
> > +	csrwr32(MSGDMA_PREF_CTL_RESET, priv->tx_pref_csr,
> > +		msgdma_pref_csroffs(control));
> > +
> > +	counter = 0;
> > +	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
> > +		if (tse_bit_is_clear(priv->tx_pref_csr,
> > +				     msgdma_pref_csroffs(control),
> > +				     MSGDMA_PREF_CTL_RESET))
> > +			break;
> > +		udelay(1);
> > +	}
> > +
> > +	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
> > +		netif_warn(priv, drv, priv->dev,
> > +			   "TSE Tx Prefetcher reset bit never cleared!\n");
> > +
> Same as above.
> 
> > +	/* clear all status bits */
> > +	csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr,
> > +		msgdma_pref_csroffs(status));
> > +
> > +	/* Reset mSGDMA dispatchers*/
> > +	msgdma_reset(priv);
> > +}
> > +
> 
> <snip>
> 
> > +
> > +/* Add MSGDMA Prefetcher Descriptor to descriptor list
> > + *   -> This should never be called when a descriptor isn't available
> > + */
> > +void msgdma_pref_add_rx_desc(struct altera_tse_private *priv,
> > +			     struct tse_buffer *rxbuffer)
> > +{
> > +	struct msgdma_pref_extended_desc *rx_descs = priv->pref_rxdesc;
> > +	u32 desc_entry = priv->pref_rx_prod % (priv->rx_ring_size * 2);
> > +
> > +	/* write descriptor entries */
> > +	rx_descs[desc_entry].len = priv->rx_dma_buf_sz;
> > +	rx_descs[desc_entry].write_addr_lo = lower_32_bits(rxbuffer->dma_addr);
> > +	rx_descs[desc_entry].write_addr_hi = upper_32_bits(rxbuffer->dma_addr);
> > +
> > +	/* set the control bits and set owned by hw */
> > +	rx_descs[desc_entry].desc_control = (MSGDMA_DESC_CTL_END_ON_EOP
> > +			| MSGDMA_DESC_CTL_END_ON_LEN
> > +			| MSGDMA_DESC_CTL_TR_COMP_IRQ
> > +			| MSGDMA_DESC_CTL_EARLY_IRQ
> > +			| MSGDMA_DESC_CTL_TR_ERR_IRQ
> > +			| MSGDMA_DESC_CTL_GO
> > +			| MSGDMA_PREF_DESC_CTL_OWNED_BY_HW);
> > +
> > +	/* we need to keep a separate one for rx as RX_DESCRIPTORS are
> > +	 * pre-configured at startup
> > +	 */
> > +	priv->pref_rx_prod++;
> 
> Can you explain more in the comment? What is "one"?

i will clean up the comment.  The rx path keeps it's own copy
of pref_rx_prod as the pref ring size is 2 * tse ring size.  I'll
also see how tricky it is to get rid of this copy.

> 
> > +
> > +	if (netif_msg_rx_status(priv)) {
> > +		netdev_info(priv->dev, "%s: desc: %d buf: %d control 0x%x\n",
> > +			    __func__, desc_entry,
> > +			    priv->rx_prod % priv->rx_ring_size,
> > +			    priv->pref_rxdesc[desc_entry].desc_control);
> > +	}
> > +}
> > +
> 
> <snip>
> 
> Thanks for the patches!

Nope, thank you for looking them over.