From: Fenghua Yu <fenghua.yu@intel.com>
To: Ingo Molnar <mingo@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
H Peter Anvin <hpa@zytor.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Dave Hansen <dave.hansen@intel.com>,
Ashok Raj <ashok.raj@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Christopherson Sean J <sean.j.christopherson@intel.com>,
Kalle Valo <kvalo@codeaurora.org>,
Michael Chan <michael.chan@broadcom.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>,
kvm@vger.kernel.org, netdev@vger.kernel.org,
linux-wireless@vger.kernel.org
Subject: Re: [PATCH v8 09/15] x86/split_lock: Define MSR TEST_CTL register
Date: Thu, 25 Apr 2019 12:48:09 -0700 [thread overview]
Message-ID: <20190425194808.GB64477@romley-ivt3.sc.intel.com> (raw)
In-Reply-To: <20190425062126.GC40105@gmail.com>
On Thu, Apr 25, 2019 at 08:21:26AM +0200, Ingo Molnar wrote:
>
> * Fenghua Yu <fenghua.yu@intel.com> wrote:
>
> > Setting bit 29 in MSR TEST_CTL (0x33) enables split lock detection and
> > clearing the bit disables split lock detection.
> >
> > Define the MSR and the bit. The definitions will be used in enabling or
> > disabling split lock detection.
> >
> > Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> > ---
> > arch/x86/include/asm/msr-index.h | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> > index f65ef6f783d2..296eeb761ab6 100644
> > --- a/arch/x86/include/asm/msr-index.h
> > +++ b/arch/x86/include/asm/msr-index.h
> > @@ -39,6 +39,10 @@
> >
> > /* Intel MSRs. Some also available on other CPUs */
> >
> > +#define MSR_TEST_CTL 0x00000033
> > +#define TEST_CTL_SPLIT_LOCK_DETECT_SHIFT 29
> > +#define TEST_CTL_SPLIT_LOCK_DETECT BIT(29)
>
> Three problems:
>
> - Is MSR_TEST_CTL is not really a canonical MSR name... A quick look at
> msr-index reveals the prevailing nomenclature:
>
> dagon:~/tip> git grep -h 'define MSR' arch/x86/include/asm/msr-index.h | cut -d_ -f1-2 | sort -n | uniq -c | sort -n | tail -10
> 8 #define MSR_K8
> 8 #define MSR_MTRRfix4K
> 12 #define MSR_CORE
> 13 #define MSR_IDT
> 14 #define MSR_K7
> 16 #define MSR_PKG
> 19 #define MSR_F15H
> 33 #define MSR_AMD64
> 83 #define MSR_P4
> 163 #define MSR_IA32
>
> I.e. this shouldn't this be something like MSR_IA32_TEST_CTL - or this
> the name the Intel SDM uses? (I haven't checked.)
TEST_CTL is the MSR's exact name shown in Table 2-14 in the latest SDM.
https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4
So can I still use MSR_TEST_CTL here?
>
> - The canonical way to define MSR capabilities is to use the MSR's name
> as a prefix. I.e.:
>
> MSR_TEST_CTL
> MSR_TEST_CTL_SPLIT_LOCK_DETECT_BIT
> MSR_TEST_CTL_SPLIT_LOCK_DETECT
> etc.
>
> Instead of the random mixture of MSR_ prefixed and non-prefixed
> MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT and
> TEST_CTL_SPLIT_LOCK_DETECT names.
>
> - Finally, this is not how we define bits - the _SHIFT postfix is actively
> confusing as we usually denote _SHIFT values with something that is
> used in a bit-shift operation, which this isn't. Instead the proper
> scheme is to postfix the bit number with _BIT and the mask with _MASK,
> i.e. something like:
>
> #define MSR_TEST_CTL 0x00000033
> #define MSR_TEST_CTL_SPLIT_LOCK_DETECT_BIT 29
> #define MSR_TEST_CTL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTL_SPLIT_LOCK_DETECT_BIT)
>
> Note how this cleans up actual usage:
>
> + msr_set_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT);
> + this_cpu_or(msr_test_ctl_cache, TEST_CTL_SPLIT_LOCK_DETECT);
>
> - msr_set_bit(MSR_TEST_CTL, MSR_TEST_CTL_SPLIT_LOCK_DETECT_BIT);
> - this_cpu_or(msr_test_ctl_cache, MSR_TEST_CTL_SPLIT_LOCK_DETECT);
>
> Frankly, this kind of disorganized code in a v8 submission is *really*
> disappointing, it's not like it's hard to look up these patterns and
> practices in existing code...
OK. Will change the bit and mask definitions.
Thanks.
-Fenghua
next prev parent reply other threads:[~2019-04-25 19:56 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-24 19:32 [PATCH v8 00/15] x86/split_lock: Enable split lock detection Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 01/15] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 02/15] drivers/net/b44: Align pwol_mask to unsigned long for better performance Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 03/15] wlcore: simplify/fix/optimize reg_ch_conf_pending operations Fenghua Yu
2019-04-25 17:12 ` Kalle Valo
2019-04-24 19:32 ` [PATCH v8 04/15] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 05/15] x86/msr-index: Define MSR_IA32_CORE_CAPABILITY and split lock detection bit Fenghua Yu
2019-04-25 5:45 ` Ingo Molnar
2019-04-25 19:01 ` Fenghua Yu
2019-04-25 19:47 ` Ingo Molnar
2019-04-25 19:51 ` Fenghua Yu
2019-04-25 20:08 ` Ingo Molnar
2019-04-25 20:22 ` Fenghua Yu
2019-04-26 6:00 ` Ingo Molnar
2019-05-06 0:12 ` Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 06/15] x86/cpufeatures: Enumerate MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 07/15] x86/split_lock: Enumerate split lock detection by MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 08/15] x86/split_lock: Enumerate split lock detection on Icelake mobile processor Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 09/15] x86/split_lock: Define MSR TEST_CTL register Fenghua Yu
2019-04-25 6:21 ` Ingo Molnar
2019-04-25 19:48 ` Fenghua Yu [this message]
2019-04-24 19:32 ` [PATCH v8 10/15] x86/split_lock: Handle #AC exception for split lock Fenghua Yu
2019-04-25 6:07 ` Ingo Molnar
2019-04-25 7:29 ` Thomas Gleixner
2019-04-24 19:32 ` [PATCH v8 11/15] kvm/x86: Emulate MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 12/15] kvm/vmx: Emulate MSR TEST_CTL Fenghua Yu
2019-04-25 7:42 ` Thomas Gleixner
2019-04-27 12:20 ` Xiaoyao Li
2019-04-28 7:09 ` Thomas Gleixner
2019-04-28 7:34 ` Xiaoyao Li
2019-04-29 7:31 ` Thomas Gleixner
2019-04-29 5:21 ` Xiaoyao Li
2019-04-24 19:33 ` [PATCH v8 13/15] x86/split_lock: Enable split lock detection by default Fenghua Yu
2019-04-25 7:50 ` Thomas Gleixner
2019-05-06 21:39 ` Fenghua Yu
2019-04-25 10:52 ` David Laight
2019-04-25 10:58 ` Thomas Gleixner
2019-04-25 11:13 ` David Laight
2019-04-25 11:41 ` Peter Zijlstra
2019-04-25 13:04 ` Thomas Gleixner
2019-05-07 20:48 ` Fenghua Yu
2019-04-24 19:33 ` [PATCH v8 14/15] x86/split_lock: Disable split lock detection by kernel parameter "nosplit_lock_detect" Fenghua Yu
2019-04-24 19:33 ` [PATCH v8 15/15] x86/split_lock: Add a sysfs interface to enable/disable split lock detection during run time Fenghua Yu
2019-04-25 6:31 ` Ingo Molnar
2019-05-06 0:21 ` Fenghua Yu
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