From: Fenghua Yu <fenghua.yu@intel.com>
To: Ingo Molnar <mingo@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
H Peter Anvin <hpa@zytor.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Dave Hansen <dave.hansen@intel.com>,
Ashok Raj <ashok.raj@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Christopherson Sean J <sean.j.christopherson@intel.com>,
Kalle Valo <kvalo@codeaurora.org>,
Michael Chan <michael.chan@broadcom.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>,
kvm@vger.kernel.org, netdev@vger.kernel.org,
linux-wireless@vger.kernel.org
Subject: Re: [PATCH v8 05/15] x86/msr-index: Define MSR_IA32_CORE_CAPABILITY and split lock detection bit
Date: Sun, 5 May 2019 17:12:21 -0700 [thread overview]
Message-ID: <20190506001219.GA110479@romley-ivt3.sc.intel.com> (raw)
In-Reply-To: <20190426060010.GB122831@gmail.com>
On Fri, Apr 26, 2019 at 08:00:10AM +0200, Ingo Molnar wrote:
>
> * Fenghua Yu <fenghua.yu@intel.com> wrote:
>
> > On Thu, Apr 25, 2019 at 10:08:30PM +0200, Ingo Molnar wrote:
> > >
> > > * Fenghua Yu <fenghua.yu@intel.com> wrote:
> > >
> > > > On Thu, Apr 25, 2019 at 09:47:14PM +0200, Ingo Molnar wrote:
> > > > >
> > > > > * Fenghua Yu <fenghua.yu@intel.com> wrote:
> > > > >
> > > > > > On Thu, Apr 25, 2019 at 07:45:11AM +0200, Ingo Molnar wrote:
> > > > > > >
> > > > > > > * Fenghua Yu <fenghua.yu@intel.com> wrote:
> > > > > > >
> > > > > > > > A new MSR_IA32_CORE_CAPABILITY (0xcf) is defined. Each bit in the MSR
> > > > > > > > enumerates a model specific feature. Currently bit 5 enumerates split
> > > > > > > > lock detection. When bit 5 is 1, split lock detection is supported.
> > > > > > > > When the bit is 0, split lock detection is not supported.
> > > > > > > >
> > > > > > > > Please check the latest Intel 64 and IA-32 Architectures Software
> > > > > > > > Developer's Manual for more detailed information on the MSR and the
> > > > > > > > split lock detection bit.
> > > > > > > >
> > > > > > > > Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> > > > > > > > ---
> > > > > > > > arch/x86/include/asm/msr-index.h | 3 +++
> > > > > > > > 1 file changed, 3 insertions(+)
> > > > > > > >
> > > > > > > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> > > > > > > > index ca5bc0eacb95..f65ef6f783d2 100644
> > > > > > > > --- a/arch/x86/include/asm/msr-index.h
> > > > > > > > +++ b/arch/x86/include/asm/msr-index.h
> > > > > > > > @@ -59,6 +59,9 @@
> > > > > > > > #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
> > > > > > > > #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
> > > > > > > >
> > > > > > > > +#define MSR_IA32_CORE_CAPABILITY 0x000000cf
> > > > > > > > +#define CORE_CAP_SPLIT_LOCK_DETECT BIT(5) /* Detect split lock */
> > > > > > >
> > > > > > > Please don't put comments into definitions.
> > > > > >
> > > > > > I'll remove the comment and change definitions of the MSR and the split lock
> > > > > > detection bit as following:
> > > > > >
> > > > > > +#define MSR_IA32_CORE_CAPABILITY 0x000000cf
> > > > > > +#define MSR_IA32_CORE_CAPABILITY_SPLIT_LOCK_DETECT_BIT 5
> > > > > > +#define MSR_IA32_CORE_CAPABILITY_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPABILITY_SPLIT_LOCK_DETECT_BIT)
> > > > > >
> > > > > > Are these right changes?
> > > > >
> > > > > I suspect it could be shortened to CORE_CAP as you (partly) did it
> > > > > originally.
> > > >
> > > > IA32_CORE_CAPABILITY is the MSR's exact name in the latest SDM (in Table 2-14):
> > > > https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4
> > > >
> > > > So can I define the MSR and the bits as follows?
> > > >
> > > > +#define MSR_IA32_CORE_CAP 0x000000cf
> > > > +#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT_BIT 5
> > > > +#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT_BIT)
> > >
> > > Yeah, I suppose that looks OK.
> >
> > Should I also change the feature definition 'X86_FEATURE_CORE_CAPABILITY' to
> > 'X86_FEATURE_CORE_CAP' in cpufeatures.h in patch #0006 to match the
> > MSR definition here? Or should I still keep the current feature definition?
> >
> > Thanks.
>
> Hm, no, for CPU features it's good to follow the vendor convention.
>
> So I guess the long-form CPU_CAPABILITY for all of these is the best
> after all.
Since MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT_BIT is not used anywhere else
except in this patch, is it OK not to define this macro?
So this patch will only has two shorter lines:
+#define MSR_IA32_CORE_CAP 0x000000cf
+#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT BIT(5)
Is this OK for this patch to only define these two macros?
Thanks.
-Fenghua
next prev parent reply other threads:[~2019-05-06 0:20 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-24 19:32 [PATCH v8 00/15] x86/split_lock: Enable split lock detection Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 01/15] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 02/15] drivers/net/b44: Align pwol_mask to unsigned long for better performance Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 03/15] wlcore: simplify/fix/optimize reg_ch_conf_pending operations Fenghua Yu
2019-04-25 17:12 ` Kalle Valo
2019-04-24 19:32 ` [PATCH v8 04/15] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 05/15] x86/msr-index: Define MSR_IA32_CORE_CAPABILITY and split lock detection bit Fenghua Yu
2019-04-25 5:45 ` Ingo Molnar
2019-04-25 19:01 ` Fenghua Yu
2019-04-25 19:47 ` Ingo Molnar
2019-04-25 19:51 ` Fenghua Yu
2019-04-25 20:08 ` Ingo Molnar
2019-04-25 20:22 ` Fenghua Yu
2019-04-26 6:00 ` Ingo Molnar
2019-05-06 0:12 ` Fenghua Yu [this message]
2019-04-24 19:32 ` [PATCH v8 06/15] x86/cpufeatures: Enumerate MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 07/15] x86/split_lock: Enumerate split lock detection by MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 08/15] x86/split_lock: Enumerate split lock detection on Icelake mobile processor Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 09/15] x86/split_lock: Define MSR TEST_CTL register Fenghua Yu
2019-04-25 6:21 ` Ingo Molnar
2019-04-25 19:48 ` Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 10/15] x86/split_lock: Handle #AC exception for split lock Fenghua Yu
2019-04-25 6:07 ` Ingo Molnar
2019-04-25 7:29 ` Thomas Gleixner
2019-04-24 19:32 ` [PATCH v8 11/15] kvm/x86: Emulate MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-04-24 19:32 ` [PATCH v8 12/15] kvm/vmx: Emulate MSR TEST_CTL Fenghua Yu
2019-04-25 7:42 ` Thomas Gleixner
2019-04-27 12:20 ` Xiaoyao Li
2019-04-28 7:09 ` Thomas Gleixner
2019-04-28 7:34 ` Xiaoyao Li
2019-04-29 7:31 ` Thomas Gleixner
2019-04-29 5:21 ` Xiaoyao Li
2019-04-24 19:33 ` [PATCH v8 13/15] x86/split_lock: Enable split lock detection by default Fenghua Yu
2019-04-25 7:50 ` Thomas Gleixner
2019-05-06 21:39 ` Fenghua Yu
2019-04-25 10:52 ` David Laight
2019-04-25 10:58 ` Thomas Gleixner
2019-04-25 11:13 ` David Laight
2019-04-25 11:41 ` Peter Zijlstra
2019-04-25 13:04 ` Thomas Gleixner
2019-05-07 20:48 ` Fenghua Yu
2019-04-24 19:33 ` [PATCH v8 14/15] x86/split_lock: Disable split lock detection by kernel parameter "nosplit_lock_detect" Fenghua Yu
2019-04-24 19:33 ` [PATCH v8 15/15] x86/split_lock: Add a sysfs interface to enable/disable split lock detection during run time Fenghua Yu
2019-04-25 6:31 ` Ingo Molnar
2019-05-06 0:21 ` Fenghua Yu
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